Struct SYSOSCFCLCTL_SPEC 

pub struct SYSOSCFCLCTL_SPEC;

SYSOSC frequency correction loop (FCL) ROSC enable

You can reset, write, write_with_zero this register using sysoscfclctl::W. See API.

Trait Implementations

impl RegisterSpec for SYSOSCFCLCTL_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for SYSOSCFCLCTL_SPEC

reset() method sets SYSOSCFCLCTL to value 0

const RESET_VALUE: Self::Ux = {transmute(0x00000000): <sysctl::sysoscfclctl::SYSOSCFCLCTL_SPEC as generic::RegisterSpec>::Ux}

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for SYSOSCFCLCTL_SPEC

write(|w| ..) method takes sysoscfclctl::W writer structure

const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <sysctl::sysoscfclctl::SYSOSCFCLCTL_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <sysctl::sysoscfclctl::SYSOSCFCLCTL_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1