Enum msp432p401r::dma::dma_enaclr::CLR_AW
source · [−]#[repr(u32)]
pub enum CLR_AW {
CLR_0,
CLR_1,
}
Expand description
Set the appropriate bit to disable the corresponding DMA channel. Note: The controller disables a channel, by setting the appropriate bit, when: a) it completes the DMA cycle b) it reads a channel_cfg memory location which has cycle_ctrl = b000 c) an ERROR occurs on the AHB-Lite bus.
Value on reset: 0
Variants
CLR_0
0: No effect. Use the DMA_ENASET Register to enable DMA channels.
CLR_1
1: Disables channel C. Writing to a bit where a DMA channel is not implemented has no effect.
Trait Implementations
impl Copy for CLR_AW
impl StructuralPartialEq for CLR_AW
Auto Trait Implementations
impl RefUnwindSafe for CLR_AW
impl Send for CLR_AW
impl Sync for CLR_AW
impl Unpin for CLR_AW
impl UnwindSafe for CLR_AW
Blanket Implementations
sourceimpl<T> BorrowMut<T> for T where
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
const: unstable · sourcefn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more