Struct msp430fr6972::dma::RegisterBlock[−][src]

#[repr(C)]
pub struct RegisterBlock {
Show fields
    pub dmactl0: Reg<DMACTL0_SPEC>,
    pub dmactl1: Reg<DMACTL1_SPEC>,
    pub dmactl2: Reg<DMACTL2_SPEC>,
    pub dmactl3: Reg<DMACTL3_SPEC>,
    pub dmactl4: Reg<DMACTL4_SPEC>,
    pub dmaiv: Reg<DMAIV_SPEC>,
    pub dma0ctl: Reg<DMA0CTL_SPEC>,
    pub dma0sa: Reg<DMA0SA_SPEC>,
    pub dma0da: Reg<DMA0DA_SPEC>,
    pub dma0sz: Reg<DMA0SZ_SPEC>,
    pub dma1ctl: Reg<DMA1CTL_SPEC>,
    pub dma1sa: Reg<DMA1SA_SPEC>,
    pub dma1da: Reg<DMA1DA_SPEC>,
    pub dma1sz: Reg<DMA1SZ_SPEC>,
    pub dma2ctl: Reg<DMA2CTL_SPEC>,
    pub dma2sa: Reg<DMA2SA_SPEC>,
    pub dma2da: Reg<DMA2DA_SPEC>,
    pub dma2sz: Reg<DMA2SZ_SPEC>,
    // some fields omitted

}

Register block

Fields

dmactl0: Reg<DMACTL0_SPEC>

0x00 - DMA Module Control 0

dmactl1: Reg<DMACTL1_SPEC>

0x02 - DMA Module Control 1

dmactl2: Reg<DMACTL2_SPEC>

0x04 - DMA Module Control 2

dmactl3: Reg<DMACTL3_SPEC>

0x06 - DMA Module Control 3

dmactl4: Reg<DMACTL4_SPEC>

0x08 - DMA Module Control 4

dmaiv: Reg<DMAIV_SPEC>

0x0e - DMA Interrupt Vector Word

dma0ctl: Reg<DMA0CTL_SPEC>

0x10 - DMA Channel 0 Control

dma0sa: Reg<DMA0SA_SPEC>

0x12 - DMA Channel 0 Source Address

dma0da: Reg<DMA0DA_SPEC>

0x16 - DMA Channel 0 Destination Address

dma0sz: Reg<DMA0SZ_SPEC>

0x1a - DMA Channel 0 Transfer Size

dma1ctl: Reg<DMA1CTL_SPEC>

0x20 - DMA Channel 1 Control

dma1sa: Reg<DMA1SA_SPEC>

0x22 - DMA Channel 1 Source Address

dma1da: Reg<DMA1DA_SPEC>

0x26 - DMA Channel 1 Destination Address

dma1sz: Reg<DMA1SZ_SPEC>

0x2a - DMA Channel 1 Transfer Size

dma2ctl: Reg<DMA2CTL_SPEC>

0x30 - DMA Channel 2 Control

dma2sa: Reg<DMA2SA_SPEC>

0x32 - DMA Channel 2 Source Address

dma2da: Reg<DMA2DA_SPEC>

0x36 - DMA Channel 2 Destination Address

dma2sz: Reg<DMA2SZ_SPEC>

0x3a - DMA Channel 2 Transfer Size

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