Struct msp430fr2355::generic::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Implementations

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u16, Reg<u16, _SFRIE1>>

pub fn wdtie(&mut self) -> WDTIE_W<'_>

Bit 0 - Watchdog timer interrupt enable

pub fn ofie(&mut self) -> OFIE_W<'_>

Bit 1 - Oscillator fault interrupt enable

pub fn vmaie(&mut self) -> VMAIE_W<'_>

Bit 3 - Vacant memory access interrupt enable

pub fn nmiie(&mut self) -> NMIIE_W<'_>

Bit 4 - NMI pin interrupt enable

pub fn jmbinie(&mut self) -> JMBINIE_W<'_>

Bit 6 - JTAG mailbox input interrupt enable

pub fn jmboutie(&mut self) -> JMBOUTIE_W<'_>

Bit 7 - JTAG mailbox output interrupt enable

impl W<u16, Reg<u16, _SFRIFG1>>

pub fn ofifg(&mut self) -> OFIFG_W<'_>

Bit 1 - Oscillator fault interrupt flag

pub fn vmaifg(&mut self) -> VMAIFG_W<'_>

Bit 3 - Vacant memory access interrupt flag

pub fn nmiifg(&mut self) -> NMIIFG_W<'_>

Bit 4 - NMI pin interrupt flag

pub fn wdtifg(&mut self) -> WDTIFG_W<'_>

Bit 0 - Watchdog timer interrupt flag

pub fn jmbinifg(&mut self) -> JMBINIFG_W<'_>

Bit 6 - JTAG mailbox input interrupt flag

pub fn jmboutifg(&mut self) -> JMBOUTIFG_W<'_>

Bit 7 - JTAG mailbox output interrupt flag

impl W<u16, Reg<u16, _SFRRPCR>>

pub fn sysnmi(&mut self) -> SYSNMI_W<'_>

Bit 0 - NMI select

pub fn sysnmiies(&mut self) -> SYSNMIIES_W<'_>

Bit 1 - NMI edge select

pub fn sysrstup(&mut self) -> SYSRSTUP_W<'_>

Bit 2 - Reset resistor pin pullup or pulldown

pub fn sysrstre(&mut self) -> SYSRSTRE_W<'_>

Bit 3 - Reset pin resistor enable

impl W<u16, Reg<u16, _PMMCTL0>>

pub fn reflow(&mut self) -> REFLOW_W<'_>

Bit 0 - Reflow pre-conditioning. Prepares device for reflow soldering. Write as 0 during normal operation.

pub fn pmmswbor(&mut self) -> PMMSWBOR_W<'_>

Bit 2 - Software brownout reset.

pub fn pmmswpor(&mut self) -> PMMSWPOR_W<'_>

Bit 3 - Software POR.

pub fn pmmregoff(&mut self) -> PMMREGOFF_W<'_>

Bit 4 - Regulator off

pub fn svshe(&mut self) -> SVSHE_W<'_>

Bit 6 - High-side SVS enable.

pub fn pmmpw(&mut self) -> PMMPW_W<'_>

Bits 8:15 - PMM password.

impl W<u16, Reg<u16, _PMMCTL2>>

pub fn intrefen(&mut self) -> INTREFEN_W<'_>

Bit 0 - Internal reference enable

pub fn extrefen(&mut self) -> EXTREFEN_W<'_>

Bit 1 - External reference output enable

pub fn pwrmode(&mut self) -> PWRMODE_W<'_>

Bits 14:15 - Power Mode Selection. The two bits are used to select the power supply in multi power supply systems. A single power supply system is not affected by the bits. Reserved for future use.

pub fn tsensoren(&mut self) -> TSENSOREN_W<'_>

Bit 3 - Temperature sensor enable

pub fn bgmode(&mut self) -> BGMODE_W<'_>

Bit 11 - Bandgap mode. Ready only.

pub fn refgenrdy(&mut self) -> REFGENRDY_W<'_>

Bit 12 - Variable reference voltage ready status.

pub fn refbgrdy(&mut self) -> REFBGRDY_W<'_>

Bit 13 - Buffered bandgap voltage ready status.

pub fn refvsel(&mut self) -> REFVSEL_W<'_>

Bits 4:5 - Reference voltage level select. Can be modified only when REFGENBUSY = 0.

pub fn refgen(&mut self) -> REFGEN_W<'_>

Bit 6 - Reference generator one-time trigger. If written with a 1, the generation of the variable reference voltage is started. When the reference voltage request is set, this bit is cleared by hardware.

pub fn refbgen(&mut self) -> REFBGEN_W<'_>

Bit 7 - Bandgap and bandgap buffer one-time trigger. If written with a 1, the generation of the buffered bandgap voltage is started. When the bandgap buffer voltage request is set, this bit is cleared by hardware.

impl W<u16, Reg<u16, _PMMIFG>>

pub fn pmmborifg(&mut self) -> PMMBORIFG_W<'_>

Bit 8 - PMM software brownout reset interrupt flag.

pub fn pmmrstifg(&mut self) -> PMMRSTIFG_W<'_>

Bit 9 - PMM reset pin interrupt flag.

pub fn pmmporifg(&mut self) -> PMMPORIFG_W<'_>

Bit 10 - PMM software POR interrupt flag.

pub fn svshifg(&mut self) -> SVSHIFG_W<'_>

Bit 13 - High-side SVS interrupt flag.

pub fn pmmlpm5ifg(&mut self) -> PMMLPM5IFG_W<'_>

Bit 15 - LPMx.5 flag.

impl W<u16, Reg<u16, _PM5CTL0>>

pub fn locklpm5(&mut self) -> LOCKLPM5_W<'_>

Bit 0 - LPMx.5 Lock Bit

pub fn lpm5sw(&mut self) -> LPM5SW_W<'_>

Bit 4 - Reports or sets the LPM3.5 switch connection upon the switch mode set by LPM5SM. When this bit is set, the VLPM3.5 domain can accept full-speed read and write operation by CPU MCLK. If the switch is disconnected, all peripherals within this domain can only accept the operation no more than 40 kHz. In automatic mode (LPM5SM = 0), this bit represents the switch connection between Vcore and VLPM3.5. Any write to this bit has no effect. In manual mode (LPM5SM = 1), this bit can be fully read and written by software. When this bit is set, the switch connection between Vcore and VLPM3.5 is connected. Otherwise, the switch is disconnected.

pub fn lpm5sm(&mut self) -> LPM5SM_W<'_>

Bit 5 - Specifies the operation mode of the LPM3.5 switch.

impl W<u16, Reg<u16, _SYSCTL>>

pub fn sysrivect(&mut self) -> SYSRIVECT_W<'_>

Bit 0 - RAM-based interrupt vectors

pub fn syspmmpe(&mut self) -> SYSPMMPE_W<'_>

Bit 2 - PMM access protect

pub fn sysjtagpin(&mut self) -> SYSJTAGPIN_W<'_>

Bit 5 - Dedicated JTAG pins enable

impl W<u16, Reg<u16, _SYSBSLC>>

pub fn sysbslr(&mut self) -> SYSBSLR_W<'_>

Bit 2 - RAM assigned to BSL

pub fn sysbsloff(&mut self) -> SYSBSLOFF_W<'_>

Bit 14 - Bootstrap loader memory disable for the size covered in SYSBSLSIZE

pub fn sysbslpe(&mut self) -> SYSBSLPE_W<'_>

Bit 15 - Bootstrap loader memory protection enable for the size covered in SYSBSLSIZE. By default, this bit is cleared by hardware with a BOR event (as indicated above); however, the boot code that checks for an available BSL may set this bit in software to protect the BSL. Because devices normally come with a TI BSL preprogrammed and protected, the boot code sets this bit.

impl W<u16, Reg<u16, _SYSJMBC>>

pub fn jmbin0fg(&mut self) -> JMBIN0FG_W<'_>

Bit 0 - Incoming JTAG Mailbox 0 flag

pub fn jmbin1fg(&mut self) -> JMBIN1FG_W<'_>

Bit 1 - Incoming JTAG Mailbox 1 flag

pub fn jmbmode(&mut self) -> JMBMODE_W<'_>

Bit 4 - Operation mode of JMB

pub fn jmbclr0off(&mut self) -> JMBCLR0OFF_W<'_>

Bit 6 - Incoming JTAG Mailbox 0 flag auto-clear disable

pub fn jmbclr1off(&mut self) -> JMBCLR1OFF_W<'_>

Bit 7 - Incoming JTAG Mailbox 1 flag auto-clear disable

impl W<u16, Reg<u16, _SYSJMBI0>>

pub fn msglo(&mut self) -> MSGLO_W<'_>

Bits 0:7 - JTAG mailbox incoming message low byte

pub fn msghi(&mut self) -> MSGHI_W<'_>

Bits 8:15 - JTAG mailbox incoming message high byte

impl W<u16, Reg<u16, _SYSJMBI1>>

pub fn msglo(&mut self) -> MSGLO_W<'_>

Bits 0:7 - JTAG mailbox incoming message low byte

pub fn msghi(&mut self) -> MSGHI_W<'_>

Bits 8:15 - JTAG mailbox incoming message high byte

impl W<u16, Reg<u16, _SYSJMBO0>>

pub fn msglo(&mut self) -> MSGLO_W<'_>

Bits 0:7 - JTAG mailbox outgoing message low byte

pub fn msghi(&mut self) -> MSGHI_W<'_>

Bits 8:15 - JTAG mailbox outgoing message high byte

impl W<u16, Reg<u16, _SYSJMBO1>>

pub fn msglo(&mut self) -> MSGLO_W<'_>

Bits 0:7 - JTAG mailbox outgoing message low byte

pub fn msghi(&mut self) -> MSGHI_W<'_>

Bits 8:15 - JTAG mailbox outgoing message high byte

impl W<u16, Reg<u16, _SYSCFG0>>

pub fn pfwp(&mut self) -> PFWP_W<'_>

Bit 0 - Program FRAM write protection

pub fn dfwp(&mut self) -> DFWP_W<'_>

Bit 1 - Data FRAM write protection

pub fn frwppw(&mut self) -> FRWPPW_W<'_>

Bits 8:15 - FRAM protection password, FRAM protection password. Write with 0A5h to unlock the FRAM protection registers. Always reads as 096h

pub fn frwpoa(&mut self) -> FRWPOA_W<'_>

Bits 2:7 - Program FRAM write protection offset address from the beginning of Program FRAM. The offset increases by 1KB resolution

impl W<u16, Reg<u16, _SYSCFG1>>

pub fn iren(&mut self) -> IREN_W<'_>

Bit 0 - Infrared enable

pub fn irpsel(&mut self) -> IRPSEL_W<'_>

Bit 1 - Infrared polarity select

pub fn irmsel(&mut self) -> IRMSEL_W<'_>

Bit 2 - Infrared mode select

pub fn irdssel(&mut self) -> IRDSSEL_W<'_>

Bit 3 - Infrared data source select

pub fn irdata(&mut self) -> IRDATA_W<'_>

Bit 4 - Infrared data

pub fn syncsel(&mut self) -> SYNCSEL_W<'_>

Bits 6:7 - Captivate Conversion triggered Source Selection

impl W<u16, Reg<u16, _SYSCFG2>>

pub fn adcpctl0(&mut self) -> ADCPCTL0_W<'_>

Bit 0 - ADC input A0 pin select

pub fn adcpctl1(&mut self) -> ADCPCTL1_W<'_>

Bit 1 - ADC input A1 pin select

pub fn adcpctl2(&mut self) -> ADCPCTL2_W<'_>

Bit 2 - ADC input A2 pin select

pub fn adcpctl3(&mut self) -> ADCPCTL3_W<'_>

Bit 3 - ADC input A3 pin select

pub fn adcpctl4(&mut self) -> ADCPCTL4_W<'_>

Bit 4 - ADC input A4 pin select

pub fn adcpctl5(&mut self) -> ADCPCTL5_W<'_>

Bit 5 - ADC input A5 pin select

pub fn adcpctl6(&mut self) -> ADCPCTL6_W<'_>

Bit 6 - ADC input A6 pin select

pub fn adcpctl7(&mut self) -> ADCPCTL7_W<'_>

Bit 7 - ADC input A7 pin select

pub fn adcpctl8(&mut self) -> ADCPCTL8_W<'_>

Bit 8 - ADC input A8 pin select

pub fn adcpctl9(&mut self) -> ADCPCTL9_W<'_>

Bit 9 - ADC input A9 pin select

pub fn uscibrmp(&mut self) -> USCIBRMP_W<'_>

Bit 11 - eUSCIB Remapping source selection , please refer to device specific for details

pub fn rtccksel(&mut self) -> RTCCKSEL_W<'_>

Bit 10 - RTC clock selection

impl W<u16, Reg<u16, _SYSCFG3>>

pub fn usciarmp(&mut self) -> USCIARMP_W<'_>

Bit 0 - eUSCIA remapping source selection, please refer to device specific for details

impl W<u16, Reg<u16, _CSCTL0>>

pub fn dco(&mut self) -> DCO_W<'_>

Bits 0:8 - DCO tap selection. These bits select the DCO tap and are modified automatically during FLL operation.

pub fn mod_(&mut self) -> MOD_W<'_>

Bits 9:13 - Modulation bit counter. These bits select the modulation pattern. All MOD bits are modified automatically during FLL operation. The DCO register value is incremented when the modulation bit counter rolls over from 31 to 0. If the modulation bit counter decrements from 0 to the maximum count, the DCO register value is also decreased.

impl W<u16, Reg<u16, _CSCTL1>>

pub fn dismod(&mut self) -> DISMOD_W<'_>

Bit 0 - Modulation. This bit enables/disables the modulation.

pub fn dcorsel(&mut self) -> DCORSEL_W<'_>

Bits 1:3 - DCO Range Select

pub fn dcoftrim(&mut self) -> DCOFTRIM_W<'_>

Bits 4:6 - DCO frequency trim. These bits trims the DCO frequency. By default, it is chipspecific trimmed. These bits can also be trimmed by user code.

pub fn dcoftrimen(&mut self) -> DCOFTRIMEN_W<'_>

Bit 7 - DCO Frequency Trim Enable. When this bit is set, DCOFTRIM value is selected to set DCO frequency. Otherwise, DCOFTRIM value is bypassed and DCO applies default settings in manufacture.

impl W<u16, Reg<u16, _CSCTL2>>

pub fn flln(&mut self) -> FLLN_W<'_>

Bits 0:9 - Multiplier bits. These bits set the multiplier value N of the DCO. N must be greater than 0. Writing zero to FLLN causes N to be set to 1.

pub fn flld(&mut self) -> FLLD_W<'_>

Bits 12:14 - FLL loop divider. These bits divide f(DCOCLK) in the FLL feedback loop. This results in an additional multiplier for the multiplier bits. See also multiplier bits.

impl W<u16, Reg<u16, _CSCTL3>>

pub fn fllrefdiv(&mut self) -> FLLREFDIV_W<'_>

Bits 0:2 - FLL reference divider. These bits define the divide factor for f(FLLREFCLK). If XT1 supports high frequency input higher than 32 kHz, the divided frequency is used as the FLL reference frequency. If XT1 only supports 32-kHz clock, FLLREFDIV is always read and written as zero, 000b = fFLLREFCLK / 1

pub fn selref(&mut self) -> SELREF_W<'_>

Bits 4:5 - FLL reference select. These bits select the FLL reference clock source.

pub fn refolp(&mut self) -> REFOLP_W<'_>

Bit 7 - REFO Low Power Enable. This bit turns on REFO low-power mode. During switch, the low-power mode will be invalid until REFOREADY is set.

impl W<u16, Reg<u16, _CSCTL4>>

pub fn selms(&mut self) -> SELMS_W<'_>

Bits 0:2 - Selects the MCLK and SMCLK source

pub fn sela(&mut self) -> SELA_W<'_>

Bits 8:9 - Selects the ACLK source

impl W<u16, Reg<u16, _CSCTL5>>

pub fn divm(&mut self) -> DIVM_W<'_>

Bits 0:2 - MCLK source divider

pub fn divs(&mut self) -> DIVS_W<'_>

Bits 4:5 - SMCLK source divider. SMCLK directly derives from MCLK. SMCLK frequency is the combination of DIVM and DIVS out of selected clock source.

pub fn smclkoff(&mut self) -> SMCLKOFF_W<'_>

Bit 8 - SMCLK off. This bit turns off SMCLK clock

pub fn vloautooff(&mut self) -> VLOAUTOOFF_W<'_>

Bit 12 - VLO automatic off enable. This bit turns off VLO, if VLO is not used.

impl W<u16, Reg<u16, _CSCTL6>>

pub fn xt1autooff(&mut self) -> XT1AUTOOFF_W<'_>

Bit 0 - XT1 automatic off enable. This bit allows XT1 turned turns off when it is not used

pub fn xt1agcoff(&mut self) -> XT1AGCOFF_W<'_>

Bit 1 - Automatic Gain Control (AGC) disable.

pub fn xt1hffreq(&mut self) -> XT1HFFREQ_W<'_>

Bits 2:3 - The XT1 High-frequency selection. These bits must be set to appropriate frequency for crystal or bypass modes of operation.

pub fn xt1bypass(&mut self) -> XT1BYPASS_W<'_>

Bit 4 - XT1 bypass select

pub fn xts(&mut self) -> XTS_W<'_>

Bit 5 - XT1 mode select

pub fn xt1drive(&mut self) -> XT1DRIVE_W<'_>

Bits 6:7 - The XT1 oscillator current can be adjusted to its drive needs. Initially, it starts with the highest supply current for reliable and quick startup. If needed, user software can reduce the drive strength. The configuration of these bits is retained during LPM3.5 until LOCKLPM5 is cleared, but not the register bits itself; therefore, reconfiguration after wake-up from LPM3.5 before clearing LOCKLPM5 is required.

pub fn diva(&mut self) -> DIVA_W<'_>

Bits 8:11 - ACLK source divider.

pub fn xt1faultoff(&mut self) -> XT1FAULTOFF_W<'_>

Bit 13 - The XT1 oscillator fault detection off

impl W<u16, Reg<u16, _CSCTL7>>

pub fn dcoffg(&mut self) -> DCOFFG_W<'_>

Bit 0 - DCO fault flag. If this bit is set, the OFIFG flag is also set. The DCOFFG bit is set if DCO = {0} or DCO = {511}. DCOFFG can be cleared by software. If the DCO fault condition still remains, DCOFFG is set. As long as DCOFFG is set, FLLUNLOCK shows the DCOERROR condition.

pub fn xt1offg(&mut self) -> XT1OFFG_W<'_>

Bit 1 - T1 oscillator fault flag. If this bit is set, the OFIFG flag is also set. XT1OFFG is set if a XT1 fault condition exists. XT1OFFG can be cleared by software. If the XT1 fault condition still remains, XT1OFFG is set.

pub fn fllulifg(&mut self) -> FLLULIFG_W<'_>

Bit 4 - FLL unlock interrupt flag. This flag is set when FLLUNLOCK bits equal 10b (DCO too fast). If FLLULPUC is also set, a PUC is triggered when FLLUIFG is set.

pub fn enstfcnt1(&mut self) -> ENSTFCNT1_W<'_>

Bit 6 - Enable start counter for XT1.

pub fn fllunlock(&mut self) -> FLLUNLOCK_W<'_>

Bits 8:9 - Unlock. These bits indicate the current FLL unlock condition. These bits are both set as long as the DCOFFG flag is set.

pub fn fllunlockhis(&mut self) -> FLLUNLOCKHIS_W<'_>

Bits 10:11 - Unlock history bits. These bits indicate the FLL unlock condition history. As soon as any unlock condition happens, the respective bits are set and remain set until cleared by software by writing 0 to it or by a POR.

pub fn fllulpuc(&mut self) -> FLLULPUC_W<'_>

Bit 12 - FLL unlock PUC enable. If the FLLULPUC bit is set, a reset (PUC) is triggered if FLLULIFG is set. FLLULIFG indicates when FLLUNLOCK bits equal 10 (too fast). FLLULPUC is automatically cleared upon servicing the event. If FLLULPUC is cleared (0), no PUC can be triggered by FLLULIFG.

pub fn fllwarnen(&mut self) -> FLLWARNEN_W<'_>

Bit 13 - Warning enable. If this bit is set, an interrupt is generated based on the FLLUNLOCKHIS bits. If FLLUNLOCKHIS is not equal to 00, an OFIFG is generated.

impl W<u16, Reg<u16, _CSCTL8>>

pub fn aclkreqen(&mut self) -> ACLKREQEN_W<'_>

Bit 0 - ACLK clock request enable. Setting this enables conditional module requests for ACLK

pub fn mclkreqen(&mut self) -> MCLKREQEN_W<'_>

Bit 1 - MCLK clock request enable. Setting this enables conditional module requests for MCLK

pub fn smclkreqen(&mut self) -> SMCLKREQEN_W<'_>

Bit 2 - SMCLK clock request enable. Setting this enables conditional module requests for SMCLK

pub fn modoscreqen(&mut self) -> MODOSCREQEN_W<'_>

Bit 3 - MODOSC clock request enable. Setting this enables conditional module requests for MODOSC.

impl W<u16, Reg<u16, _FRCTL0>>

pub fn nwaits(&mut self) -> NWAITS_W<'_>

Bits 4:6 - Wait state numbers

pub fn frctlpw(&mut self) -> FRCTLPW_W<'_>

Bits 8:15 - FRCTLPW password

impl W<u16, Reg<u16, _GCCTL0>>

pub fn ubdrsten(&mut self) -> UBDRSTEN_W<'_>

Bit 7 - Enable Power Up Clear (PUC) reset for the uncorrectable bit error detection flag (UBDIFG)

pub fn ubdie(&mut self) -> UBDIE_W<'_>

Bit 6 - Enable NMI event for the uncorrectable bit error detection flag (UBDIFG)

pub fn cbdie(&mut self) -> CBDIE_W<'_>

Bit 5 - Enable NMI event for the correctable bit error detection flag (CBDIFG)

pub fn frpwr(&mut self) -> FRPWR_W<'_>

Bit 2 - FRAM Memory Power Control Request

pub fn frlpmpwr(&mut self) -> FRLPMPWR_W<'_>

Bit 1 - Enables FRAM auto power up after LPM

impl W<u16, Reg<u16, _GCCTL1>>

pub fn accteifg(&mut self) -> ACCTEIFG_W<'_>

Bit 3 - Access time error flag

pub fn ubdifg(&mut self) -> UBDIFG_W<'_>

Bit 2 - FRAM uncorrectable bit error detection flag

pub fn cbdifg(&mut self) -> CBDIFG_W<'_>

Bit 1 - FRAM correctable bit error detection flag

impl W<u16, Reg<u16, _WDTCTL>>

pub fn wdtis(&mut self) -> WDTIS_W<'_>

Bits 0:2 - Watchdog timer interval select

pub fn wdtcntcl(&mut self) -> WDTCNTCL_W<'_>

Bit 3 - Watchdog timer counter clear

pub fn wdttmsel(&mut self) -> WDTTMSEL_W<'_>

Bit 4 - Watchdog timer mode select

pub fn wdtssel(&mut self) -> WDTSSEL_W<'_>

Bits 5:6 - Watchdog timer clock source select

pub fn wdthold(&mut self) -> WDTHOLD_W<'_>

Bit 7 - Watchdog timer hold

pub fn wdtpw(&mut self) -> WDTPW_W<'_>

Bits 8:15 - Watchdog timer password

impl W<u16, Reg<u16, _RTCCTL>>

pub fn rtcie(&mut self) -> RTCIE_W<'_>

Bit 1 - Real-time interrupt enable

pub fn rtcsr(&mut self) -> RTCSR_W<'_>

Bit 6 - Real-time software reset. This is a write only bit and is always read with logic 0. 0b = Write 0 has no effect

pub fn rtcps(&mut self) -> RTCPS_W<'_>

Bits 8:10 - Real-time clock pre-divider select

pub fn rtcss(&mut self) -> RTCSS_W<'_>

Bits 12:13 - Real-time clock source select

impl W<u16, Reg<u16, _TB0CTL>>

pub fn tbifg(&mut self) -> TBIFG_W<'_>

Bit 0 - TimerB interrupt flag

pub fn tbie(&mut self) -> TBIE_W<'_>

Bit 1 - TimerB interrupt enable

pub fn tbclr(&mut self) -> TBCLR_W<'_>

Bit 2 - TimerB clear

pub fn mc(&mut self) -> MC_W<'_>

Bits 4:5 - Mode control

pub fn id(&mut self) -> ID_W<'_>

Bits 6:7 - Input divider

pub fn tbssel(&mut self) -> TBSSEL_W<'_>

Bits 8:9 - TimerB clock source select

pub fn cntl(&mut self) -> CNTL_W<'_>

Bits 11:12 - Counter length

pub fn tbclgrp(&mut self) -> TBCLGRP_W<'_>

Bits 13:14 - TBxCLn group

impl W<u16, Reg<u16, _TB0CCTL0>>

pub fn ccifg(&mut self) -> CCIFG_W<'_>

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>

Bit 1 - Capture overflow

pub fn out(&mut self) -> OUT_W<'_>

Bit 2 - Output

pub fn ccie(&mut self) -> CCIE_W<'_>

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>

Bits 5:7 - Output mode

pub fn cap(&mut self) -> CAP_W<'_>

Bit 8 - Capture mode

pub fn clld(&mut self) -> CLLD_W<'_>

Bits 9:10 - Compare latch load

pub fn scs(&mut self) -> SCS_W<'_>

Bit 11 - Synchronize capture source

pub fn ccis(&mut self) -> CCIS_W<'_>

Bits 12:13 - Capture/compare input select

pub fn cm(&mut self) -> CM_W<'_>

Bits 14:15 - Capture mode

impl W<u16, Reg<u16, _TB0CCTL1>>

pub fn ccifg(&mut self) -> CCIFG_W<'_>

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>

Bit 1 - Capture overflow

pub fn out(&mut self) -> OUT_W<'_>

Bit 2 - Output

pub fn ccie(&mut self) -> CCIE_W<'_>

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>

Bits 5:7 - Output mode

pub fn cap(&mut self) -> CAP_W<'_>

Bit 8 - Capture mode

pub fn clld(&mut self) -> CLLD_W<'_>

Bits 9:10 - Compare latch load

pub fn scs(&mut self) -> SCS_W<'_>

Bit 11 - Synchronize capture source

pub fn ccis(&mut self) -> CCIS_W<'_>

Bits 12:13 - Capture/compare input select

pub fn cm(&mut self) -> CM_W<'_>

Bits 14:15 - Capture mode

impl W<u16, Reg<u16, _TB0CCTL2>>

pub fn ccifg(&mut self) -> CCIFG_W<'_>

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>

Bit 1 - Capture overflow

pub fn out(&mut self) -> OUT_W<'_>

Bit 2 - Output

pub fn ccie(&mut self) -> CCIE_W<'_>

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>

Bits 5:7 - Output mode

pub fn cap(&mut self) -> CAP_W<'_>

Bit 8 - Capture mode

pub fn clld(&mut self) -> CLLD_W<'_>

Bits 9:10 - Compare latch load

pub fn scs(&mut self) -> SCS_W<'_>

Bit 11 - Synchronize capture source

pub fn ccis(&mut self) -> CCIS_W<'_>

Bits 12:13 - Capture/compare input select

pub fn cm(&mut self) -> CM_W<'_>

Bits 14:15 - Capture mode

impl W<u16, Reg<u16, _TB0EX0>>

pub fn tbidex(&mut self) -> TBIDEX_W<'_>

Bits 0:2 - Input divider expansion

impl W<u16, Reg<u16, _TB1CTL>>

pub fn tbifg(&mut self) -> TBIFG_W<'_>

Bit 0 - TimerB interrupt flag

pub fn tbie(&mut self) -> TBIE_W<'_>

Bit 1 - TimerB interrupt enable

pub fn tbclr(&mut self) -> TBCLR_W<'_>

Bit 2 - TimerB clear

pub fn mc(&mut self) -> MC_W<'_>

Bits 4:5 - Mode control

pub fn id(&mut self) -> ID_W<'_>

Bits 6:7 - Input divider

pub fn tbssel(&mut self) -> TBSSEL_W<'_>

Bits 8:9 - TimerB clock source select

pub fn cntl(&mut self) -> CNTL_W<'_>

Bits 11:12 - Counter length

pub fn tbclgrp(&mut self) -> TBCLGRP_W<'_>

Bits 13:14 - TBxCLn group

impl W<u16, Reg<u16, _TB1CCTL0>>

pub fn ccifg(&mut self) -> CCIFG_W<'_>

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>

Bit 1 - Capture overflow

pub fn out(&mut self) -> OUT_W<'_>

Bit 2 - Output

pub fn ccie(&mut self) -> CCIE_W<'_>

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>

Bits 5:7 - Output mode

pub fn cap(&mut self) -> CAP_W<'_>

Bit 8 - Capture mode

pub fn clld(&mut self) -> CLLD_W<'_>

Bits 9:10 - Compare latch load

pub fn scs(&mut self) -> SCS_W<'_>

Bit 11 - Synchronize capture source

pub fn ccis(&mut self) -> CCIS_W<'_>

Bits 12:13 - Capture/compare input select

pub fn cm(&mut self) -> CM_W<'_>

Bits 14:15 - Capture mode

impl W<u16, Reg<u16, _TB1CCTL1>>

pub fn ccifg(&mut self) -> CCIFG_W<'_>

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>

Bit 1 - Capture overflow

pub fn out(&mut self) -> OUT_W<'_>

Bit 2 - Output

pub fn ccie(&mut self) -> CCIE_W<'_>

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>

Bits 5:7 - Output mode

pub fn cap(&mut self) -> CAP_W<'_>

Bit 8 - Capture mode

pub fn clld(&mut self) -> CLLD_W<'_>

Bits 9:10 - Compare latch load

pub fn scs(&mut self) -> SCS_W<'_>

Bit 11 - Synchronize capture source

pub fn ccis(&mut self) -> CCIS_W<'_>

Bits 12:13 - Capture/compare input select

pub fn cm(&mut self) -> CM_W<'_>

Bits 14:15 - Capture mode

impl W<u16, Reg<u16, _TB1CCTL2>>

pub fn ccifg(&mut self) -> CCIFG_W<'_>

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>

Bit 1 - Capture overflow

pub fn out(&mut self) -> OUT_W<'_>

Bit 2 - Output

pub fn ccie(&mut self) -> CCIE_W<'_>

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>

Bits 5:7 - Output mode

pub fn cap(&mut self) -> CAP_W<'_>

Bit 8 - Capture mode

pub fn clld(&mut self) -> CLLD_W<'_>

Bits 9:10 - Compare latch load

pub fn scs(&mut self) -> SCS_W<'_>

Bit 11 - Synchronize capture source

pub fn ccis(&mut self) -> CCIS_W<'_>

Bits 12:13 - Capture/compare input select

pub fn cm(&mut self) -> CM_W<'_>

Bits 14:15 - Capture mode

impl W<u16, Reg<u16, _TB1EX0>>

pub fn tbidex(&mut self) -> TBIDEX_W<'_>

Bits 0:2 - Input divider expansion

impl W<u16, Reg<u16, _TB2CTL>>

pub fn tbifg(&mut self) -> TBIFG_W<'_>

Bit 0 - TimerB interrupt flag

pub fn tbie(&mut self) -> TBIE_W<'_>

Bit 1 - TimerB interrupt enable

pub fn tbclr(&mut self) -> TBCLR_W<'_>

Bit 2 - TimerB clear

pub fn mc(&mut self) -> MC_W<'_>

Bits 4:5 - Mode control

pub fn id(&mut self) -> ID_W<'_>

Bits 6:7 - Input divider

pub fn tbssel(&mut self) -> TBSSEL_W<'_>

Bits 8:9 - TimerB clock source select

pub fn cntl(&mut self) -> CNTL_W<'_>

Bits 11:12 - Counter length

pub fn tbclgrp(&mut self) -> TBCLGRP_W<'_>

Bits 13:14 - TBxCLn group

impl W<u16, Reg<u16, _TB2CCTL0>>

pub fn ccifg(&mut self) -> CCIFG_W<'_>

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>

Bit 1 - Capture overflow

pub fn out(&mut self) -> OUT_W<'_>

Bit 2 - Output

pub fn ccie(&mut self) -> CCIE_W<'_>

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>

Bits 5:7 - Output mode

pub fn cap(&mut self) -> CAP_W<'_>

Bit 8 - Capture mode

pub fn clld(&mut self) -> CLLD_W<'_>

Bits 9:10 - Compare latch load

pub fn scs(&mut self) -> SCS_W<'_>

Bit 11 - Synchronize capture source

pub fn ccis(&mut self) -> CCIS_W<'_>

Bits 12:13 - Capture/compare input select

pub fn cm(&mut self) -> CM_W<'_>

Bits 14:15 - Capture mode

impl W<u16, Reg<u16, _TB2CCTL1>>

pub fn ccifg(&mut self) -> CCIFG_W<'_>

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>

Bit 1 - Capture overflow

pub fn out(&mut self) -> OUT_W<'_>

Bit 2 - Output

pub fn ccie(&mut self) -> CCIE_W<'_>

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>

Bits 5:7 - Output mode

pub fn cap(&mut self) -> CAP_W<'_>

Bit 8 - Capture mode

pub fn clld(&mut self) -> CLLD_W<'_>

Bits 9:10 - Compare latch load

pub fn scs(&mut self) -> SCS_W<'_>

Bit 11 - Synchronize capture source

pub fn ccis(&mut self) -> CCIS_W<'_>

Bits 12:13 - Capture/compare input select

pub fn cm(&mut self) -> CM_W<'_>

Bits 14:15 - Capture mode

impl W<u16, Reg<u16, _TB2CCTL2>>

pub fn ccifg(&mut self) -> CCIFG_W<'_>

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>

Bit 1 - Capture overflow

pub fn out(&mut self) -> OUT_W<'_>

Bit 2 - Output

pub fn ccie(&mut self) -> CCIE_W<'_>

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>

Bits 5:7 - Output mode

pub fn cap(&mut self) -> CAP_W<'_>

Bit 8 - Capture mode

pub fn clld(&mut self) -> CLLD_W<'_>

Bits 9:10 - Compare latch load

pub fn scs(&mut self) -> SCS_W<'_>

Bit 11 - Synchronize capture source

pub fn ccis(&mut self) -> CCIS_W<'_>

Bits 12:13 - Capture/compare input select

pub fn cm(&mut self) -> CM_W<'_>

Bits 14:15 - Capture mode

impl W<u16, Reg<u16, _TB2EX0>>

pub fn tbidex(&mut self) -> TBIDEX_W<'_>

Bits 0:2 - Input divider expansion

impl W<u16, Reg<u16, _TB3CTL>>

pub fn tbifg(&mut self) -> TBIFG_W<'_>

Bit 0 - TimerB interrupt flag

pub fn tbie(&mut self) -> TBIE_W<'_>

Bit 1 - TimerB interrupt enable

pub fn tbclr(&mut self) -> TBCLR_W<'_>

Bit 2 - TimerB clear

pub fn mc(&mut self) -> MC_W<'_>

Bits 4:5 - Mode control

pub fn id(&mut self) -> ID_W<'_>

Bits 6:7 - Input divider

pub fn tbssel(&mut self) -> TBSSEL_W<'_>

Bits 8:9 - TimerB clock source select

pub fn cntl(&mut self) -> CNTL_W<'_>

Bits 11:12 - Counter length

pub fn tbclgrp(&mut self) -> TBCLGRP_W<'_>

Bits 13:14 - TBxCLn group

impl W<u16, Reg<u16, _TB3CCTL0>>

pub fn ccifg(&mut self) -> CCIFG_W<'_>

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>

Bit 1 - Capture overflow

pub fn out(&mut self) -> OUT_W<'_>

Bit 2 - Output

pub fn ccie(&mut self) -> CCIE_W<'_>

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>

Bits 5:7 - Output mode

pub fn cap(&mut self) -> CAP_W<'_>

Bit 8 - Capture mode

pub fn clld(&mut self) -> CLLD_W<'_>

Bits 9:10 - Compare latch load

pub fn scs(&mut self) -> SCS_W<'_>

Bit 11 - Synchronize capture source

pub fn ccis(&mut self) -> CCIS_W<'_>

Bits 12:13 - Capture/compare input select

pub fn cm(&mut self) -> CM_W<'_>

Bits 14:15 - Capture mode

impl W<u16, Reg<u16, _TB3CCTL1>>

pub fn ccifg(&mut self) -> CCIFG_W<'_>

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>

Bit 1 - Capture overflow

pub fn out(&mut self) -> OUT_W<'_>

Bit 2 - Output

pub fn ccie(&mut self) -> CCIE_W<'_>

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>

Bits 5:7 - Output mode

pub fn cap(&mut self) -> CAP_W<'_>

Bit 8 - Capture mode

pub fn clld(&mut self) -> CLLD_W<'_>

Bits 9:10 - Compare latch load

pub fn scs(&mut self) -> SCS_W<'_>

Bit 11 - Synchronize capture source

pub fn ccis(&mut self) -> CCIS_W<'_>

Bits 12:13 - Capture/compare input select

pub fn cm(&mut self) -> CM_W<'_>

Bits 14:15 - Capture mode

impl W<u16, Reg<u16, _TB3CCTL2>>

pub fn ccifg(&mut self) -> CCIFG_W<'_>

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>

Bit 1 - Capture overflow

pub fn out(&mut self) -> OUT_W<'_>

Bit 2 - Output

pub fn ccie(&mut self) -> CCIE_W<'_>

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>

Bits 5:7 - Output mode

pub fn cap(&mut self) -> CAP_W<'_>

Bit 8 - Capture mode

pub fn clld(&mut self) -> CLLD_W<'_>

Bits 9:10 - Compare latch load

pub fn scs(&mut self) -> SCS_W<'_>

Bit 11 - Synchronize capture source

pub fn ccis(&mut self) -> CCIS_W<'_>

Bits 12:13 - Capture/compare input select

pub fn cm(&mut self) -> CM_W<'_>

Bits 14:15 - Capture mode

impl W<u16, Reg<u16, _TB3CCTL3>>

pub fn ccifg(&mut self) -> CCIFG_W<'_>

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>

Bit 1 - Capture overflow

pub fn out(&mut self) -> OUT_W<'_>

Bit 2 - Output

pub fn ccie(&mut self) -> CCIE_W<'_>

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>

Bits 5:7 - Output mode

pub fn cap(&mut self) -> CAP_W<'_>

Bit 8 - Capture mode

pub fn clld(&mut self) -> CLLD_W<'_>

Bits 9:10 - Compare latch load

pub fn scs(&mut self) -> SCS_W<'_>

Bit 11 - Synchronize capture source

pub fn ccis(&mut self) -> CCIS_W<'_>

Bits 12:13 - Capture/compare input select

pub fn cm(&mut self) -> CM_W<'_>

Bits 14:15 - Capture mode

impl W<u16, Reg<u16, _TB3CCTL4>>

pub fn ccifg(&mut self) -> CCIFG_W<'_>

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>

Bit 1 - Capture overflow

pub fn out(&mut self) -> OUT_W<'_>

Bit 2 - Output

pub fn ccie(&mut self) -> CCIE_W<'_>

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>

Bits 5:7 - Output mode

pub fn cap(&mut self) -> CAP_W<'_>

Bit 8 - Capture mode

pub fn clld(&mut self) -> CLLD_W<'_>

Bits 9:10 - Compare latch load

pub fn scs(&mut self) -> SCS_W<'_>

Bit 11 - Synchronize capture source

pub fn ccis(&mut self) -> CCIS_W<'_>

Bits 12:13 - Capture/compare input select

pub fn cm(&mut self) -> CM_W<'_>

Bits 14:15 - Capture mode

impl W<u16, Reg<u16, _TB3CCTL5>>

pub fn ccifg(&mut self) -> CCIFG_W<'_>

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>

Bit 1 - Capture overflow

pub fn out(&mut self) -> OUT_W<'_>

Bit 2 - Output

pub fn ccie(&mut self) -> CCIE_W<'_>

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>

Bits 5:7 - Output mode

pub fn cap(&mut self) -> CAP_W<'_>

Bit 8 - Capture mode

pub fn clld(&mut self) -> CLLD_W<'_>

Bits 9:10 - Compare latch load

pub fn scs(&mut self) -> SCS_W<'_>

Bit 11 - Synchronize capture source

pub fn ccis(&mut self) -> CCIS_W<'_>

Bits 12:13 - Capture/compare input select

pub fn cm(&mut self) -> CM_W<'_>

Bits 14:15 - Capture mode

impl W<u16, Reg<u16, _TB3CCTL6>>

pub fn ccifg(&mut self) -> CCIFG_W<'_>

Bit 0 - Capture/compare interrupt flag

pub fn cov(&mut self) -> COV_W<'_>

Bit 1 - Capture overflow

pub fn out(&mut self) -> OUT_W<'_>

Bit 2 - Output

pub fn ccie(&mut self) -> CCIE_W<'_>

Bit 4 - Capture/compare interrupt enable

pub fn outmod(&mut self) -> OUTMOD_W<'_>

Bits 5:7 - Output mode

pub fn cap(&mut self) -> CAP_W<'_>

Bit 8 - Capture mode

pub fn clld(&mut self) -> CLLD_W<'_>

Bits 9:10 - Compare latch load

pub fn scs(&mut self) -> SCS_W<'_>

Bit 11 - Synchronize capture source

pub fn ccis(&mut self) -> CCIS_W<'_>

Bits 12:13 - Capture/compare input select

pub fn cm(&mut self) -> CM_W<'_>

Bits 14:15 - Capture mode

impl W<u16, Reg<u16, _TB3EX0>>

pub fn tbidex(&mut self) -> TBIDEX_W<'_>

Bits 0:2 - Input divider expansion

impl W<u16, Reg<u16, _MACS32H>>

pub fn macs32h(&mut self) -> MACS32H_W<'_>

Bits 8:15 - 32-bit operand 1 signed multiply accumulate high word

impl W<u16, Reg<u16, _MPY32CTL0>>

pub fn mpydly32(&mut self) -> MPYDLY32_W<'_>

Bit 9 - Delayed write mode.

pub fn mpydlywrten(&mut self) -> MPYDLYWRTEN_W<'_>

Bit 8 - Delayed write enable.

pub fn mpyop2_32(&mut self) -> MPYOP2_32_W<'_>

Bit 7 - Multiplier bit width of operand 2

pub fn mpyop1_32(&mut self) -> MPYOP1_32_W<'_>

Bit 6 - Multiplier bit width of operand 1

pub fn mpym(&mut self) -> MPYM_W<'_>

Bits 4:5 - Multiplier mode

pub fn mpysat(&mut self) -> MPYSAT_W<'_>

Bit 3 - Saturation mode

pub fn mpyfrac(&mut self) -> MPYFRAC_W<'_>

Bit 2 - Fractional mode.

pub fn mpyc(&mut self) -> MPYC_W<'_>

Bit 0 - Carry of the multiplier

impl W<u16, Reg<u16, _UCA0CTLW0>>

pub fn ucswrst(&mut self) -> UCSWRST_W<'_>

Bit 0 - Software reset enable

pub fn uctxbrk(&mut self) -> UCTXBRK_W<'_>

Bit 1 - Transmit break

pub fn uctxaddr(&mut self) -> UCTXADDR_W<'_>

Bit 2 - Transmit address

pub fn ucdorm(&mut self) -> UCDORM_W<'_>

Bit 3 - Dormant

pub fn ucbrkie(&mut self) -> UCBRKIE_W<'_>

Bit 4 - Receive break character interrupt enable

pub fn ucrxeie(&mut self) -> UCRXEIE_W<'_>

Bit 5 - Receive erroneous-character interrupt enable

pub fn ucssel(&mut self) -> UCSSEL_W<'_>

Bits 6:7 - eUSCI_A clock source select

pub fn ucsync(&mut self) -> UCSYNC_W<'_>

Bit 8 - Synchronous mode enable

pub fn ucmode(&mut self) -> UCMODE_W<'_>

Bits 9:10 - eUSCI_A mode

pub fn ucspb(&mut self) -> UCSPB_W<'_>

Bit 11 - Stop bit select

pub fn uc7bit(&mut self) -> UC7BIT_W<'_>

Bit 12 - Character length

pub fn ucmsb(&mut self) -> UCMSB_W<'_>

Bit 13 - MSB first select

pub fn ucpar(&mut self) -> UCPAR_W<'_>

Bit 14 - Parity select

pub fn ucpen(&mut self) -> UCPEN_W<'_>

Bit 15 - Parity enable

impl W<u16, Reg<u16, _UCA0CTLW0_SPI>>

pub fn ucswrst(&mut self) -> UCSWRST_W<'_>

Bit 0 - Software reset enable

pub fn ucstem(&mut self) -> UCSTEM_W<'_>

Bit 1 - STE mode select in master mode.

pub fn ucssel(&mut self) -> UCSSEL_W<'_>

Bits 6:7 - eUSCI_A clock source select

pub fn ucsync(&mut self) -> UCSYNC_W<'_>

Bit 8 - Synchronous mode enable

pub fn ucmode(&mut self) -> UCMODE_W<'_>

Bits 9:10 - eUSCI mode

pub fn ucmst(&mut self) -> UCMST_W<'_>

Bit 11 - Master mode select

pub fn uc7bit(&mut self) -> UC7BIT_W<'_>

Bit 12 - Character length

pub fn ucmsb(&mut self) -> UCMSB_W<'_>

Bit 13 - MSB first select

pub fn ucckpl(&mut self) -> UCCKPL_W<'_>

Bit 14 - Clock polarity select

pub fn ucckph(&mut self) -> UCCKPH_W<'_>

Bit 15 - Clock phase select

impl W<u16, Reg<u16, _UCA0CTLW1>>

pub fn ucglit(&mut self) -> UCGLIT_W<'_>

Bits 0:1 - Deglitch time

impl W<u16, Reg<u16, _UCA0MCTLW>>

pub fn ucos16(&mut self) -> UCOS16_W<'_>

Bit 0 - Oversampling mode enabled

pub fn ucbrf(&mut self) -> UCBRF_W<'_>

Bits 4:7 - First modulation stage select

pub fn ucbrs(&mut self) -> UCBRS_W<'_>

Bits 8:15 - Second modulation stage select

impl W<u16, Reg<u16, _UCA0STATW>>

pub fn ucaddr_ucidle(&mut self) -> UCADDR_UCIDLE_W<'_>

Bit 1 - Address received / Idle line detected

pub fn ucrxerr(&mut self) -> UCRXERR_W<'_>

Bit 2 - Receive error flag

pub fn ucbrk(&mut self) -> UCBRK_W<'_>

Bit 3 - Break detect flag

pub fn ucpe(&mut self) -> UCPE_W<'_>

Bit 4 - Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read.

pub fn ucoe(&mut self) -> UCOE_W<'_>

Bit 5 - Overrun error flag

pub fn ucfe(&mut self) -> UCFE_W<'_>

Bit 6 - Framing error flag

pub fn uclisten(&mut self) -> UCLISTEN_W<'_>

Bit 7 - Listen enable

impl W<u16, Reg<u16, _UCA0STATW_SPI>>

pub fn ucoe(&mut self) -> UCOE_W<'_>

Bit 5 - Overrun error flag

pub fn ucfe(&mut self) -> UCFE_W<'_>

Bit 6 - Framing error flag

pub fn uclisten(&mut self) -> UCLISTEN_W<'_>

Bit 7 - Listen enable

impl W<u16, Reg<u16, _UCA0TXBUF>>

pub fn uctxbuf(&mut self) -> UCTXBUF_W<'_>

Bits 0:7 - Transmit data buffer

impl W<u16, Reg<u16, _UCA0TXBUF_SPI>>

pub fn uctxbuf(&mut self) -> UCTXBUF_W<'_>

Bits 0:7 - Transmit data buffer

impl W<u16, Reg<u16, _UCA0ABCTL>>

pub fn ucabden(&mut self) -> UCABDEN_W<'_>

Bit 0 - Automatic baud-rate detect enable

pub fn ucbtoe(&mut self) -> UCBTOE_W<'_>

Bit 2 - Break time out error

pub fn ucstoe(&mut self) -> UCSTOE_W<'_>

Bit 3 - Synch field time out error

pub fn ucdelim(&mut self) -> UCDELIM_W<'_>

Bits 4:5 - Break/synch delimiter length

impl W<u16, Reg<u16, _UCA0IRCTL>>

pub fn uciren(&mut self) -> UCIREN_W<'_>

Bit 0 - IrDA encoder/decoder enable

pub fn ucirtxclk(&mut self) -> UCIRTXCLK_W<'_>

Bit 1 - IrDA transmit pulse clock select

pub fn ucirtxpl(&mut self) -> UCIRTXPL_W<'_>

Bits 2:7 - Transmit pulse length

pub fn ucirrxfe(&mut self) -> UCIRRXFE_W<'_>

Bit 8 - IrDA receive filter enabled

pub fn ucirrxpl(&mut self) -> UCIRRXPL_W<'_>

Bit 9 - IrDA receive input UCAxRXD polarity

pub fn ucirrxfl(&mut self) -> UCIRRXFL_W<'_>

Bits 10:15 - Receive filter length

impl W<u16, Reg<u16, _UCA0IE>>

pub fn ucrxie(&mut self) -> UCRXIE_W<'_>

Bit 0 - Receive interrupt enable

pub fn uctxie(&mut self) -> UCTXIE_W<'_>

Bit 1 - Transmit interrupt enable

pub fn ucsttie(&mut self) -> UCSTTIE_W<'_>

Bit 2 - Start bit interrupt enable

pub fn uctxcptie(&mut self) -> UCTXCPTIE_W<'_>

Bit 3 - Transmit complete interrupt enable

impl W<u16, Reg<u16, _UCA0IE_SPI>>

pub fn ucrxie(&mut self) -> UCRXIE_W<'_>

Bit 0 - Receive interrupt enable

pub fn uctxie(&mut self) -> UCTXIE_W<'_>

Bit 1 - Transmit interrupt enable

impl W<u16, Reg<u16, _UCA0IFG>>

pub fn ucrxifg(&mut self) -> UCRXIFG_W<'_>

Bit 0 - Receive interrupt flag

pub fn uctxifg(&mut self) -> UCTXIFG_W<'_>

Bit 1 - Transmit interrupt flag

pub fn ucsttifg(&mut self) -> UCSTTIFG_W<'_>

Bit 2 - Start bit interrupt flag

pub fn uctxcptifg(&mut self) -> UCTXCPTIFG_W<'_>

Bit 3 - Transmit ready interrupt enable

impl W<u16, Reg<u16, _UCA0IFG_SPI>>

pub fn ucrxifg(&mut self) -> UCRXIFG_W<'_>

Bit 0 - Receive interrupt flag

pub fn uctxifg(&mut self) -> UCTXIFG_W<'_>

Bit 1 - Transmit interrupt flag

impl W<u16, Reg<u16, _UCB0CTLW0>>

pub fn ucswrst(&mut self) -> UCSWRST_W<'_>

Bit 0 - Software reset enable

pub fn uctxstt(&mut self) -> UCTXSTT_W<'_>

Bit 1 - Transmit START condition in master mode

pub fn uctxstp(&mut self) -> UCTXSTP_W<'_>

Bit 2 - Transmit STOP condition in master mode

pub fn uctxnack(&mut self) -> UCTXNACK_W<'_>

Bit 3 - Transmit a NACK

pub fn uctr(&mut self) -> UCTR_W<'_>

Bit 4 - Transmitter/receiver

pub fn uctxack(&mut self) -> UCTXACK_W<'_>

Bit 5 - Transmit ACK condition in slave mode

pub fn ucssel(&mut self) -> UCSSEL_W<'_>

Bits 6:7 - eUSCI_B clock source select

pub fn ucsync(&mut self) -> UCSYNC_W<'_>

Bit 8 - Synchronous mode enable

pub fn ucmode(&mut self) -> UCMODE_W<'_>

Bits 9:10 - eUSCI_B mode

pub fn ucmst(&mut self) -> UCMST_W<'_>

Bit 11 - Master mode select

pub fn ucmm(&mut self) -> UCMM_W<'_>

Bit 13 - Multi-master environment select

pub fn ucsla10(&mut self) -> UCSLA10_W<'_>

Bit 14 - Slave addressing mode select

pub fn uca10(&mut self) -> UCA10_W<'_>

Bit 15 - Own addressing mode select

impl W<u16, Reg<u16, _UCB0CTLW0_SPI>>

pub fn ucswrst(&mut self) -> UCSWRST_W<'_>

Bit 0 - Software reset enable

pub fn ucstem(&mut self) -> UCSTEM_W<'_>

Bit 1 - STE mode select in master mode.

pub fn ucssel(&mut self) -> UCSSEL_W<'_>

Bits 6:7 - eUSCI_B clock source select

pub fn ucsync(&mut self) -> UCSYNC_W<'_>

Bit 8 - Synchronous mode enable

pub fn ucmode(&mut self) -> UCMODE_W<'_>

Bits 9:10 - eUSCI mode

pub fn ucmst(&mut self) -> UCMST_W<'_>

Bit 11 - Master mode select

pub fn uc7bit(&mut self) -> UC7BIT_W<'_>

Bit 12 - Character length

pub fn ucmsb(&mut self) -> UCMSB_W<'_>

Bit 13 - MSB first select

pub fn ucckpl(&mut self) -> UCCKPL_W<'_>

Bit 14 - Clock polarity select

pub fn ucckph(&mut self) -> UCCKPH_W<'_>

Bit 15 - Clock phase select

impl W<u16, Reg<u16, _UCB0CTLW1>>

pub fn ucglit(&mut self) -> UCGLIT_W<'_>

Bits 0:1 - Deglitch time

pub fn ucastp(&mut self) -> UCASTP_W<'_>

Bits 2:3 - Automatic STOP condition generation

pub fn ucswack(&mut self) -> UCSWACK_W<'_>

Bit 4 - SW or HW ACK control

pub fn ucstpnack(&mut self) -> UCSTPNACK_W<'_>

Bit 5 - ACK all master bytes

pub fn ucclto(&mut self) -> UCCLTO_W<'_>

Bits 6:7 - Clock low timeout select

pub fn ucetxint(&mut self) -> UCETXINT_W<'_>

Bit 8 - Early UCTXIFG0

impl W<u16, Reg<u16, _UCB0STATW_SPI>>

pub fn ucoe(&mut self) -> UCOE_W<'_>

Bit 5 - Overrun error flag

pub fn ucfe(&mut self) -> UCFE_W<'_>

Bit 6 - Framing error flag

pub fn uclisten(&mut self) -> UCLISTEN_W<'_>

Bit 7 - Listen enable

impl W<u16, Reg<u16, _UCB0TBCNT>>

pub fn uctbcnt(&mut self) -> UCTBCNT_W<'_>

Bits 0:7 - Byte counter threshold value

impl W<u16, Reg<u16, _UCB0TXBUF>>

pub fn uctxbuf(&mut self) -> UCTXBUF_W<'_>

Bits 0:7 - Transmit data buffer

impl W<u16, Reg<u16, _UCB0TXBUF_SPI>>

pub fn uctxbuf(&mut self) -> UCTXBUF_W<'_>

Bits 0:7 - Transmit data buffer

impl W<u16, Reg<u16, _UCB0I2COA0>>

pub fn i2coa0(&mut self) -> I2COA0_W<'_>

Bits 0:9 - I2C own address

pub fn ucoaen(&mut self) -> UCOAEN_W<'_>

Bit 10 - Own Address enable register

pub fn ucgcen(&mut self) -> UCGCEN_W<'_>

Bit 15 - General call response enable

impl W<u16, Reg<u16, _UCB0I2COA1>>

pub fn i2coa1(&mut self) -> I2COA1_W<'_>

Bits 0:9 - I2C own address

pub fn ucoaen(&mut self) -> UCOAEN_W<'_>

Bit 10 - Own Address enable register

impl W<u16, Reg<u16, _UCB0I2COA2>>

pub fn i2coa2(&mut self) -> I2COA2_W<'_>

Bits 0:9 - I2C own address

pub fn ucoaen(&mut self) -> UCOAEN_W<'_>

Bit 10 - Own Address enable register

impl W<u16, Reg<u16, _UCB0I2COA3>>

pub fn i2coa3(&mut self) -> I2COA3_W<'_>

Bits 0:9 - I2C own address

pub fn ucoaen(&mut self) -> UCOAEN_W<'_>

Bit 10 - Own Address enable register

impl W<u16, Reg<u16, _UCB0ADDMASK>>

pub fn addmask(&mut self) -> ADDMASK_W<'_>

Bits 0:9 - Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1.

impl W<u16, Reg<u16, _UCB0I2CSA>>

pub fn i2csa(&mut self) -> I2CSA_W<'_>

Bits 0:9 - I2C slave address

impl W<u16, Reg<u16, _UCB0IE>>

pub fn ucrxie0(&mut self) -> UCRXIE0_W<'_>

Bit 0 - Receive interrupt enable 0

pub fn uctxie0(&mut self) -> UCTXIE0_W<'_>

Bit 1 - Transmit interrupt enable 0

pub fn ucsttie(&mut self) -> UCSTTIE_W<'_>

Bit 2 - START condition interrupt enable

pub fn ucstpie(&mut self) -> UCSTPIE_W<'_>

Bit 3 - STOP condition interrupt enable

pub fn ucalie(&mut self) -> UCALIE_W<'_>

Bit 4 - Arbitration lost interrupt enable

pub fn ucnackie(&mut self) -> UCNACKIE_W<'_>

Bit 5 - Not-acknowledge interrupt enable

pub fn ucbcntie(&mut self) -> UCBCNTIE_W<'_>

Bit 6 - Byte counter interrupt enable

pub fn uccltoie(&mut self) -> UCCLTOIE_W<'_>

Bit 7 - Clock low timeout interrupt enable

pub fn ucrxie1(&mut self) -> UCRXIE1_W<'_>

Bit 8 - Receive interrupt enable 1

pub fn uctxie1(&mut self) -> UCTXIE1_W<'_>

Bit 9 - Transmit interrupt enable 1

pub fn ucrxie2(&mut self) -> UCRXIE2_W<'_>

Bit 10 - Receive interrupt enable 2

pub fn uctxie2(&mut self) -> UCTXIE2_W<'_>

Bit 11 - Transmit interrupt enable 2

pub fn ucrxie3(&mut self) -> UCRXIE3_W<'_>

Bit 12 - Receive interrupt enable 3

pub fn uctxie3(&mut self) -> UCTXIE3_W<'_>

Bit 13 - Transmit interrupt enable 3

pub fn ucbit9ie(&mut self) -> UCBIT9IE_W<'_>

Bit 14 - Bit position 9 interrupt enable

impl W<u16, Reg<u16, _UCB0IE_SPI>>

pub fn ucrxie(&mut self) -> UCRXIE_W<'_>

Bit 0 - Receive interrupt enable

pub fn uctxie(&mut self) -> UCTXIE_W<'_>

Bit 1 - Transmit interrupt enable

impl W<u16, Reg<u16, _UCB0IFG>>

pub fn ucrxifg0(&mut self) -> UCRXIFG0_W<'_>

Bit 0 - eUSCI_B receive interrupt flag 0

pub fn uctxifg0(&mut self) -> UCTXIFG0_W<'_>

Bit 1 - eUSCI_B transmit interrupt flag 0

pub fn ucsttifg(&mut self) -> UCSTTIFG_W<'_>

Bit 2 - START condition interrupt flag

pub fn ucstpifg(&mut self) -> UCSTPIFG_W<'_>

Bit 3 - STOP condition interrupt flag

pub fn ucalifg(&mut self) -> UCALIFG_W<'_>

Bit 4 - Arbitration lost interrupt flag

pub fn ucnackifg(&mut self) -> UCNACKIFG_W<'_>

Bit 5 - Not-acknowledge received interrupt flag

pub fn ucbcntifg(&mut self) -> UCBCNTIFG_W<'_>

Bit 6 - Byte counter interrupt flag

pub fn uccltoifg(&mut self) -> UCCLTOIFG_W<'_>

Bit 7 - Clock low timeout interrupt flag

pub fn ucrxifg1(&mut self) -> UCRXIFG1_W<'_>

Bit 8 - eUSCI_B receive interrupt flag 1

pub fn uctxifg1(&mut self) -> UCTXIFG1_W<'_>

Bit 9 - eUSCI_B transmit interrupt flag 1

pub fn ucrxifg2(&mut self) -> UCRXIFG2_W<'_>

Bit 10 - eUSCI_B receive interrupt flag 2

pub fn uctxifg2(&mut self) -> UCTXIFG2_W<'_>

Bit 11 - eUSCI_B transmit interrupt flag 2

pub fn ucrxifg3(&mut self) -> UCRXIFG3_W<'_>

Bit 12 - eUSCI_B receive interrupt flag 3

pub fn uctxifg3(&mut self) -> UCTXIFG3_W<'_>

Bit 13 - eUSCI_B transmit interrupt flag 3

pub fn ucbit9ifg(&mut self) -> UCBIT9IFG_W<'_>

Bit 14 - Bit position 9 interrupt flag

impl W<u16, Reg<u16, _UCB0IFG_SPI>>

pub fn ucrxifg(&mut self) -> UCRXIFG_W<'_>

Bit 0 - Receive interrupt flag

pub fn uctxifg(&mut self) -> UCTXIFG_W<'_>

Bit 1 - Transmit interrupt flag

impl W<u16, Reg<u16, _UCA1CTLW0>>

pub fn ucswrst(&mut self) -> UCSWRST_W<'_>

Bit 0 - Software reset enable

pub fn uctxbrk(&mut self) -> UCTXBRK_W<'_>

Bit 1 - Transmit break

pub fn uctxaddr(&mut self) -> UCTXADDR_W<'_>

Bit 2 - Transmit address

pub fn ucdorm(&mut self) -> UCDORM_W<'_>

Bit 3 - Dormant

pub fn ucbrkie(&mut self) -> UCBRKIE_W<'_>

Bit 4 - Receive break character interrupt enable

pub fn ucrxeie(&mut self) -> UCRXEIE_W<'_>

Bit 5 - Receive erroneous-character interrupt enable

pub fn ucssel(&mut self) -> UCSSEL_W<'_>

Bits 6:7 - eUSCI_A clock source select

pub fn ucsync(&mut self) -> UCSYNC_W<'_>

Bit 8 - Synchronous mode enable

pub fn ucmode(&mut self) -> UCMODE_W<'_>

Bits 9:10 - eUSCI_A mode

pub fn ucspb(&mut self) -> UCSPB_W<'_>

Bit 11 - Stop bit select

pub fn uc7bit(&mut self) -> UC7BIT_W<'_>

Bit 12 - Character length

pub fn ucmsb(&mut self) -> UCMSB_W<'_>

Bit 13 - MSB first select

pub fn ucpar(&mut self) -> UCPAR_W<'_>

Bit 14 - Parity select

pub fn ucpen(&mut self) -> UCPEN_W<'_>

Bit 15 - Parity enable

impl W<u16, Reg<u16, _UCA1CTLW0_SPI>>

pub fn ucswrst(&mut self) -> UCSWRST_W<'_>

Bit 0 - Software reset enable

pub fn ucstem(&mut self) -> UCSTEM_W<'_>

Bit 1 - STE mode select in master mode.

pub fn ucssel(&mut self) -> UCSSEL_W<'_>

Bits 6:7 - eUSCI_A clock source select

pub fn ucsync(&mut self) -> UCSYNC_W<'_>

Bit 8 - Synchronous mode enable

pub fn ucmode(&mut self) -> UCMODE_W<'_>

Bits 9:10 - eUSCI mode

pub fn ucmst(&mut self) -> UCMST_W<'_>

Bit 11 - Master mode select

pub fn uc7bit(&mut self) -> UC7BIT_W<'_>

Bit 12 - Character length

pub fn ucmsb(&mut self) -> UCMSB_W<'_>

Bit 13 - MSB first select

pub fn ucckpl(&mut self) -> UCCKPL_W<'_>

Bit 14 - Clock polarity select

pub fn ucckph(&mut self) -> UCCKPH_W<'_>

Bit 15 - Clock phase select

impl W<u16, Reg<u16, _UCA1CTLW1>>

pub fn ucglit(&mut self) -> UCGLIT_W<'_>

Bits 0:1 - Deglitch time

impl W<u16, Reg<u16, _UCA1MCTLW>>

pub fn ucos16(&mut self) -> UCOS16_W<'_>

Bit 0 - Oversampling mode enabled

pub fn ucbrf(&mut self) -> UCBRF_W<'_>

Bits 4:7 - First modulation stage select

pub fn ucbrs(&mut self) -> UCBRS_W<'_>

Bits 8:15 - Second modulation stage select

impl W<u16, Reg<u16, _UCA1STATW>>

pub fn ucaddr_ucidle(&mut self) -> UCADDR_UCIDLE_W<'_>

Bit 1 - Address received / Idle line detected

pub fn ucrxerr(&mut self) -> UCRXERR_W<'_>

Bit 2 - Receive error flag

pub fn ucbrk(&mut self) -> UCBRK_W<'_>

Bit 3 - Break detect flag

pub fn ucpe(&mut self) -> UCPE_W<'_>

Bit 4 - Parity error flag. When UCPEN = 0, UCPE is read as 0. UCPE is cleared when UCAxRXBUF is read.

pub fn ucoe(&mut self) -> UCOE_W<'_>

Bit 5 - Overrun error flag

pub fn ucfe(&mut self) -> UCFE_W<'_>

Bit 6 - Framing error flag

pub fn uclisten(&mut self) -> UCLISTEN_W<'_>

Bit 7 - Listen enable

impl W<u16, Reg<u16, _UCA1STATW_SPI>>

pub fn ucoe(&mut self) -> UCOE_W<'_>

Bit 5 - Overrun error flag

pub fn ucfe(&mut self) -> UCFE_W<'_>

Bit 6 - Framing error flag

pub fn uclisten(&mut self) -> UCLISTEN_W<'_>

Bit 7 - Listen enable

impl W<u16, Reg<u16, _UCA1TXBUF>>

pub fn uctxbuf(&mut self) -> UCTXBUF_W<'_>

Bits 0:7 - Transmit data buffer

impl W<u16, Reg<u16, _UCA1TXBUF_SPI>>

pub fn uctxbuf(&mut self) -> UCTXBUF_W<'_>

Bits 0:7 - Transmit data buffer

impl W<u16, Reg<u16, _UCA1ABCTL>>

pub fn ucabden(&mut self) -> UCABDEN_W<'_>

Bit 0 - Automatic baud-rate detect enable

pub fn ucbtoe(&mut self) -> UCBTOE_W<'_>

Bit 2 - Break time out error

pub fn ucstoe(&mut self) -> UCSTOE_W<'_>

Bit 3 - Synch field time out error

pub fn ucdelim(&mut self) -> UCDELIM_W<'_>

Bits 4:5 - Break/synch delimiter length

impl W<u16, Reg<u16, _UCA1IRCTL>>

pub fn uciren(&mut self) -> UCIREN_W<'_>

Bit 0 - IrDA encoder/decoder enable

pub fn ucirtxclk(&mut self) -> UCIRTXCLK_W<'_>

Bit 1 - IrDA transmit pulse clock select

pub fn ucirtxpl(&mut self) -> UCIRTXPL_W<'_>

Bits 2:7 - Transmit pulse length

pub fn ucirrxfe(&mut self) -> UCIRRXFE_W<'_>

Bit 8 - IrDA receive filter enabled

pub fn ucirrxpl(&mut self) -> UCIRRXPL_W<'_>

Bit 9 - IrDA receive input UCAxRXD polarity

pub fn ucirrxfl(&mut self) -> UCIRRXFL_W<'_>

Bits 10:15 - Receive filter length

impl W<u16, Reg<u16, _UCA1IE>>

pub fn ucrxie(&mut self) -> UCRXIE_W<'_>

Bit 0 - Receive interrupt enable

pub fn uctxie(&mut self) -> UCTXIE_W<'_>

Bit 1 - Transmit interrupt enable

pub fn ucsttie(&mut self) -> UCSTTIE_W<'_>

Bit 2 - Start bit interrupt enable

pub fn uctxcptie(&mut self) -> UCTXCPTIE_W<'_>

Bit 3 - Transmit complete interrupt enable

impl W<u16, Reg<u16, _UCA1IE_SPI>>

pub fn ucrxie(&mut self) -> UCRXIE_W<'_>

Bit 0 - Receive interrupt enable

pub fn uctxie(&mut self) -> UCTXIE_W<'_>

Bit 1 - Transmit interrupt enable

impl W<u16, Reg<u16, _UCA1IFG>>

pub fn ucrxifg(&mut self) -> UCRXIFG_W<'_>

Bit 0 - Receive interrupt flag

pub fn uctxifg(&mut self) -> UCTXIFG_W<'_>

Bit 1 - Transmit interrupt flag

pub fn ucsttifg(&mut self) -> UCSTTIFG_W<'_>

Bit 2 - Start bit interrupt flag

pub fn uctxcptifg(&mut self) -> UCTXCPTIFG_W<'_>

Bit 3 - Transmit ready interrupt enable

impl W<u16, Reg<u16, _UCA1IFG_SPI>>

pub fn ucrxifg(&mut self) -> UCRXIFG_W<'_>

Bit 0 - Receive interrupt flag

pub fn uctxifg(&mut self) -> UCTXIFG_W<'_>

Bit 1 - Transmit interrupt flag

impl W<u16, Reg<u16, _UCB1CTLW0>>

pub fn ucswrst(&mut self) -> UCSWRST_W<'_>

Bit 0 - Software reset enable

pub fn uctxstt(&mut self) -> UCTXSTT_W<'_>

Bit 1 - Transmit START condition in master mode

pub fn uctxstp(&mut self) -> UCTXSTP_W<'_>

Bit 2 - Transmit STOP condition in master mode

pub fn uctxnack(&mut self) -> UCTXNACK_W<'_>

Bit 3 - Transmit a NACK

pub fn uctr(&mut self) -> UCTR_W<'_>

Bit 4 - Transmitter/receiver

pub fn uctxack(&mut self) -> UCTXACK_W<'_>

Bit 5 - Transmit ACK condition in slave mode

pub fn ucssel(&mut self) -> UCSSEL_W<'_>

Bits 6:7 - eUSCI_B clock source select

pub fn ucsync(&mut self) -> UCSYNC_W<'_>

Bit 8 - Synchronous mode enable

pub fn ucmode(&mut self) -> UCMODE_W<'_>

Bits 9:10 - eUSCI_B mode

pub fn ucmst(&mut self) -> UCMST_W<'_>

Bit 11 - Master mode select

pub fn ucmm(&mut self) -> UCMM_W<'_>

Bit 13 - Multi-master environment select

pub fn ucsla10(&mut self) -> UCSLA10_W<'_>

Bit 14 - Slave addressing mode select

pub fn uca10(&mut self) -> UCA10_W<'_>

Bit 15 - Own addressing mode select

impl W<u16, Reg<u16, _UCB1CTLW0_SPI>>

pub fn ucswrst(&mut self) -> UCSWRST_W<'_>

Bit 0 - Software reset enable

pub fn ucstem(&mut self) -> UCSTEM_W<'_>

Bit 1 - STE mode select in master mode.

pub fn ucssel(&mut self) -> UCSSEL_W<'_>

Bits 6:7 - eUSCI_B clock source select

pub fn ucsync(&mut self) -> UCSYNC_W<'_>

Bit 8 - Synchronous mode enable

pub fn ucmode(&mut self) -> UCMODE_W<'_>

Bits 9:10 - eUSCI mode

pub fn ucmst(&mut self) -> UCMST_W<'_>

Bit 11 - Master mode select

pub fn uc7bit(&mut self) -> UC7BIT_W<'_>

Bit 12 - Character length

pub fn ucmsb(&mut self) -> UCMSB_W<'_>

Bit 13 - MSB first select

pub fn ucckpl(&mut self) -> UCCKPL_W<'_>

Bit 14 - Clock polarity select

pub fn ucckph(&mut self) -> UCCKPH_W<'_>

Bit 15 - Clock phase select

impl W<u16, Reg<u16, _UCB1CTLW1>>

pub fn ucglit(&mut self) -> UCGLIT_W<'_>

Bits 0:1 - Deglitch time

pub fn ucastp(&mut self) -> UCASTP_W<'_>

Bits 2:3 - Automatic STOP condition generation

pub fn ucswack(&mut self) -> UCSWACK_W<'_>

Bit 4 - SW or HW ACK control

pub fn ucstpnack(&mut self) -> UCSTPNACK_W<'_>

Bit 5 - ACK all master bytes

pub fn ucclto(&mut self) -> UCCLTO_W<'_>

Bits 6:7 - Clock low timeout select

pub fn ucetxint(&mut self) -> UCETXINT_W<'_>

Bit 8 - Early UCTXIFG0

impl W<u16, Reg<u16, _UCB1STATW_SPI>>

pub fn ucoe(&mut self) -> UCOE_W<'_>

Bit 5 - Overrun error flag

pub fn ucfe(&mut self) -> UCFE_W<'_>

Bit 6 - Framing error flag

pub fn uclisten(&mut self) -> UCLISTEN_W<'_>

Bit 7 - Listen enable

impl W<u16, Reg<u16, _UCB1TBCNT>>

pub fn uctbcnt(&mut self) -> UCTBCNT_W<'_>

Bits 0:7 - Byte counter threshold value

impl W<u16, Reg<u16, _UCB1TXBUF>>

pub fn uctxbuf(&mut self) -> UCTXBUF_W<'_>

Bits 0:7 - Transmit data buffer

impl W<u16, Reg<u16, _UCB1TXBUF_SPI>>

pub fn uctxbuf(&mut self) -> UCTXBUF_W<'_>

Bits 0:7 - Transmit data buffer

impl W<u16, Reg<u16, _UCB1I2COA0>>

pub fn i2coa0(&mut self) -> I2COA0_W<'_>

Bits 0:9 - I2C own address

pub fn ucoaen(&mut self) -> UCOAEN_W<'_>

Bit 10 - Own Address enable register

pub fn ucgcen(&mut self) -> UCGCEN_W<'_>

Bit 15 - General call response enable

impl W<u16, Reg<u16, _UCB1I2COA1>>

pub fn i2coa1(&mut self) -> I2COA1_W<'_>

Bits 0:9 - I2C own address

pub fn ucoaen(&mut self) -> UCOAEN_W<'_>

Bit 10 - Own Address enable register

impl W<u16, Reg<u16, _UCB1I2COA2>>

pub fn i2coa2(&mut self) -> I2COA2_W<'_>

Bits 0:9 - I2C own address

pub fn ucoaen(&mut self) -> UCOAEN_W<'_>

Bit 10 - Own Address enable register

impl W<u16, Reg<u16, _UCB1I2COA3>>

pub fn i2coa3(&mut self) -> I2COA3_W<'_>

Bits 0:9 - I2C own address

pub fn ucoaen(&mut self) -> UCOAEN_W<'_>

Bit 10 - Own Address enable register

impl W<u16, Reg<u16, _UCB1ADDMASK>>

pub fn addmask(&mut self) -> ADDMASK_W<'_>

Bits 0:9 - Address Mask Register. By clearing the corresponding bit of the own address, this bit is a don't care when comparing the address on the bus to the own address. Using this method, it is possible to react on more than one slave address. When all bits of ADDMASKx are set, the address mask feature is deactivated. Modify only when UCSWRST = 1.

impl W<u16, Reg<u16, _UCB1I2CSA>>

pub fn i2csa(&mut self) -> I2CSA_W<'_>

Bits 0:9 - I2C slave address

impl W<u16, Reg<u16, _UCB1IE>>

pub fn ucrxie0(&mut self) -> UCRXIE0_W<'_>

Bit 0 - Receive interrupt enable 0

pub fn uctxie0(&mut self) -> UCTXIE0_W<'_>

Bit 1 - Transmit interrupt enable 0

pub fn ucsttie(&mut self) -> UCSTTIE_W<'_>

Bit 2 - START condition interrupt enable

pub fn ucstpie(&mut self) -> UCSTPIE_W<'_>

Bit 3 - STOP condition interrupt enable

pub fn ucalie(&mut self) -> UCALIE_W<'_>

Bit 4 - Arbitration lost interrupt enable

pub fn ucnackie(&mut self) -> UCNACKIE_W<'_>

Bit 5 - Not-acknowledge interrupt enable

pub fn ucbcntie(&mut self) -> UCBCNTIE_W<'_>

Bit 6 - Byte counter interrupt enable

pub fn uccltoie(&mut self) -> UCCLTOIE_W<'_>

Bit 7 - Clock low timeout interrupt enable

pub fn ucrxie1(&mut self) -> UCRXIE1_W<'_>

Bit 8 - Receive interrupt enable 1

pub fn uctxie1(&mut self) -> UCTXIE1_W<'_>

Bit 9 - Transmit interrupt enable 1

pub fn ucrxie2(&mut self) -> UCRXIE2_W<'_>

Bit 10 - Receive interrupt enable 2

pub fn uctxie2(&mut self) -> UCTXIE2_W<'_>

Bit 11 - Transmit interrupt enable 2

pub fn ucrxie3(&mut self) -> UCRXIE3_W<'_>

Bit 12 - Receive interrupt enable 3

pub fn uctxie3(&mut self) -> UCTXIE3_W<'_>

Bit 13 - Transmit interrupt enable 3

pub fn ucbit9ie(&mut self) -> UCBIT9IE_W<'_>

Bit 14 - Bit position 9 interrupt enable

impl W<u16, Reg<u16, _UCB1IE_SPI>>

pub fn ucrxie(&mut self) -> UCRXIE_W<'_>

Bit 0 - Receive interrupt enable

pub fn uctxie(&mut self) -> UCTXIE_W<'_>

Bit 1 - Transmit interrupt enable

impl W<u16, Reg<u16, _UCB1IFG>>

pub fn ucrxifg0(&mut self) -> UCRXIFG0_W<'_>

Bit 0 - eUSCI_B receive interrupt flag 0

pub fn uctxifg0(&mut self) -> UCTXIFG0_W<'_>

Bit 1 - eUSCI_B transmit interrupt flag 0

pub fn ucsttifg(&mut self) -> UCSTTIFG_W<'_>

Bit 2 - START condition interrupt flag

pub fn ucstpifg(&mut self) -> UCSTPIFG_W<'_>

Bit 3 - STOP condition interrupt flag

pub fn ucalifg(&mut self) -> UCALIFG_W<'_>

Bit 4 - Arbitration lost interrupt flag

pub fn ucnackifg(&mut self) -> UCNACKIFG_W<'_>

Bit 5 - Not-acknowledge received interrupt flag

pub fn ucbcntifg(&mut self) -> UCBCNTIFG_W<'_>

Bit 6 - Byte counter interrupt flag

pub fn uccltoifg(&mut self) -> UCCLTOIFG_W<'_>

Bit 7 - Clock low timeout interrupt flag

pub fn ucrxifg1(&mut self) -> UCRXIFG1_W<'_>

Bit 8 - eUSCI_B receive interrupt flag 1

pub fn uctxifg1(&mut self) -> UCTXIFG1_W<'_>

Bit 9 - eUSCI_B transmit interrupt flag 1

pub fn ucrxifg2(&mut self) -> UCRXIFG2_W<'_>

Bit 10 - eUSCI_B receive interrupt flag 2

pub fn uctxifg2(&mut self) -> UCTXIFG2_W<'_>

Bit 11 - eUSCI_B transmit interrupt flag 2

pub fn ucrxifg3(&mut self) -> UCRXIFG3_W<'_>

Bit 12 - eUSCI_B receive interrupt flag 3

pub fn uctxifg3(&mut self) -> UCTXIFG3_W<'_>

Bit 13 - eUSCI_B transmit interrupt flag 3

pub fn ucbit9ifg(&mut self) -> UCBIT9IFG_W<'_>

Bit 14 - Bit position 9 interrupt flag

impl W<u16, Reg<u16, _UCB1IFG_SPI>>

pub fn ucrxifg(&mut self) -> UCRXIFG_W<'_>

Bit 0 - Receive interrupt flag

pub fn uctxifg(&mut self) -> UCTXIFG_W<'_>

Bit 1 - Transmit interrupt flag

impl W<u16, Reg<u16, _ICCSC>>

pub fn iccen(&mut self) -> ICCEN_W<'_>

Bit 7 - ICC enable

impl W<u16, Reg<u16, _ICCILSR0>>

pub fn ilsr0(&mut self) -> ILSR0_W<'_>

Bits 0:1 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRx bit.

pub fn ilsr1(&mut self) -> ILSR1_W<'_>

Bits 2:3 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRx bit.

pub fn ilsr2(&mut self) -> ILSR2_W<'_>

Bits 4:5 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRx bit.

pub fn ilsr3(&mut self) -> ILSR3_W<'_>

Bits 6:7 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRx bit.

pub fn ilsr4(&mut self) -> ILSR4_W<'_>

Bits 8:9 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRx bit.

pub fn ilsr5(&mut self) -> ILSR5_W<'_>

Bits 10:11 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRx bit.

pub fn ilsr6(&mut self) -> ILSR6_W<'_>

Bits 12:13 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRx bit.

pub fn ilsr7(&mut self) -> ILSR7_W<'_>

Bits 14:15 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRx bit.

impl W<u16, Reg<u16, _ICCILSR1>>

pub fn ilsr8(&mut self) -> ILSR8_W<'_>

Bits 0:1 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr9(&mut self) -> ILSR9_W<'_>

Bits 2:3 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr10(&mut self) -> ILSR10_W<'_>

Bits 4:5 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr11(&mut self) -> ILSR11_W<'_>

Bits 6:7 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit

pub fn ilsr12(&mut self) -> ILSR12_W<'_>

Bits 8:9 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr13(&mut self) -> ILSR13_W<'_>

Bits 10:11 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr14(&mut self) -> ILSR14_W<'_>

Bits 12:13 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr15(&mut self) -> ILSR15_W<'_>

Bits 14:15 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

impl W<u16, Reg<u16, _ICCILSR2>>

pub fn ilsr16(&mut self) -> ILSR16_W<'_>

Bits 0:1 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr17(&mut self) -> ILSR17_W<'_>

Bits 2:3 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit

pub fn ilsr18(&mut self) -> ILSR18_W<'_>

Bits 4:5 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr19(&mut self) -> ILSR19_W<'_>

Bits 6:7 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr20(&mut self) -> ILSR20_W<'_>

Bits 8:9 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr21(&mut self) -> ILSR21_W<'_>

Bits 10:11 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr22(&mut self) -> ILSR22_W<'_>

Bits 12:13 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each

pub fn ilsr23(&mut self) -> ILSR23_W<'_>

Bits 14:15 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each

impl W<u16, Reg<u16, _ICCILSR3>>

pub fn ilsr24(&mut self) -> ILSR24_W<'_>

Bits 0:1 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr25(&mut self) -> ILSR25_W<'_>

Bits 2:3 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr26(&mut self) -> ILSR26_W<'_>

Bits 4:5 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr27(&mut self) -> ILSR27_W<'_>

Bits 6:7 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr28(&mut self) -> ILSR28_W<'_>

Bits 8:9 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr29(&mut self) -> ILSR29_W<'_>

Bits 10:11 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr30(&mut self) -> ILSR30_W<'_>

Bits 12:13 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

pub fn ilsr31(&mut self) -> ILSR31_W<'_>

Bits 14:15 - Sets the interrupt level for this interrupt source. Maskable interrupt sources only. See the device-specific data sheet to determine the interrupt source for each ILSRxx bit.

impl W<u16, Reg<u16, _ADCCTL0>>

pub fn adcsc(&mut self) -> ADCSC_W<'_>

Bit 0 - start conversion

pub fn adcenc(&mut self) -> ADCENC_W<'_>

Bit 1 - enable conversion

pub fn adcon(&mut self) -> ADCON_W<'_>

Bit 4 - ADC on

pub fn adcmsc(&mut self) -> ADCMSC_W<'_>

Bit 7 - sample-and-hold time.

pub fn adcsht(&mut self) -> ADCSHT_W<'_>

Bits 8:11 - sample-and-hold time.

impl W<u16, Reg<u16, _ADCCTL1>>

pub fn adcconseq(&mut self) -> ADCCONSEQ_W<'_>

Bits 1:2 - conversion sequence mode select

pub fn adcssel(&mut self) -> ADCSSEL_W<'_>

Bits 3:4 - clock source select

pub fn adcdiv(&mut self) -> ADCDIV_W<'_>

Bits 5:7 - clock divider

pub fn adcissh(&mut self) -> ADCISSH_W<'_>

Bit 8 - invert signal sample-and-hold

pub fn adcshp(&mut self) -> ADCSHP_W<'_>

Bit 9 - sample-and-hold pulse-mode select

pub fn adcshs(&mut self) -> ADCSHS_W<'_>

Bits 10:11 - sample-and-hold source select

impl W<u16, Reg<u16, _ADCCTL2>>

pub fn adcdf(&mut self) -> ADCDF_W<'_>

Bit 3 - data read-back format

pub fn adcres(&mut self) -> ADCRES_W<'_>

Bits 4:5 - resolution

pub fn adcsr(&mut self) -> ADCSR_W<'_>

Bit 2 - ADC sampling rate.

pub fn adcpdiv(&mut self) -> ADCPDIV_W<'_>

Bits 8:9 - ADC predivider. This bit predivides the selected ADC clock source before it gets divided again using ADCDIVx.

impl W<u16, Reg<u16, _ADCMCTL0>>

pub fn adcinch(&mut self) -> ADCINCH_W<'_>

Bits 0:3 - Input channel select

pub fn adcsref(&mut self) -> ADCSREF_W<'_>

Bits 4:6 - Select reference. It is not recommended to change this setting while a conversion is ongoing. Can be modified only when ADCENC = 0. Resetting ADCENC = 0 by software and changing these fields immediately shows an effect when a conversion is active.

pub fn expchen(&mut self) -> EXPCHEN_W<'_>

Bit 8 - ADC input channels expanded

impl W<u16, Reg<u16, _ADCIE>>

pub fn adcie0(&mut self) -> ADCIE0_W<'_>

Bit 0 - Interrupt enable. This bits enable or disable the interrupt request for a completed ADC conversion.

pub fn adcinie(&mut self) -> ADCINIE_W<'_>

Bit 1 - Interrupt enable for the inside of window interrupt of the window comparator.

pub fn adcloie(&mut self) -> ADCLOIE_W<'_>

Bit 2 - Interrupt enable for the below lower threshold interrupt of the window comparator.

pub fn adchiie(&mut self) -> ADCHIIE_W<'_>

Bit 3 - Interrupt enable for the above upper threshold interrupt of the window comparator.

pub fn adcovie(&mut self) -> ADCOVIE_W<'_>

Bit 4 - ADCMEM0 overflow interrupt enable.

pub fn adctovie(&mut self) -> ADCTOVIE_W<'_>

Bit 5 - ADC conversion-time-overflow interrupt enable.

impl W<u16, Reg<u16, _ADCIFG>>

pub fn adcifg0(&mut self) -> ADCIFG0_W<'_>

Bit 0 - ADCMEM0 interrupt flag

pub fn adcinifg(&mut self) -> ADCINIFG_W<'_>

Bit 1 - The ADCINIFG is set when the result of the current ADC conversion is within the thresholds defined by the window comparator threshold registers.

pub fn adcloifg(&mut self) -> ADCLOIFG_W<'_>

Bit 2 - The ADCLOIFG is set when the result of the current ADC conversion is below the lower threshold defined by the window comparator lower threshold register.

pub fn adchiifg(&mut self) -> ADCHIIFG_W<'_>

Bit 3 - The ADCHIIFG is set when the result of the current ADC conversion is greater than the upper threshold defined by the window comparator upper threshold register.

pub fn adcovifg(&mut self) -> ADCOVIFG_W<'_>

Bit 4 - The ADCOVIFG is set when the ADCMEM0 register is written before the last conversion result has been read.

pub fn adctovifg(&mut self) -> ADCTOVIFG_W<'_>

Bit 5 - The ADCTOVIFG is set when an ADC conversion is triggered before the actual conversion has completed.

impl W<u16, Reg<u16, _ADCIV>>

pub fn adciv(&mut self) -> ADCIV_W<'_>

Bits 0:15 - interrupt vector value

impl W<u16, Reg<u16, _CPCTL0>>

pub fn cppen(&mut self) -> CPPEN_W<'_>

Bit 4 - Channel input enable for the V+ terminal

pub fn cpnsel(&mut self) -> CPNSEL_W<'_>

Bits 8:10 - Channel input selected for the - terminal

pub fn cpnen(&mut self) -> CPNEN_W<'_>

Bit 12 - Channel input enable for the - terminal

pub fn cppsel(&mut self) -> CPPSEL_W<'_>

Bits 0:2 - Channel input selected for the V+ terminal

impl W<u16, Reg<u16, _CPCTL1>>

pub fn cpinv(&mut self) -> CPINV_W<'_>

Bit 1 - Comparator output polarity

pub fn cpies(&mut self) -> CPIES_W<'_>

Bit 4 - Interrupt edge select for CEIIFG and CEIFG

pub fn cpflt(&mut self) -> CPFLT_W<'_>

Bit 5 - Analog Output Low Pass filter Selection. Changing CPFLT might set interrupt flag.

pub fn cpfltdly(&mut self) -> CPFLTDLY_W<'_>

Bits 6:7 - Analog Filter Delay selection. These bits are used to select the analog filter delay

pub fn cpmsel(&mut self) -> CPMSEL_W<'_>

Bit 8 - Power mode selection.

pub fn cpen(&mut self) -> CPEN_W<'_>

Bit 9 - Comparator enable/disable. This bit is used to disable/enable the comparator. When the comparator is disabled, the Comparator consumes no power.

pub fn cphsel(&mut self) -> CPHSEL_W<'_>

Bits 10:11 - Programable Hysteresis mode. These bits are used to select the Hysteresis mode.

pub fn cpie(&mut self) -> CPIE_W<'_>

Bit 14 - Comparator interrupt output enable bit

pub fn cpiie(&mut self) -> CPIIE_W<'_>

Bit 15 - Comparator inverted interrupt output enable bit

impl W<u16, Reg<u16, _CPINT>>

pub fn cpifg(&mut self) -> CPIFG_W<'_>

Bit 0 - Comparator output interrupt flag

pub fn cpiifg(&mut self) -> CPIIFG_W<'_>

Bit 1 - Comparator output inverted interrupt flag

impl W<u16, Reg<u16, _CPDACCTL>>

pub fn cpdacsw(&mut self) -> CPDACSW_W<'_>

Bit 0 - This bit is only valid when CPDACBUFS is set to 1.

pub fn cpdacbufs(&mut self) -> CPDACBUFS_W<'_>

Bit 1 - Comparator built-in DAC buffer controlled source selection.

pub fn cpdacrefs(&mut self) -> CPDACREFS_W<'_>

Bit 2 - Comparator built-in DAC reference voltage selection

pub fn cpdacen(&mut self) -> CPDACEN_W<'_>

Bit 7 - Comparator built-in DAC output control bit.

impl W<u16, Reg<u16, _CPDACDATA>>

pub fn cpdacbuf1(&mut self) -> CPDACBUF1_W<'_>

Bits 0:5 - 1st 6-bit DAC buffer Data

pub fn cpdacbuf2(&mut self) -> CPDACBUF2_W<'_>

Bits 8:13 - 2nd 6-bit DAC buffer Data

impl W<u16, Reg<u16, _CP1CTL0>>

pub fn cppen(&mut self) -> CPPEN_W<'_>

Bit 4 - Channel input enable for the V+ terminal

pub fn cpnsel(&mut self) -> CPNSEL_W<'_>

Bits 8:10 - Channel input selected for the - terminal

pub fn cpnen(&mut self) -> CPNEN_W<'_>

Bit 12 - Channel input enable for the - terminal

pub fn cppsel(&mut self) -> CPPSEL_W<'_>

Bits 0:2 - Channel input selected for the V+ terminal

impl W<u16, Reg<u16, _CP1CTL1>>

pub fn cpinv(&mut self) -> CPINV_W<'_>

Bit 1 - Comparator output polarity

pub fn cpies(&mut self) -> CPIES_W<'_>

Bit 4 - Interrupt edge select for CEIIFG and CEIFG

pub fn cpflt(&mut self) -> CPFLT_W<'_>

Bit 5 - Analog Output Low Pass filter Selection. Changing CPFLT might set interrupt flag.

pub fn cpfltdly(&mut self) -> CPFLTDLY_W<'_>

Bits 6:7 - Analog Filter Delay selection. These bits are used to select the analog filter delay

pub fn cpmsel(&mut self) -> CPMSEL_W<'_>

Bit 8 - Power mode selection.

pub fn cpen(&mut self) -> CPEN_W<'_>

Bit 9 - Comparator enable/disable. This bit is used to disable/enable the comparator. When the comparator is disabled, the Comparator consumes no power.

pub fn cphsel(&mut self) -> CPHSEL_W<'_>

Bits 10:11 - Programable Hysteresis mode. These bits are used to select the Hysteresis mode.

pub fn cpie(&mut self) -> CPIE_W<'_>

Bit 14 - Comparator interrupt output enable bit

pub fn cpiie(&mut self) -> CPIIE_W<'_>

Bit 15 - Comparator inverted interrupt output enable bit

impl W<u16, Reg<u16, _CP1INT>>

pub fn cpifg(&mut self) -> CPIFG_W<'_>

Bit 0 - Comparator output interrupt flag

pub fn cpiifg(&mut self) -> CPIIFG_W<'_>

Bit 1 - Comparator output inverted interrupt flag

impl W<u16, Reg<u16, _CP1DACCTL>>

pub fn cpdacsw(&mut self) -> CPDACSW_W<'_>

Bit 0 - This bit is only valid when CPDACBUFS is set to 1.

pub fn cpdacbufs(&mut self) -> CPDACBUFS_W<'_>

Bit 1 - Comparator built-in DAC buffer controlled source selection.

pub fn cpdacrefs(&mut self) -> CPDACREFS_W<'_>

Bit 2 - Comparator built-in DAC reference voltage selection

pub fn cpdacen(&mut self) -> CPDACEN_W<'_>

Bit 7 - Comparator built-in DAC output control bit.

impl W<u16, Reg<u16, _CP1DACDATA>>

pub fn cpdacbuf1(&mut self) -> CPDACBUF1_W<'_>

Bits 0:5 - 1st 6-bit DAC buffer Data

pub fn cpdacbuf2(&mut self) -> CPDACBUF2_W<'_>

Bits 8:13 - 2nd 6-bit DAC buffer Data

impl W<u16, Reg<u16, _SAC0OA>>

pub fn psel(&mut self) -> PSEL_W<'_>

Bits 0:1 - SAC OA Positive input source selection

pub fn pmuxen(&mut self) -> PMUXEN_W<'_>

Bit 3 - SAC Positive input MUX control.

pub fn nsel(&mut self) -> NSEL_W<'_>

Bits 4:5 - SAC OA Negative input source selection

pub fn nmuxen(&mut self) -> NMUXEN_W<'_>

Bit 7 - SAC Negative input MUX controL

pub fn oaen(&mut self) -> OAEN_W<'_>

Bit 8 - SAC OA Enable selection

pub fn oapm(&mut self) -> OAPM_W<'_>

Bit 9 - SAC OA power mode selection

pub fn sacen(&mut self) -> SACEN_W<'_>

Bit 10 - SAC Enable selection

impl W<u16, Reg<u16, _SAC0PGA>>

pub fn msel(&mut self) -> MSEL_W<'_>

Bits 0:1 - SAC PGA Mode Selection

pub fn gain(&mut self) -> GAIN_W<'_>

Bits 4:6 - SAC PGA Gain configuration

impl W<u16, Reg<u16, _SAC0DAC>>

pub fn dacen(&mut self) -> DACEN_W<'_>

Bit 0 - SAC DAC enable

pub fn dacie(&mut self) -> DACIE_W<'_>

Bit 1 - SAC DAC interrupt enable

pub fn dacdmae(&mut self) -> DACDMAE_W<'_>

Bit 2 - SAC DAC DMA request enable

pub fn daclsel(&mut self) -> DACLSEL_W<'_>

Bits 8:9 - SAC DAC load select. Selects the load trigger for the DAC latch.

pub fn dacsref(&mut self) -> DACSREF_W<'_>

Bit 12 - SAC DAC select reference voltage

impl W<u16, Reg<u16, _SAC0DAT>>

pub fn dacdata(&mut self) -> DACDATA_W<'_>

Bits 0:11 - SAC DAC data in unsigned format.

impl W<u16, Reg<u16, _SAC0DACSTS>>

pub fn dacifg(&mut self) -> DACIFG_W<'_>

Bit 0 - SAC DAC data update flag

impl W<u16, Reg<u16, _SAC1OA>>

pub fn psel(&mut self) -> PSEL_W<'_>

Bits 0:1 - SAC OA Positive input source selection

pub fn pmuxen(&mut self) -> PMUXEN_W<'_>

Bit 3 - SAC Positive input MUX control.

pub fn nsel(&mut self) -> NSEL_W<'_>

Bits 4:5 - SAC OA Negative input source selection

pub fn nmuxen(&mut self) -> NMUXEN_W<'_>

Bit 7 - SAC Negative input MUX controL

pub fn oaen(&mut self) -> OAEN_W<'_>

Bit 8 - SAC OA Enable selection

pub fn oapm(&mut self) -> OAPM_W<'_>

Bit 9 - SAC OA power mode selection

pub fn sacen(&mut self) -> SACEN_W<'_>

Bit 10 - SAC Enable selection

impl W<u16, Reg<u16, _SAC1PGA>>

pub fn msel(&mut self) -> MSEL_W<'_>

Bits 0:1 - SAC PGA Mode Selection

pub fn gain(&mut self) -> GAIN_W<'_>

Bits 4:6 - SAC PGA Gain configuration

impl W<u16, Reg<u16, _SAC1DAC>>

pub fn dacen(&mut self) -> DACEN_W<'_>

Bit 0 - SAC DAC enable

pub fn dacie(&mut self) -> DACIE_W<'_>

Bit 1 - SAC DAC interrupt enable

pub fn dacdmae(&mut self) -> DACDMAE_W<'_>

Bit 2 - SAC DAC DMA request enable

pub fn daclsel(&mut self) -> DACLSEL_W<'_>

Bits 8:9 - SAC DAC load select. Selects the load trigger for the DAC latch.

pub fn dacsref(&mut self) -> DACSREF_W<'_>

Bit 12 - SAC DAC select reference voltage

impl W<u16, Reg<u16, _SAC1DAT>>

pub fn dacdata(&mut self) -> DACDATA_W<'_>

Bits 0:11 - SAC DAC data in unsigned format.

impl W<u16, Reg<u16, _SAC1DACSTS>>

pub fn dacifg(&mut self) -> DACIFG_W<'_>

Bit 0 - SAC DAC data update flag

impl W<u16, Reg<u16, _SAC2OA>>

pub fn psel(&mut self) -> PSEL_W<'_>

Bits 0:1 - SAC OA Positive input source selection

pub fn pmuxen(&mut self) -> PMUXEN_W<'_>

Bit 3 - SAC Positive input MUX control.

pub fn nsel(&mut self) -> NSEL_W<'_>

Bits 4:5 - SAC OA Negative input source selection

pub fn nmuxen(&mut self) -> NMUXEN_W<'_>

Bit 7 - SAC Negative input MUX controL

pub fn oaen(&mut self) -> OAEN_W<'_>

Bit 8 - SAC OA Enable selection

pub fn oapm(&mut self) -> OAPM_W<'_>

Bit 9 - SAC OA power mode selection

pub fn sacen(&mut self) -> SACEN_W<'_>

Bit 10 - SAC Enable selection

impl W<u16, Reg<u16, _SAC2PGA>>

pub fn msel(&mut self) -> MSEL_W<'_>

Bits 0:1 - SAC PGA Mode Selection

pub fn gain(&mut self) -> GAIN_W<'_>

Bits 4:6 - SAC PGA Gain configuration

impl W<u16, Reg<u16, _SAC2DAC>>

pub fn dacen(&mut self) -> DACEN_W<'_>

Bit 0 - SAC DAC enable

pub fn dacie(&mut self) -> DACIE_W<'_>

Bit 1 - SAC DAC interrupt enable

pub fn dacdmae(&mut self) -> DACDMAE_W<'_>

Bit 2 - SAC DAC DMA request enable

pub fn daclsel(&mut self) -> DACLSEL_W<'_>

Bits 8:9 - SAC DAC load select. Selects the load trigger for the DAC latch.

pub fn dacsref(&mut self) -> DACSREF_W<'_>

Bit 12 - SAC DAC select reference voltage

impl W<u16, Reg<u16, _SAC2DAT>>

pub fn dacdata(&mut self) -> DACDATA_W<'_>

Bits 0:11 - SAC DAC data in unsigned format.

impl W<u16, Reg<u16, _SAC2DACSTS>>

pub fn dacifg(&mut self) -> DACIFG_W<'_>

Bit 0 - SAC DAC data update flag

impl W<u16, Reg<u16, _SAC3OA>>

pub fn psel(&mut self) -> PSEL_W<'_>

Bits 0:1 - SAC OA Positive input source selection

pub fn pmuxen(&mut self) -> PMUXEN_W<'_>

Bit 3 - SAC Positive input MUX control.

pub fn nsel(&mut self) -> NSEL_W<'_>

Bits 4:5 - SAC OA Negative input source selection

pub fn nmuxen(&mut self) -> NMUXEN_W<'_>

Bit 7 - SAC Negative input MUX controL

pub fn oaen(&mut self) -> OAEN_W<'_>

Bit 8 - SAC OA Enable selection

pub fn oapm(&mut self) -> OAPM_W<'_>

Bit 9 - SAC OA power mode selection

pub fn sacen(&mut self) -> SACEN_W<'_>

Bit 10 - SAC Enable selection

impl W<u16, Reg<u16, _SAC3PGA>>

pub fn msel(&mut self) -> MSEL_W<'_>

Bits 0:1 - SAC PGA Mode Selection

pub fn gain(&mut self) -> GAIN_W<'_>

Bits 4:6 - SAC PGA Gain configuration

impl W<u16, Reg<u16, _SAC3DAC>>

pub fn dacen(&mut self) -> DACEN_W<'_>

Bit 0 - SAC DAC enable

pub fn dacie(&mut self) -> DACIE_W<'_>

Bit 1 - SAC DAC interrupt enable

pub fn dacdmae(&mut self) -> DACDMAE_W<'_>

Bit 2 - SAC DAC DMA request enable

pub fn daclsel(&mut self) -> DACLSEL_W<'_>

Bits 8:9 - SAC DAC load select. Selects the load trigger for the DAC latch.

pub fn dacsref(&mut self) -> DACSREF_W<'_>

Bit 12 - SAC DAC select reference voltage

impl W<u16, Reg<u16, _SAC3DAT>>

pub fn dacdata(&mut self) -> DACDATA_W<'_>

Bits 0:11 - SAC DAC data in unsigned format.

impl W<u16, Reg<u16, _SAC3DACSTS>>

pub fn dacifg(&mut self) -> DACIFG_W<'_>

Bit 0 - SAC DAC data update flag