Struct msp430f5529::dma::dmactl0::DMA1TSEL_W
source · [−]pub struct DMA1TSEL_W<'a> { /* private fields */ }
Expand description
Field DMA1TSEL
writer - DMA channel 1 transfer select bit 0
Implementations
Writes variant
to the field
DMA channel 1 transfer select 0: DMA_REQ (sw)
DMA channel 1 transfer select 1: Timer0_A (TA0CCR0.IFG)
DMA channel 1 transfer select 2: Timer0_A (TA0CCR2.IFG)
DMA channel 1 transfer select 3: Timer1_A (TA1CCR0.IFG)
DMA channel 1 transfer select 4: Timer1_A (TA1CCR2.IFG)
DMA channel 1 transfer select 5: Timer2_A (TA2CCR0.IFG)
DMA channel 1 transfer select 6: Timer2_A (TA2CCR2.IFG)
DMA channel 1 transfer select 7: TimerB (TB0CCR0.IFG)
DMA channel 1 transfer select 8: TimerB (TB0CCR2.IFG)
DMA channel 1 transfer select 9: Reserved
DMA channel 1 transfer select 10: Reserved
DMA channel 1 transfer select 11: Reserved
DMA channel 1 transfer select 12: Reserved
DMA channel 1 transfer select 13: Reserved
DMA channel 1 transfer select 14: Reserved
DMA channel 1 transfer select 15: Reserved
DMA channel 1 transfer select 16: USCIA0 receive
DMA channel 1 transfer select 17: USCIA0 transmit
DMA channel 1 transfer select 18: USCIB0 receive
DMA channel 1 transfer select 19: USCIB0 transmit
DMA channel 1 transfer select 20: USCIA1 receive
DMA channel 1 transfer select 21: USCIA1 transmit
DMA channel 1 transfer select 22: USCIB1 receive
DMA channel 1 transfer select 23: USCIB1 transmit
DMA channel 1 transfer select 24: ADC12IFGx
DMA channel 1 transfer select 25: Reserved
DMA channel 1 transfer select 26: Reserved
DMA channel 1 transfer select 27: USB FNRXD
DMA channel 1 transfer select 28: USB ready
DMA channel 1 transfer select 29: Multiplier ready
DMA channel 1 transfer select 30: previous DMA channel DMA0IFG
DMA channel 1 transfer select 31: ext. Trigger (DMAE0)