Amd64Reg

Struct Amd64Reg 

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pub struct Amd64Reg(pub u16);

Tuple Fields§

§0: u16

Implementations§

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impl Amd64Reg

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pub const AL: Amd64Reg

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pub const CL: Amd64Reg

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pub const DL: Amd64Reg

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pub const BL: Amd64Reg

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pub const AH: Amd64Reg

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pub const CH: Amd64Reg

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pub const DH: Amd64Reg

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pub const BH: Amd64Reg

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pub const AX: Amd64Reg

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pub const CX: Amd64Reg

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pub const DX: Amd64Reg

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pub const BX: Amd64Reg

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pub const SP: Amd64Reg

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pub const BP: Amd64Reg

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pub const SI: Amd64Reg

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pub const DI: Amd64Reg

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pub const EAX: Amd64Reg

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pub const ECX: Amd64Reg

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pub const EDX: Amd64Reg

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pub const EBX: Amd64Reg

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pub const ESP: Amd64Reg

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pub const EBP: Amd64Reg

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pub const ESI: Amd64Reg

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pub const EDI: Amd64Reg

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pub const ES: Amd64Reg

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pub const CS: Amd64Reg

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pub const SS: Amd64Reg

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pub const DS: Amd64Reg

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pub const FS: Amd64Reg

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pub const GS: Amd64Reg

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pub const FLAGS: Amd64Reg

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pub const RIP: Amd64Reg

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pub const EFLAGS: Amd64Reg

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pub const CR0: Amd64Reg

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pub const CR1: Amd64Reg

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pub const CR2: Amd64Reg

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pub const CR3: Amd64Reg

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pub const CR4: Amd64Reg

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pub const CR8: Amd64Reg

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pub const DR0: Amd64Reg

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pub const DR1: Amd64Reg

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pub const DR2: Amd64Reg

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pub const DR3: Amd64Reg

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pub const DR4: Amd64Reg

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pub const DR5: Amd64Reg

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pub const DR6: Amd64Reg

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pub const DR7: Amd64Reg

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pub const DR8: Amd64Reg

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pub const DR9: Amd64Reg

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pub const DR10: Amd64Reg

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pub const DR11: Amd64Reg

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pub const DR12: Amd64Reg

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pub const DR13: Amd64Reg

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pub const DR14: Amd64Reg

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pub const DR15: Amd64Reg

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pub const GDTR: Amd64Reg

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pub const GDTL: Amd64Reg

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pub const IDTR: Amd64Reg

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pub const IDTL: Amd64Reg

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pub const LDTR: Amd64Reg

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pub const TR: Amd64Reg

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pub const ST0: Amd64Reg

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pub const ST1: Amd64Reg

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pub const ST2: Amd64Reg

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pub const ST3: Amd64Reg

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pub const ST4: Amd64Reg

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pub const ST5: Amd64Reg

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pub const ST6: Amd64Reg

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pub const ST7: Amd64Reg

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pub const CTRL: Amd64Reg

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pub const STAT: Amd64Reg

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pub const TAG: Amd64Reg

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pub const FPIP: Amd64Reg

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pub const FPCS: Amd64Reg

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pub const FPDO: Amd64Reg

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pub const FPDS: Amd64Reg

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pub const ISEM: Amd64Reg

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pub const FPEIP: Amd64Reg

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pub const FPEDO: Amd64Reg

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pub const MM0: Amd64Reg

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pub const MM1: Amd64Reg

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pub const MM2: Amd64Reg

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pub const MM3: Amd64Reg

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pub const MM4: Amd64Reg

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pub const MM5: Amd64Reg

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pub const MM6: Amd64Reg

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pub const MM7: Amd64Reg

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pub const XMM0: Amd64Reg

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pub const XMM1: Amd64Reg

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pub const XMM2: Amd64Reg

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pub const XMM3: Amd64Reg

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pub const XMM4: Amd64Reg

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pub const XMM5: Amd64Reg

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pub const XMM6: Amd64Reg

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pub const XMM7: Amd64Reg

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pub const XMM0_0: Amd64Reg

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pub const XMM0_1: Amd64Reg

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pub const XMM0_2: Amd64Reg

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pub const XMM0_3: Amd64Reg

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pub const XMM1_0: Amd64Reg

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pub const XMM1_1: Amd64Reg

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pub const XMM1_2: Amd64Reg

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pub const XMM1_3: Amd64Reg

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pub const XMM2_0: Amd64Reg

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pub const XMM2_1: Amd64Reg

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pub const XMM2_2: Amd64Reg

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pub const XMM2_3: Amd64Reg

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pub const XMM3_0: Amd64Reg

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pub const XMM3_1: Amd64Reg

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pub const XMM3_2: Amd64Reg

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pub const XMM3_3: Amd64Reg

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pub const XMM4_0: Amd64Reg

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pub const XMM4_1: Amd64Reg

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pub const XMM4_2: Amd64Reg

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pub const XMM4_3: Amd64Reg

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pub const XMM5_0: Amd64Reg

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pub const XMM5_1: Amd64Reg

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pub const XMM5_2: Amd64Reg

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pub const XMM5_3: Amd64Reg

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pub const XMM6_0: Amd64Reg

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pub const XMM6_1: Amd64Reg

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pub const XMM6_2: Amd64Reg

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pub const XMM6_3: Amd64Reg

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pub const XMM7_0: Amd64Reg

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pub const XMM7_1: Amd64Reg

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pub const XMM7_2: Amd64Reg

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pub const XMM7_3: Amd64Reg

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pub const XMM0L: Amd64Reg

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pub const XMM1L: Amd64Reg

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pub const XMM2L: Amd64Reg

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pub const XMM3L: Amd64Reg

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pub const XMM4L: Amd64Reg

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pub const XMM5L: Amd64Reg

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pub const XMM6L: Amd64Reg

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pub const XMM7L: Amd64Reg

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pub const XMM0H: Amd64Reg

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pub const XMM1H: Amd64Reg

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pub const XMM2H: Amd64Reg

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pub const XMM3H: Amd64Reg

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pub const XMM4H: Amd64Reg

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pub const XMM5H: Amd64Reg

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pub const XMM6H: Amd64Reg

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pub const XMM7H: Amd64Reg

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pub const MXCSR: Amd64Reg

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pub const EMM0L: Amd64Reg

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pub const EMM1L: Amd64Reg

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pub const EMM2L: Amd64Reg

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pub const EMM3L: Amd64Reg

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pub const EMM4L: Amd64Reg

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pub const EMM5L: Amd64Reg

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pub const EMM6L: Amd64Reg

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pub const EMM7L: Amd64Reg

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pub const EMM0H: Amd64Reg

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pub const EMM1H: Amd64Reg

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pub const EMM2H: Amd64Reg

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pub const EMM3H: Amd64Reg

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pub const EMM4H: Amd64Reg

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pub const EMM5H: Amd64Reg

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pub const EMM6H: Amd64Reg

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pub const EMM7H: Amd64Reg

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pub const MM00: Amd64Reg

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pub const MM01: Amd64Reg

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pub const MM10: Amd64Reg

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pub const MM11: Amd64Reg

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pub const MM20: Amd64Reg

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pub const MM21: Amd64Reg

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pub const MM30: Amd64Reg

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pub const MM31: Amd64Reg

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pub const MM40: Amd64Reg

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pub const MM41: Amd64Reg

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pub const MM50: Amd64Reg

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pub const MM51: Amd64Reg

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pub const MM60: Amd64Reg

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pub const MM61: Amd64Reg

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pub const MM70: Amd64Reg

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pub const MM71: Amd64Reg

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pub const XMM8: Amd64Reg

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pub const XMM9: Amd64Reg

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pub const XMM10: Amd64Reg

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pub const XMM11: Amd64Reg

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pub const XMM12: Amd64Reg

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pub const XMM13: Amd64Reg

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pub const XMM14: Amd64Reg

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pub const XMM15: Amd64Reg

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pub const XMM8_0: Amd64Reg

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pub const XMM8_1: Amd64Reg

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pub const XMM8_2: Amd64Reg

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pub const XMM8_3: Amd64Reg

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pub const XMM9_0: Amd64Reg

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pub const XMM9_1: Amd64Reg

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pub const XMM9_2: Amd64Reg

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pub const XMM9_3: Amd64Reg

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pub const XMM10_0: Amd64Reg

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pub const XMM10_1: Amd64Reg

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pub const XMM10_2: Amd64Reg

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pub const XMM10_3: Amd64Reg

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pub const XMM11_0: Amd64Reg

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pub const XMM11_1: Amd64Reg

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pub const XMM11_2: Amd64Reg

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pub const XMM11_3: Amd64Reg

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pub const XMM12_0: Amd64Reg

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pub const XMM12_1: Amd64Reg

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pub const XMM12_2: Amd64Reg

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pub const XMM12_3: Amd64Reg

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pub const XMM13_0: Amd64Reg

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pub const XMM13_1: Amd64Reg

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pub const XMM13_2: Amd64Reg

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pub const XMM13_3: Amd64Reg

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pub const XMM14_0: Amd64Reg

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pub const XMM14_1: Amd64Reg

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pub const XMM14_2: Amd64Reg

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pub const XMM14_3: Amd64Reg

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pub const XMM15_0: Amd64Reg

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pub const XMM15_1: Amd64Reg

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pub const XMM15_2: Amd64Reg

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pub const XMM15_3: Amd64Reg

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pub const XMM8L: Amd64Reg

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pub const XMM9L: Amd64Reg

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pub const XMM10L: Amd64Reg

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pub const XMM11L: Amd64Reg

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pub const XMM12L: Amd64Reg

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pub const XMM13L: Amd64Reg

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pub const XMM14L: Amd64Reg

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pub const XMM15L: Amd64Reg

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pub const XMM8H: Amd64Reg

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pub const XMM9H: Amd64Reg

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pub const XMM10H: Amd64Reg

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pub const XMM11H: Amd64Reg

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pub const XMM12H: Amd64Reg

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pub const XMM13H: Amd64Reg

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pub const XMM14H: Amd64Reg

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pub const XMM15H: Amd64Reg

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pub const EMM8L: Amd64Reg

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pub const EMM9L: Amd64Reg

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pub const EMM10L: Amd64Reg

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pub const EMM11L: Amd64Reg

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pub const EMM12L: Amd64Reg

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pub const EMM13L: Amd64Reg

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pub const EMM14L: Amd64Reg

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pub const EMM15L: Amd64Reg

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pub const EMM8H: Amd64Reg

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pub const EMM9H: Amd64Reg

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pub const EMM10H: Amd64Reg

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pub const EMM11H: Amd64Reg

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pub const EMM12H: Amd64Reg

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pub const EMM13H: Amd64Reg

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pub const EMM14H: Amd64Reg

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pub const EMM15H: Amd64Reg

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pub const SIL: Amd64Reg

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pub const DIL: Amd64Reg

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pub const BPL: Amd64Reg

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pub const SPL: Amd64Reg

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pub const RAX: Amd64Reg

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pub const RBX: Amd64Reg

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pub const RCX: Amd64Reg

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pub const RDX: Amd64Reg

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pub const RSI: Amd64Reg

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pub const RDI: Amd64Reg

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pub const RBP: Amd64Reg

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pub const RSP: Amd64Reg

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pub const R8: Amd64Reg

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pub const R9: Amd64Reg

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pub const R10: Amd64Reg

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pub const R11: Amd64Reg

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pub const R12: Amd64Reg

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pub const R13: Amd64Reg

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pub const R14: Amd64Reg

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pub const R15: Amd64Reg

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pub const R8B: Amd64Reg

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pub const R9B: Amd64Reg

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pub const R10B: Amd64Reg

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pub const R11B: Amd64Reg

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pub const R12B: Amd64Reg

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pub const R13B: Amd64Reg

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pub const R14B: Amd64Reg

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pub const R15B: Amd64Reg

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pub const R8W: Amd64Reg

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pub const R9W: Amd64Reg

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pub const R10W: Amd64Reg

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pub const R11W: Amd64Reg

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pub const R12W: Amd64Reg

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pub const R13W: Amd64Reg

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pub const R14W: Amd64Reg

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pub const R15W: Amd64Reg

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pub const R8D: Amd64Reg

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pub const R9D: Amd64Reg

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pub const R10D: Amd64Reg

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pub const R11D: Amd64Reg

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pub const R12D: Amd64Reg

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pub const R13D: Amd64Reg

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pub const R14D: Amd64Reg

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pub const R15D: Amd64Reg

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pub const YMM0: Amd64Reg

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pub const YMM1: Amd64Reg

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pub const YMM2: Amd64Reg

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pub const YMM3: Amd64Reg

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pub const YMM4: Amd64Reg

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pub const YMM5: Amd64Reg

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pub const YMM6: Amd64Reg

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pub const YMM7: Amd64Reg

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pub const YMM8: Amd64Reg

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pub const YMM9: Amd64Reg

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pub const YMM10: Amd64Reg

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pub const YMM11: Amd64Reg

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pub const YMM12: Amd64Reg

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pub const YMM13: Amd64Reg

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pub const YMM14: Amd64Reg

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pub const YMM15: Amd64Reg

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pub const YMM0H: Amd64Reg

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pub const YMM1H: Amd64Reg

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pub const YMM2H: Amd64Reg

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pub const YMM3H: Amd64Reg

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pub const YMM4H: Amd64Reg

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pub const YMM5H: Amd64Reg

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pub const YMM6H: Amd64Reg

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pub const YMM7H: Amd64Reg

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pub const YMM8H: Amd64Reg

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pub const YMM9H: Amd64Reg

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pub const YMM10H: Amd64Reg

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pub const YMM11H: Amd64Reg

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pub const YMM12H: Amd64Reg

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pub const YMM13H: Amd64Reg

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pub const YMM14H: Amd64Reg

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pub const YMM15H: Amd64Reg

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pub const XMM0IL: Amd64Reg

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pub const XMM1IL: Amd64Reg

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pub const XMM2IL: Amd64Reg

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pub const XMM3IL: Amd64Reg

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pub const XMM4IL: Amd64Reg

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pub const XMM5IL: Amd64Reg

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pub const XMM6IL: Amd64Reg

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pub const XMM7IL: Amd64Reg

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pub const XMM8IL: Amd64Reg

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pub const XMM9IL: Amd64Reg

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pub const XMM10IL: Amd64Reg

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pub const XMM11IL: Amd64Reg

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pub const XMM12IL: Amd64Reg

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pub const XMM13IL: Amd64Reg

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pub const XMM14IL: Amd64Reg

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pub const XMM15IL: Amd64Reg

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pub const XMM0IH: Amd64Reg

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pub const XMM1IH: Amd64Reg

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pub const XMM2IH: Amd64Reg

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pub const XMM3IH: Amd64Reg

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pub const XMM4IH: Amd64Reg

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pub const XMM5IH: Amd64Reg

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pub const XMM6IH: Amd64Reg

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pub const XMM7IH: Amd64Reg

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pub const XMM8IH: Amd64Reg

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pub const XMM9IH: Amd64Reg

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pub const XMM10IH: Amd64Reg

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pub const XMM11IH: Amd64Reg

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pub const XMM12IH: Amd64Reg

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pub const XMM13IH: Amd64Reg

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pub const XMM14IH: Amd64Reg

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pub const XMM15IH: Amd64Reg

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pub const YMM0I0: Amd64Reg

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pub const YMM0I1: Amd64Reg

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pub const YMM0I2: Amd64Reg

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pub const YMM0I3: Amd64Reg

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pub const YMM1I0: Amd64Reg

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pub const YMM1I1: Amd64Reg

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pub const YMM1I2: Amd64Reg

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pub const YMM1I3: Amd64Reg

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pub const YMM2I0: Amd64Reg

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pub const YMM2I1: Amd64Reg

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pub const YMM2I2: Amd64Reg

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pub const YMM2I3: Amd64Reg

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pub const YMM3I0: Amd64Reg

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pub const YMM3I1: Amd64Reg

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pub const YMM3I2: Amd64Reg

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pub const YMM3I3: Amd64Reg

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pub const YMM4I0: Amd64Reg

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pub const YMM4I1: Amd64Reg

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pub const YMM4I2: Amd64Reg

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pub const YMM4I3: Amd64Reg

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pub const YMM5I0: Amd64Reg

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pub const YMM5I1: Amd64Reg

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pub const YMM5I2: Amd64Reg

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pub const YMM5I3: Amd64Reg

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pub const YMM6I0: Amd64Reg

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pub const YMM6I1: Amd64Reg

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pub const YMM6I2: Amd64Reg

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pub const YMM6I3: Amd64Reg

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pub const YMM7I0: Amd64Reg

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pub const YMM7I1: Amd64Reg

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pub const YMM7I2: Amd64Reg

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pub const YMM7I3: Amd64Reg

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pub const YMM8I0: Amd64Reg

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pub const YMM8I1: Amd64Reg

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pub const YMM8I2: Amd64Reg

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pub const YMM8I3: Amd64Reg

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pub const YMM9I0: Amd64Reg

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pub const YMM9I1: Amd64Reg

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pub const YMM9I2: Amd64Reg

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pub const YMM9I3: Amd64Reg

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pub const YMM10I0: Amd64Reg

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pub const YMM10I1: Amd64Reg

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pub const YMM10I2: Amd64Reg

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pub const YMM10I3: Amd64Reg

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pub const YMM11I0: Amd64Reg

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pub const YMM11I1: Amd64Reg

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pub const YMM11I2: Amd64Reg

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pub const YMM11I3: Amd64Reg

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pub const YMM12I0: Amd64Reg

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pub const YMM12I1: Amd64Reg

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pub const YMM12I2: Amd64Reg

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pub const YMM12I3: Amd64Reg

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pub const YMM13I0: Amd64Reg

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pub const YMM13I1: Amd64Reg

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pub const YMM13I2: Amd64Reg

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pub const YMM13I3: Amd64Reg

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pub const YMM14I0: Amd64Reg

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pub const YMM14I1: Amd64Reg

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pub const YMM14I2: Amd64Reg

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pub const YMM14I3: Amd64Reg

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pub const YMM15I0: Amd64Reg

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pub const YMM15I1: Amd64Reg

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pub const YMM15I2: Amd64Reg

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pub const YMM15I3: Amd64Reg

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pub const YMM0F0: Amd64Reg

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pub const YMM0F1: Amd64Reg

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pub const YMM0F2: Amd64Reg

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pub const YMM0F3: Amd64Reg

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pub const YMM0F4: Amd64Reg

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pub const YMM0F5: Amd64Reg

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pub const YMM0F6: Amd64Reg

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pub const YMM0F7: Amd64Reg

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pub const YMM1F0: Amd64Reg

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pub const YMM1F1: Amd64Reg

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pub const YMM1F2: Amd64Reg

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pub const YMM1F3: Amd64Reg

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pub const YMM1F4: Amd64Reg

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pub const YMM1F5: Amd64Reg

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pub const YMM1F6: Amd64Reg

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pub const YMM1F7: Amd64Reg

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pub const YMM2F0: Amd64Reg

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pub const YMM2F1: Amd64Reg

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pub const YMM2F2: Amd64Reg

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pub const YMM2F3: Amd64Reg

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pub const YMM2F4: Amd64Reg

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pub const YMM2F5: Amd64Reg

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pub const YMM2F6: Amd64Reg

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pub const YMM2F7: Amd64Reg

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pub const YMM3F0: Amd64Reg

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pub const YMM3F1: Amd64Reg

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pub const YMM3F2: Amd64Reg

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pub const YMM3F3: Amd64Reg

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pub const YMM3F4: Amd64Reg

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pub const YMM3F5: Amd64Reg

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pub const YMM3F6: Amd64Reg

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pub const YMM3F7: Amd64Reg

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pub const YMM4F0: Amd64Reg

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pub const YMM4F1: Amd64Reg

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pub const YMM4F2: Amd64Reg

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pub const YMM4F3: Amd64Reg

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pub const YMM4F4: Amd64Reg

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pub const YMM4F5: Amd64Reg

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pub const YMM4F6: Amd64Reg

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pub const YMM4F7: Amd64Reg

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pub const YMM5F0: Amd64Reg

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pub const YMM5F1: Amd64Reg

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pub const YMM5F2: Amd64Reg

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pub const YMM5F3: Amd64Reg

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pub const YMM5F4: Amd64Reg

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pub const YMM5F5: Amd64Reg

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pub const YMM5F6: Amd64Reg

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pub const YMM5F7: Amd64Reg

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pub const YMM6F0: Amd64Reg

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pub const YMM6F1: Amd64Reg

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pub const YMM6F2: Amd64Reg

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pub const YMM6F3: Amd64Reg

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pub const YMM6F4: Amd64Reg

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pub const YMM6F5: Amd64Reg

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pub const YMM6F6: Amd64Reg

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pub const YMM6F7: Amd64Reg

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pub const YMM7F0: Amd64Reg

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pub const YMM7F1: Amd64Reg

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pub const YMM7F2: Amd64Reg

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pub const YMM7F3: Amd64Reg

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pub const YMM7F4: Amd64Reg

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pub const YMM7F5: Amd64Reg

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pub const YMM7F6: Amd64Reg

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pub const YMM7F7: Amd64Reg

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pub const YMM8F0: Amd64Reg

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pub const YMM8F1: Amd64Reg

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pub const YMM8F2: Amd64Reg

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pub const YMM8F3: Amd64Reg

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pub const YMM8F4: Amd64Reg

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pub const YMM8F5: Amd64Reg

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pub const YMM8F6: Amd64Reg

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pub const YMM8F7: Amd64Reg

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pub const YMM9F0: Amd64Reg

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pub const YMM9F1: Amd64Reg

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pub const YMM9F2: Amd64Reg

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pub const YMM9F3: Amd64Reg

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pub const YMM9F4: Amd64Reg

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pub const YMM9F5: Amd64Reg

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pub const YMM9F6: Amd64Reg

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pub const YMM9F7: Amd64Reg

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pub const YMM10F0: Amd64Reg

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pub const YMM10F1: Amd64Reg

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pub const YMM10F2: Amd64Reg

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pub const YMM10F3: Amd64Reg

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pub const YMM10F4: Amd64Reg

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pub const YMM10F5: Amd64Reg

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pub const YMM10F6: Amd64Reg

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pub const YMM10F7: Amd64Reg

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pub const YMM11F0: Amd64Reg

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pub const YMM11F1: Amd64Reg

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pub const YMM11F2: Amd64Reg

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pub const YMM11F3: Amd64Reg

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pub const YMM11F4: Amd64Reg

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pub const YMM11F5: Amd64Reg

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pub const YMM11F6: Amd64Reg

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pub const YMM11F7: Amd64Reg

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pub const YMM12F0: Amd64Reg

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pub const YMM12F1: Amd64Reg

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pub const YMM12F2: Amd64Reg

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pub const YMM12F3: Amd64Reg

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pub const YMM12F4: Amd64Reg

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pub const YMM12F5: Amd64Reg

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pub const YMM12F6: Amd64Reg

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pub const YMM12F7: Amd64Reg

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pub const YMM13F0: Amd64Reg

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pub const YMM13F1: Amd64Reg

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pub const YMM13F2: Amd64Reg

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pub const YMM13F3: Amd64Reg

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pub const YMM13F4: Amd64Reg

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pub const YMM13F5: Amd64Reg

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pub const YMM13F6: Amd64Reg

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pub const YMM13F7: Amd64Reg

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pub const YMM14F0: Amd64Reg

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pub const YMM14F1: Amd64Reg

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pub const YMM14F2: Amd64Reg

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pub const YMM14F3: Amd64Reg

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pub const YMM14F4: Amd64Reg

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pub const YMM14F5: Amd64Reg

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pub const YMM14F6: Amd64Reg

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pub const YMM14F7: Amd64Reg

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pub const YMM15F0: Amd64Reg

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pub const YMM15F1: Amd64Reg

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pub const YMM15F2: Amd64Reg

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pub const YMM15F3: Amd64Reg

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pub const YMM15F4: Amd64Reg

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pub const YMM15F5: Amd64Reg

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pub const YMM15F6: Amd64Reg

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pub const YMM15F7: Amd64Reg

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pub const YMM0D0: Amd64Reg

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pub const YMM0D1: Amd64Reg

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pub const YMM0D2: Amd64Reg

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pub const YMM0D3: Amd64Reg

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pub const YMM1D0: Amd64Reg

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pub const YMM1D1: Amd64Reg

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pub const YMM1D2: Amd64Reg

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pub const YMM1D3: Amd64Reg

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pub const YMM2D0: Amd64Reg

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pub const YMM2D1: Amd64Reg

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pub const YMM2D2: Amd64Reg

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pub const YMM2D3: Amd64Reg

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pub const YMM3D0: Amd64Reg

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pub const YMM3D1: Amd64Reg

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pub const YMM3D2: Amd64Reg

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pub const YMM3D3: Amd64Reg

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pub const YMM4D0: Amd64Reg

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pub const YMM4D1: Amd64Reg

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pub const YMM4D2: Amd64Reg

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pub const YMM4D3: Amd64Reg

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pub const YMM5D0: Amd64Reg

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pub const YMM5D1: Amd64Reg

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pub const YMM5D2: Amd64Reg

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pub const YMM5D3: Amd64Reg

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pub const YMM6D0: Amd64Reg

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pub const YMM6D1: Amd64Reg

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pub const YMM6D2: Amd64Reg

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pub const YMM6D3: Amd64Reg

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pub const YMM7D0: Amd64Reg

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pub const YMM7D1: Amd64Reg

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pub const YMM7D2: Amd64Reg

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pub const YMM7D3: Amd64Reg

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pub const YMM8D0: Amd64Reg

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pub const YMM8D1: Amd64Reg

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pub const YMM8D2: Amd64Reg

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pub const YMM8D3: Amd64Reg

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pub const YMM9D0: Amd64Reg

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pub const YMM9D1: Amd64Reg

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pub const YMM9D2: Amd64Reg

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pub const YMM9D3: Amd64Reg

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pub const YMM10D0: Amd64Reg

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pub const YMM10D1: Amd64Reg

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pub const YMM10D2: Amd64Reg

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pub const YMM10D3: Amd64Reg

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pub const YMM11D0: Amd64Reg

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pub const YMM11D1: Amd64Reg

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pub const YMM11D2: Amd64Reg

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pub const YMM11D3: Amd64Reg

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pub const YMM12D0: Amd64Reg

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pub const YMM12D1: Amd64Reg

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pub const YMM12D2: Amd64Reg

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pub const YMM12D3: Amd64Reg

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pub const YMM13D0: Amd64Reg

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pub const YMM13D1: Amd64Reg

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pub const YMM13D2: Amd64Reg

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pub const YMM13D3: Amd64Reg

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pub const YMM14D0: Amd64Reg

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pub const YMM14D1: Amd64Reg

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pub const YMM14D2: Amd64Reg

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pub const YMM14D3: Amd64Reg

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pub const YMM15D0: Amd64Reg

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pub const YMM15D1: Amd64Reg

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pub const YMM15D2: Amd64Reg

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pub const YMM15D3: Amd64Reg

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pub fn get_name(self) -> Option<&'static str>

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pub fn from_name(name: &str) -> Option<Self>

Trait Implementations§

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impl Clone for Amd64Reg

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fn clone(&self) -> Amd64Reg

Returns a duplicate of the value. Read more
1.0.0 · Source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
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impl Debug for Amd64Reg

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fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
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impl Display for Amd64Reg

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fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
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impl Hash for Amd64Reg

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fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher. Read more
1.3.0 · Source§

fn hash_slice<H>(data: &[Self], state: &mut H)
where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher. Read more
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impl Ord for Amd64Reg

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fn cmp(&self, other: &Amd64Reg) -> Ordering

This method returns an Ordering between self and other. Read more
1.21.0 · Source§

fn max(self, other: Self) -> Self
where Self: Sized,

Compares and returns the maximum of two values. Read more
1.21.0 · Source§

fn min(self, other: Self) -> Self
where Self: Sized,

Compares and returns the minimum of two values. Read more
1.50.0 · Source§

fn clamp(self, min: Self, max: Self) -> Self
where Self: Sized,

Restrict a value to a certain interval. Read more
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impl PartialEq for Amd64Reg

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fn eq(&self, other: &Amd64Reg) -> bool

Tests for self and other values to be equal, and is used by ==.
1.0.0 · Source§

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.
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impl PartialOrd for Amd64Reg

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fn partial_cmp(&self, other: &Amd64Reg) -> Option<Ordering>

This method returns an ordering between self and other values if one exists. Read more
1.0.0 · Source§

fn lt(&self, other: &Rhs) -> bool

Tests less than (for self and other) and is used by the < operator. Read more
1.0.0 · Source§

fn le(&self, other: &Rhs) -> bool

Tests less than or equal to (for self and other) and is used by the <= operator. Read more
1.0.0 · Source§

fn gt(&self, other: &Rhs) -> bool

Tests greater than (for self and other) and is used by the > operator. Read more
1.0.0 · Source§

fn ge(&self, other: &Rhs) -> bool

Tests greater than or equal to (for self and other) and is used by the >= operator. Read more
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impl Copy for Amd64Reg

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impl Eq for Amd64Reg

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impl StructuralPartialEq for Amd64Reg

Auto Trait Implementations§

Blanket Implementations§

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> CloneToUninit for T
where T: Clone,

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unsafe fn clone_to_uninit(&self, dest: *mut u8)

🔬This is a nightly-only experimental API. (clone_to_uninit)
Performs copy-assignment from self to dest. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T> Instrument for T

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fn instrument(self, span: Span) -> Instrumented<Self>

Instruments this type with the provided Span, returning an Instrumented wrapper. Read more
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fn in_current_span(self) -> Instrumented<Self>

Instruments this type with the current Span, returning an Instrumented wrapper. Read more
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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T> ToOwned for T
where T: Clone,

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type Owned = T

The resulting type after obtaining ownership.
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fn to_owned(&self) -> T

Creates owned data from borrowed data, usually by cloning. Read more
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fn clone_into(&self, target: &mut T)

Uses borrowed data to replace owned data, usually by cloning. Read more
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impl<T> ToString for T
where T: Display + ?Sized,

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fn to_string(&self) -> String

Converts the given value to a String. Read more
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impl<T, U> TryFrom<U> for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.
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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.
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impl<T> WithSubscriber for T

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fn with_subscriber<S>(self, subscriber: S) -> WithDispatch<Self>
where S: Into<Dispatch>,

Attaches the provided Subscriber to this type, returning a WithDispatch wrapper. Read more
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fn with_current_subscriber(self) -> WithDispatch<Self>

Attaches the current default Subscriber to this type, returning a WithDispatch wrapper. Read more