#[repr(C)]pub struct PCIE_END_CONF_TypeDef {Show 45 fields
pub VID_DEVID: u32,
pub CFG_PRMSCR: u32,
pub CLASS_CODE: u32,
pub BIST_HEADER: u32,
pub BAR0: u32,
pub BAR1: u32,
pub BAR2: u32,
pub BAR3: u32,
pub BAR4: u32,
pub BAR5: u32,
pub RESERVED1: u32,
pub SUBSYSTEM_ID: u32,
pub EXPAN_ROM: u32,
pub CAPAB_POINTER: u32,
pub EXPAN_ROM_BASE: u32,
pub INT_LINE_PIN: u32,
pub RESERVED2: [u32; 16],
pub CAPAB_LIST: u32,
pub DEVICE_CAPAB: u32,
pub DEVICE_CTRL_STAT: u32,
pub LINK_CAPAB: u32,
pub LINK_CTRL_STAT: u32,
pub SLOT_CAPAB: u32,
pub SLOT_CTRL_STAT: u32,
pub ROOT_CTRL: u32,
pub ROOT_STAT: u32,
pub DEVICE2_CAPAB: u32,
pub DEVICE2_CTRL_STAT: u32,
pub LINK2_CAPAB: u32,
pub LINK2_CTRL_STAT: u32,
pub SLOT2_CAPAB: u32,
pub SLOT2_CTRL_STAT: u32,
pub RESERVED3: [u32; 5],
pub MSI_X_CAPAB_CTRL: u32,
pub MSI_X_TABLE: u32,
pub MSI_X_PBA: u32,
pub RESERVED4: u32,
pub MSI_CAPAB_CTRL: u32,
pub MSI_LOWER_ADDRESS: u32,
pub MSI_UPPER_ADDRESS: u32,
pub RESERVED5: u32,
pub MSI_DATA: u32,
pub RESERVED6: u32,
pub POWER_MNGM_CAPAB: u32,
pub POWER_CTRL_STAT: u32,
}Fields§
§VID_DEVID: u32Information register: vendor_id & device_id bits [15:0] vendor_id bits [31:16] device_id
CFG_PRMSCR: u32PCI Express Control & Status Register: cfg_prmscr
CLASS_CODE: u32Information register: class_code
BIST_HEADER: u32BIST, Header, master latency timer, cache : BIST_HEADER
BAR0: u32Bridge Configuration Register: bar0
BAR1: u32Bridge Configuration Register: bar1
BAR2: u32Bridge Configuration Register: bar2
BAR3: u32Bridge Configuration Register: bar3
BAR4: u32Bridge Configuration Register: bar4
BAR5: u32Bridge Configuration Register: bar5
RESERVED1: u32§SUBSYSTEM_ID: u32Information register: subsystem_id
EXPAN_ROM: u32Expansion ROM Base Address Register: expansion_rom
CAPAB_POINTER: u32Capability pointer register: capab_pointer
EXPAN_ROM_BASE: u32Expansion ROM Base Address register: expansion_rom_base
INT_LINE_PIN: u32Interrupt Line and Pin register: int_line_pin
RESERVED2: [u32; 16]§CAPAB_LIST: u32PCIe Capability list register: CAPAB_LIST
DEVICE_CAPAB: u32Device Capabilities register: device_capab
DEVICE_CTRL_STAT: u32Device Control and status register: device_ctrl_stat
LINK_CAPAB: u32Link Capabilities register: link_capab
LINK_CTRL_STAT: u32Link Control and status register: link_ctrl_stat
SLOT_CAPAB: u32Slot capabilities register: slot_capab
SLOT_CTRL_STAT: u32Slot Control and status register: slot_ctrl_stat
ROOT_CTRL: u32Root control register: root_ctrl
ROOT_STAT: u32Root status register: root_stat
DEVICE2_CAPAB: u32Device 2 Capabilities register: device2_capab
DEVICE2_CTRL_STAT: u32Device 2 Control and status register: device2_ctrl_stat
LINK2_CAPAB: u32Link Capabilities 2 register: link2_capab
LINK2_CTRL_STAT: u32Link Control and status 2register: link2_ctrl_stat
SLOT2_CAPAB: u32Slot 2 capabilities register: slot2_capab
SLOT2_CTRL_STAT: u32Slot 2 Control and status register: slot2_ctrl_stat
RESERVED3: [u32; 5]§MSI_X_CAPAB_CTRL: u32MSI-X capability and control register: msi_x_capab_ctrl
MSI_X_TABLE: u32MSI-X table register: msi_x_table
MSI_X_PBA: u32MSI-X PBA register: msi_x_pba
RESERVED4: u32§MSI_CAPAB_CTRL: u32MSI capability id and message control register: msi_capab_ctrl
MSI_LOWER_ADDRESS: u32MSI message lower address register: msi_lower address
MSI_UPPER_ADDRESS: u32MSI message upper address register: msi_upper address
RESERVED5: u32§MSI_DATA: u32MSI message data register: msi_data
RESERVED6: u32§POWER_MNGM_CAPAB: u32Power Management Capability register: power_mngm_capab
POWER_CTRL_STAT: u32Power Management control and status register: power_ctrl_stat
Trait Implementations§
Source§impl Clone for PCIE_END_CONF_TypeDef
impl Clone for PCIE_END_CONF_TypeDef
Source§fn clone(&self) -> PCIE_END_CONF_TypeDef
fn clone(&self) -> PCIE_END_CONF_TypeDef
1.0.0 · Source§fn clone_from(&mut self, source: &Self)
fn clone_from(&mut self, source: &Self)
source. Read more