PCIE_CTRL_TypeDef

mpfs_pac

Struct PCIE_CTRL_TypeDef 

Source 
#[repr(C)]
pub struct PCIE_CTRL_TypeDef {
Show 52 fields
    pub SOFT_RESET: u32,
    pub DEV_CONTROL: u32,
    pub CLOCK_CONTROL: u32,
    pub RESERVED0: u32,
    pub SOFT_RESET_DEBUG_INFO: u32,
    pub SOFT_RESET_CTLR: u32,
    pub RESERVED1: [u32; 2],
    pub SEC_ERROR_EVENT_CNT: u32,
    pub DED_ERROR_EVENT_CNT: u32,
    pub SEC_ERROR_INT: u32,
    pub SEC_ERROR_INT_MASK: u32,
    pub DED_ERROR_INT: u32,
    pub DED_ERROR_INT_MASK: u32,
    pub ECC_CONTROL: u32,
    pub ECC_ERR_LOC: u32,
    pub RAM_MARGIN_1: u32,
    pub RAM_MARGIN_2: u32,
    pub RAM_POWER_CONTROL: u32,
    pub RESERVED2: u32,
    pub DEBUG_SEL: u32,
    pub RESERVED3: [u32; 2],
    pub LTSSM_STATE: u32,
    pub PHY_COMMON_INTERFACE: u32,
    pub PL_TX_LANEIF_0: u32,
    pub PL_RX_LANEIF_0: u32,
    pub PL_WAKECLKREQ: u32,
    pub RESERVED4: [u32; 4],
    pub PCICONF_PCI_IDS_OVERRIDE: u32,
    pub PCICONF_PCI_IDS_31_0: u32,
    pub PCICONF_PCI_IDS_63_32: u32,
    pub PCICONF_PCI_IDS_95_64: u32,
    pub RESERVED5: [u32; 4],
    pub PCIE_PEX_DEV_LINK_SPC2: u32,
    pub PCIE_PEX_SPC: u32,
    pub RESERVED6: [u32; 22],
    pub PCIE_AXI_MASTER_ATR_CFG0: u32,
    pub PCIE_AXI_MASTER_ATR_CFG1: u32,
    pub PCIE_AXI_MASTER_ATR_CFG2: u32,
    pub RESERVED7: [u32; 5],
    pub AXI_SLAVE_PCIE_ATR_CFG0: u32,
    pub AXI_SLAVE_PCIE_ATR_CFG1: u32,
    pub AXI_SLAVE_PCIE_ATR_CFG2: u32,
    pub RESERVED8: [u32; 5],
    pub PCIE_BAR_01: u32,
    pub PCIE_BAR_23: u32,
    pub PCIE_BAR_45: u32,
    pub PCIE_EVENT_INT: u32,
    pub RESERVED9: [u32; 12],
    pub PCIE_BAR_WIN: u32,
    pub RESERVED10: [u32; 703],
    pub TEST_BUS_IN_31_0: u32,
    pub TEST_BUS_IN_63_32: u32,

}

Fields§

§SOFT_RESET: u32§DEV_CONTROL: u32§CLOCK_CONTROL: u32§RESERVED0: u32§SOFT_RESET_DEBUG_INFO: u32§SOFT_RESET_CTLR: u32§RESERVED1: [u32; 2]§SEC_ERROR_EVENT_CNT: u32§DED_ERROR_EVENT_CNT: u32§SEC_ERROR_INT: u32§SEC_ERROR_INT_MASK: u32§DED_ERROR_INT: u32§DED_ERROR_INT_MASK: u32§ECC_CONTROL: u32§ECC_ERR_LOC: u32§RAM_MARGIN_1: u32§RAM_MARGIN_2: u32§RAM_POWER_CONTROL: u32§RESERVED2: u32§DEBUG_SEL: u32§RESERVED3: [u32; 2]§LTSSM_STATE: u32§PHY_COMMON_INTERFACE: u32§PL_TX_LANEIF_0: u32§PL_RX_LANEIF_0: u32§PL_WAKECLKREQ: u32§RESERVED4: [u32; 4]§PCICONF_PCI_IDS_OVERRIDE: u32§PCICONF_PCI_IDS_31_0: u32§PCICONF_PCI_IDS_63_32: u32§PCICONF_PCI_IDS_95_64: u32§RESERVED5: [u32; 4]§PCIE_PEX_DEV_LINK_SPC2: u32§PCIE_PEX_SPC: u32§RESERVED6: [u32; 22]§PCIE_AXI_MASTER_ATR_CFG0: u32§PCIE_AXI_MASTER_ATR_CFG1: u32§PCIE_AXI_MASTER_ATR_CFG2: u32§RESERVED7: [u32; 5]§AXI_SLAVE_PCIE_ATR_CFG0: u32§AXI_SLAVE_PCIE_ATR_CFG1: u32§AXI_SLAVE_PCIE_ATR_CFG2: u32§RESERVED8: [u32; 5]§PCIE_BAR_01: u32§PCIE_BAR_23: u32§PCIE_BAR_45: u32§PCIE_EVENT_INT: u32§RESERVED9: [u32; 12]§PCIE_BAR_WIN: u32§RESERVED10: [u32; 703]§TEST_BUS_IN_31_0: u32§TEST_BUS_IN_63_32: u32

Trait Implementations§

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impl Clone for PCIE_CTRL_TypeDef

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fn clone(&self) -> PCIE_CTRL_TypeDef

Returns a duplicate of the value. Read more
1.0.0 · Source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
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impl Debug for PCIE_CTRL_TypeDef

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fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
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impl Copy for PCIE_CTRL_TypeDef

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> CloneToUninit for T
where T: Clone,

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unsafe fn clone_to_uninit(&self, dest: *mut u8)

🔬This is a nightly-only experimental API. (clone_to_uninit)
Performs copy-assignment from self to dest. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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Calls U::from(self).

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type Error = Infallible

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type Error = <U as TryFrom<T>>::Error

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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.