PCIE_BRIDGE_TypeDef

mpfs_pac

Struct PCIE_BRIDGE_TypeDef 

Source 
#[repr(C)]
pub struct PCIE_BRIDGE_TypeDef {
Show 373 fields
    pub BRIDGE_VER: u32,
    pub BRIDGE_BUS: u32,
    pub BRIDGE_IMPL_IF: u32,
    pub RESERVED: u32,
    pub PCIE_IF_CONF: u32,
    pub PCIE_BASIC_CONF: u32,
    pub PCIE_BASIC_STATUS: u32,
    pub RESERVED0: [u32; 2],
    pub AXI_SLVL_CONF: u32,
    pub RESERVED1: [u32; 2],
    pub AXI_MST0_CONF: u32,
    pub AXI_SLV0_CONF: u32,
    pub RESERVED2: [u32; 18],
    pub GEN_SETTINGS: u32,
    pub PCIE_CFGCTRL: u32,
    pub PCIE_PIPE_DW0: u32,
    pub PCIE_PIPE_DW1: u32,
    pub PCIE_VC_CRED_DW0: u32,
    pub PCIE_VC_CRED_DW1: u32,
    pub PCIE_PCI_IDS_DW0: u32,
    pub PCIE_PCI_IDS_DW1: u32,
    pub PCIE_PCI_IDS_DW2: u32,
    pub PCIE_PCI_LPM: u32,
    pub PCIE_PCI_IRQ_DW0: u32,
    pub PCIE_PCI_IRQ_DW1: u32,
    pub PCIE_PCI_IRQ_DW2: u32,
    pub PCIE_PCI_IOV_DW0: u32,
    pub PCIE_PCI_IOV_DW1: u32,
    pub RESERVED3: u32,
    pub PCIE_PEX_DEV: u32,
    pub PCIE_PEX_DEV2: u32,
    pub PCIE_PEX_LINK: u32,
    pub PCIE_PEX_SLOT: u32,
    pub PCIE_PEX_ROOT_VC: u32,
    pub PCIE_PEX_SPC: u32,
    pub PCIE_PEX_SPC2: u32,
    pub PCIE_PEX_NFTS: u32,
    pub PCIE_PEX_L1SS: u32,
    pub PCIE_BAR_01_DW0: u32,
    pub PCIE_BAR_01_DW1: u32,
    pub PCIE_BAR_23_DW0: u32,
    pub PCIE_BAR_23_DW1: u32,
    pub PCIE_BAR_45_DW0: u32,
    pub PCIE_BAR_45_DW1: u32,
    pub PCIE_BAR_WIN: u32,
    pub PCIE_EQ_PRESET_DW0: u32,
    pub PCIE_EQ_PRESET_DW1: u32,
    pub PCIE_EQ_PRESET_DW2: u32,
    pub PCIE_EQ_PRESET_DW3: u32,
    pub PCIE_EQ_PRESET_DW4: u32,
    pub PCIE_EQ_PRESET_DW5: u32,
    pub PCIE_EQ_PRESET_DW6: u32,
    pub PCIE_EQ_PRESET_DW7: u32,
    pub PCIE_SRIOV_DW0: u32,
    pub PCIE_SRIOV_DW1: u32,
    pub PCIE_SRIOV_DW2: u32,
    pub PCIE_SRIOV_DW3: u32,
    pub PCIE_SRIOV_DW4: u32,
    pub PCIE_SRIOV_DW5: u32,
    pub PCIE_SRIOV_DW6: u32,
    pub PCIE_SRIOV_DW7: u32,
    pub PCIE_CFGNUM: u32,
    pub RESERVED4: [u32; 12],
    pub PM_CONF_DW0: u32,
    pub PM_CONF_DW1: u32,
    pub PM_CONF_DW2: u32,
    pub IMASK_LOCAL: u32,
    pub ISTATUS_LOCAL: u32,
    pub IMASK_HOST: u32,
    pub ISTATUS_HOST: u32,
    pub IMSI_ADDR: u32,
    pub ISTATUS_MSI: u32,
    pub ICMD_PM: u32,
    pub ISTATUS_PM: u32,
    pub ATS_PRI_REPORT: u32,
    pub LTR_VALUES: u32,
    pub RESERVED5: [u32; 2],
    pub ISTATUS_DMA0: u32,
    pub ISTATUS_DMA1: u32,
    pub RESERVED6: [u32; 8],
    pub ISTATUS_P_ADT_WIN0: u32,
    pub ISTATUS_P_ADT_WIN1: u32,
    pub ISTATUS_A_ADT_SLV0: u32,
    pub ISTATUS_A_ADT_SLV1: u32,
    pub ISTATUS_A_ADT_SLV2: u32,
    pub ISTATUS_A_ADT_SLV3: u32,
    pub RESERVED7: [u32; 4],
    pub ROUTING_RULES_R_DW0: u32,
    pub ROUTING_RULES_R_DW1: u32,
    pub ROUTING_RULES_R_DW2: u32,
    pub ROUTING_RULES_R_DW3: u32,
    pub ROUTING_RULES_R_DW4: u32,
    pub ROUTING_RULES_R_DW5: u32,
    pub ROUTING_RULES_R_DW6: u32,
    pub ROUTING_RULES_R_DW7: u32,
    pub ROUTING_RULES_R_DW8: u32,
    pub ROUTING_RULES_R_DW9: u32,
    pub ROUTING_RULES_R_DW10: u32,
    pub ROUTING_RULES_R_DW11: u32,
    pub ROUTING_RULES_R_DW12: u32,
    pub ROUTING_RULES_R_DW13: u32,
    pub ROUTING_RULES_R_DW14: u32,
    pub ROUTING_RULES_R_DW15: u32,
    pub ROUTING_RULES_W_DW0: u32,
    pub ROUTING_RULES_W_DW1: u32,
    pub ROUTING_RULES_W_DW2: u32,
    pub ROUTING_RULES_W_DW3: u32,
    pub ROUTING_RULES_W_DW4: u32,
    pub ROUTING_RULES_W_DW5: u32,
    pub ROUTING_RULES_W_DW6: u32,
    pub ROUTING_RULES_W_DW7: u32,
    pub ROUTING_RULES_W_DW8: u32,
    pub ROUTING_RULES_W_DW9: u32,
    pub ROUTING_RULES_W_DW10: u32,
    pub ROUTING_RULES_W_DW11: u32,
    pub ROUTING_RULES_W_DW12: u32,
    pub ROUTING_RULES_W_DW13: u32,
    pub ROUTING_RULES_W_DW14: u32,
    pub ROUTING_RULES_W_DW15: u32,
    pub ARBITRATION_RULES_DW0: u32,
    pub ARBITRATION_RULES_DW1: u32,
    pub ARBITRATION_RULES_DW2: u32,
    pub ARBITRATION_RULES_DW3: u32,
    pub ARBITRATION_RULES_DW4: u32,
    pub ARBITRATION_RULES_DW5: u32,
    pub ARBITRATION_RULES_DW6: u32,
    pub ARBITRATION_RULES_DW7: u32,
    pub ARBITRATION_RULES_DW8: u32,
    pub ARBITRATION_RULES_DW9: u32,
    pub ARBITRATION_RULES_DW10: u32,
    pub ARBITRATION_RULES_DW11: u32,
    pub ARBITRATION_RULES_DW12: u32,
    pub ARBITRATION_RULES_DW13: u32,
    pub ARBITRATION_RULES_DW14: u32,
    pub ARBITRATION_RULES_DW15: u32,
    pub PRIORITY_RULES_DW0: u32,
    pub PRIORITY_RULES_DW1: u32,
    pub PRIORITY_RULES_DW2: u32,
    pub PRIORITY_RULES_DW3: u32,
    pub PRIORITY_RULES_DW4: u32,
    pub PRIORITY_RULES_DW5: u32,
    pub PRIORITY_RULES_DW6: u32,
    pub PRIORITY_RULES_DW7: u32,
    pub PRIORITY_RULES_DW8: u32,
    pub PRIORITY_RULES_DW9: u32,
    pub PRIORITY_RULES_DW10: u32,
    pub PRIORITY_RULES_DW11: u32,
    pub PRIORITY_RULES_DW12: u32,
    pub PRIORITY_RULES_DW13: u32,
    pub PRIORITY_RULES_DW14: u32,
    pub PRIORITY_RULES_DW15: u32,
    pub RESERVED8: [u32; 48],
    pub P2A_TC_QOS_CONV: u32,
    pub P2A_ATTR_CACHE_CONV: u32,
    pub P2A_NC_BASE_ADDR_DW0: u32,
    pub P2A_NC_BASE_ADDR_DW1: u32,
    pub RESERVED9: [u32; 12],
    pub DMA0_SRC_PARAM: u32,
    pub DMA0_DESTPARAM: u32,
    pub DMA0_SRCADDR_LDW: u32,
    pub DMA0_SRCADDR_UDW: u32,
    pub DMA0_DESTADDR_LDW: u32,
    pub DMA0_DESTADDR_UDW: u32,
    pub DMA0_LENGTH: u32,
    pub DMA0_CONTROL: u32,
    pub DMA0_STATUS: u32,
    pub DMA0_PRC_LENGTH: u32,
    pub DMA0_SHARE_ACCESS: u32,
    pub RESERVED10: [u32; 5],
    pub DMA1_SRC_PARAM: u32,
    pub DMA1_DESTPARAM: u32,
    pub DMA1_SRCADDR_LDW: u32,
    pub DMA1_SRCADDR_UDW: u32,
    pub DMA1_DESTADDR_LDW: u32,
    pub DMA1_DESTADDR_UDW: u32,
    pub DMA1_LENGTH: u32,
    pub DMA1_CONTROL: u32,
    pub DMA1_STATUS: u32,
    pub DMA1_PRC_LENGTH: u32,
    pub DMA1_SHARE_ACCESS: u32,
    pub RESERVED11: [u32; 101],
    pub ATR0_PCIE_WIN0_SRCADDR_PARAM: u32,
    pub ATR0_PCIE_WIN0_SRC_ADDR: u32,
    pub ATR0_PCIE_WIN0_TRSL_ADDR_LSB: u32,
    pub ATR0_PCIE_WIN0_TRSL_ADDR_UDW: u32,
    pub ATR0_PCIE_WIN0_TRSL_PARAM: u32,
    pub RESERVED12: u32,
    pub ATR0_PCIE_WIN0_TRSL_MASK_DW0: u32,
    pub ATR0_PCIE_WIN0_TRSL_MASK_DW1: u32,
    pub ATR1_PCIE_WIN0_SRCADDR_PARAM: u32,
    pub ATR1_PCIE_WIN0_SRC_ADDR: u32,
    pub ATR1_PCIE_WIN0_TRSL_ADDR_LSB: u32,
    pub ATR1_PCIE_WIN0_TRSL_ADDR_UDW: u32,
    pub ATR1_PCIE_WIN0_TRSL_PARAM: u32,
    pub RESERVED13: u32,
    pub ATR1_PCIE_WIN0_TRSL_MASK_DW0: u32,
    pub ATR1_PCIE_WIN0_TRSL_MASK_DW1: u32,
    pub ATR2_PCIE_WIN0_SRCADDR_PARAM: u32,
    pub ATR2_PCIE_WIN0_SRC_ADDR: u32,
    pub ATR2_PCIE_WIN0_TRSL_ADDR_LSB: u32,
    pub ATR2_PCIE_WIN0_TRSL_ADDR_UDW: u32,
    pub ATR2_PCIE_WIN0_TRSL_PARAM: u32,
    pub RESERVED14: u32,
    pub ATR2_PCIE_WIN0_TRSL_MASK_DW0: u32,
    pub ATR2_PCIE_WIN0_TRSL_MASK_DW1: u32,
    pub ATR3_PCIE_WIN0_SRCADDR_PARAM: u32,
    pub ATR3_PCIE_WIN0_SRC_ADDR: u32,
    pub ATR3_PCIE_WIN0_TRSL_ADDR_LSB: u32,
    pub ATR3_PCIE_WIN0_TRSL_ADDR_UDW: u32,
    pub ATR3_PCIE_WIN0_TRSL_PARAM: u32,
    pub RESERVED15: u32,
    pub ATR3_PCIE_WIN0_TRSL_MASK_DW0: u32,
    pub ATR3_PCIE_WIN0_TRSL_MASK_DW1: u32,
    pub ATR4_PCIE_WIN0_SRCADDR_PARAM: u32,
    pub ATR4_PCIE_WIN0_SRC_ADDR: u32,
    pub ATR4_PCIE_WIN0_TRSL_ADDR_LSB: u32,
    pub ATR4_PCIE_WIN0_TRSL_ADDR_UDW: u32,
    pub ATR4_PCIE_WIN0_TRSL_PARAM: u32,
    pub RESERVED16: u32,
    pub ATR4_PCIE_WIN0_TRSL_MASK_DW0: u32,
    pub ATR4_PCIE_WIN0_TRSL_MASK_DW1: u32,
    pub ATR5_PCIE_WIN0_SRCADDR_PARAM: u32,
    pub ATR5_PCIE_WIN0_SRC_ADDR: u32,
    pub ATR5_PCIE_WIN0_TRSL_ADDR_LSB: u32,
    pub ATR5_PCIE_WIN0_TRSL_ADDR_UDW: u32,
    pub ATR5_PCIE_WIN0_TRSL_PARAM: u32,
    pub RESERVED17: u32,
    pub ATR5_PCIE_WIN0_TRSL_MASK_DW0: u32,
    pub ATR5_PCIE_WIN0_TRSL_MASK_DW1: u32,
    pub ATR6_PCIE_WIN0_SRCADDR_PARAM: u32,
    pub ATR6_PCIE_WIN0_SRC_ADDR: u32,
    pub ATR6_PCIE_WIN0_TRSL_ADDR_LSB: u32,
    pub ATR6_PCIE_WIN0_TRSL_ADDR_UDW: u32,
    pub ATR6_PCIE_WIN0_TRSL_PARAM: u32,
    pub RESERVED18: u32,
    pub ATR6_PCIE_WIN0_TRSL_MASK_DW0: u32,
    pub ATR6_PCIE_WIN0_TRSL_MASK_DW1: u32,
    pub ATR7_PCIE_WIN0_SRCADDR_PARAM: u32,
    pub ATR7_PCIE_WIN0_SRC_ADDR: u32,
    pub ATR7_PCIE_WIN0_TRSL_ADDR_LSB: u32,
    pub ATR7_PCIE_WIN0_TRSL_ADDR_UDW: u32,
    pub ATR7_PCIE_WIN0_TRSL_PARAM: u32,
    pub RESERVED19: u32,
    pub ATR7_PCIE_WIN0_TRSL_MASK_DW0: u32,
    pub ATR7_PCIE_WIN0_TRSL_MASK_DW1: u32,
    pub ATR0_PCIE_WIN1_SRCADDR_PARAM: u32,
    pub ATR0_PCIE_WIN1_SRC_ADDR: u32,
    pub ATR0_PCIE_WIN1_TRSL_ADDR_LSB: u32,
    pub ATR0_PCIE_WIN1_TRSL_ADDR_UDW: u32,
    pub ATR0_PCIE_WIN1_TRSL_PARAM: u32,
    pub RESERVED20: u32,
    pub ATR0_PCIE_WIN1_TRSL_MASK_DW0: u32,
    pub ATR0_PCIE_WIN1_TRSL_MASK_DW1: u32,
    pub ATR1_PCIE_WIN1_SRCADDR_PARAM: u32,
    pub ATR1_PCIE_WIN1_SRC_ADDR: u32,
    pub ATR1_PCIE_WIN1_TRSL_ADDR_LSB: u32,
    pub ATR1_PCIE_WIN1_TRSL_ADDR_UDW: u32,
    pub ATR1_PCIE_WIN1_TRSL_PARAM: u32,
    pub RESERVED21: u32,
    pub ATR1_PCIE_WIN1_TRSL_MASK_DW0: u32,
    pub ATR1_PCIE_WIN1_TRSL_MASK_DW1: u32,
    pub ATR2_PCIE_WIN1_SRCADDR_PARAM: u32,
    pub ATR2_PCIE_WIN1_SRC_ADDR: u32,
    pub ATR2_PCIE_WIN1_TRSL_ADDR_LSB: u32,
    pub ATR2_PCIE_WIN1_TRSL_ADDR_UDW: u32,
    pub ATR2_PCIE_WIN1_TRSL_PARAM: u32,
    pub RESERVED22: u32,
    pub ATR2_PCIE_WIN1_TRSL_MASK_DW0: u32,
    pub ATR2_PCIE_WIN1_TRSL_MASK_DW1: u32,
    pub ATR3_PCIE_WIN1_SRCADDR_PARAM: u32,
    pub ATR3_PCIE_WIN1_SRC_ADDR: u32,
    pub ATR3_PCIE_WIN1_TRSL_ADDR_LSB: u32,
    pub ATR3_PCIE_WIN1_TRSL_ADDR_UDW: u32,
    pub ATR3_PCIE_WIN1_TRSL_PARAM: u32,
    pub RESERVED23: u32,
    pub ATR3_PCIE_WIN1_TRSL_MASK_DW0: u32,
    pub ATR3_PCIE_WIN1_TRSL_MASK_DW1: u32,
    pub ATR4_PCIE_WIN1_SRCADDR_PARAM: u32,
    pub ATR4_PCIE_WIN1_SRC_ADDR: u32,
    pub ATR4_PCIE_WIN1_TRSL_ADDR_LSB: u32,
    pub ATR4_PCIE_WIN1_TRSL_ADDR_UDW: u32,
    pub ATR4_PCIE_WIN1_TRSL_PARAM: u32,
    pub RESERVED24: u32,
    pub ATR4_PCIE_WIN1_TRSL_MASK_DW0: u32,
    pub ATR4_PCIE_WIN1_TRSL_MASK_DW1: u32,
    pub ATR5_PCIE_WIN1_SRCADDR_PARAM: u32,
    pub ATR5_PCIE_WIN1_SRC_ADDR: u32,
    pub ATR5_PCIE_WIN1_TRSL_ADDR_LSB: u32,
    pub ATR5_PCIE_WIN1_TRSL_ADDR_UDW: u32,
    pub ATR5_PCIE_WIN1_TRSL_PARAM: u32,
    pub RESERVED25: u32,
    pub ATR5_PCIE_WIN1_TRSL_MASK_DW0: u32,
    pub ATR5_PCIE_WIN1_TRSL_MASK_DW1: u32,
    pub ATR6_PCIE_WIN1_SRCADDR_PARAM: u32,
    pub ATR6_PCIE_WIN1_SRC_ADDR: u32,
    pub ATR6_PCIE_WIN1_TRSL_ADDR_LSB: u32,
    pub ATR6_PCIE_WIN1_TRSL_ADDR_UDW: u32,
    pub ATR6_PCIE_WIN1_TRSL_PARAM: u32,
    pub RESERVED26: u32,
    pub ATR6_PCIE_WIN1_TRSL_MASK_DW0: u32,
    pub ATR6_PCIE_WIN1_TRSL_MASK_DW1: u32,
    pub ATR7_PCIE_WIN1_SRCADDR_PARAM: u32,
    pub ATR7_PCIE_WIN1_SRC_ADDR: u32,
    pub ATR7_PCIE_WIN1_TRSL_ADDR_LSB: u32,
    pub ATR7_PCIE_WIN1_TRSL_ADDR_UDW: u32,
    pub ATR7_PCIE_WIN1_TRSL_PARAM: u32,
    pub RESERVED27: u32,
    pub ATR7_PCIE_WIN1_TRSL_MASK_DW0: u32,
    pub ATR7_PCIE_WIN1_TRSL_MASK_DW1: u32,
    pub ATR0_AXI4_SLV0_SRCADDR_PARAM: u32,
    pub ATR0_AXI4_SLV0_SRC_ADDR: u32,
    pub ATR0_AXI4_SLV0_TRSL_ADDR_LSB: u32,
    pub ATR0_AXI4_SLV0_TRSL_ADDR_UDW: u32,
    pub ATR0_AXI4_SLV0_TRSL_PARAM: u32,
    pub RESERVED28: u32,
    pub ATR0_AXI4_SLV0_TRSL_MASK_DW0: u32,
    pub ATR0_AXI4_SLV0_TRSL_MASK_DW1: u32,
    pub ATR1_AXI4_SLV0_SRCADDR_PARAM: u32,
    pub ATR1_AXI4_SLV0_SRC_ADDR: u32,
    pub ATR1_AXI4_SLV0_TRSL_ADDR_LSB: u32,
    pub ATR1_AXI4_SLV0_TRSL_ADDR_UDW: u32,
    pub ATR1_AXI4_SLV0_TRSL_PARAM: u32,
    pub RESERVED29: u32,
    pub ATR1_AXI4_SLV0_TRSL_MASK_DW0: u32,
    pub ATR1_AXI4_SLV0_TRSL_MASK_DW1: u32,
    pub ATR2_AXI4_SLV0_SRCADDR_PARAM: u32,
    pub ATR2_AXI4_SLV0_SRC_ADDR: u32,
    pub ATR2_AXI4_SLV0_TRSL_ADDR_LSB: u32,
    pub ATR2_AXI4_SLV0_TRSL_ADDR_UDW: u32,
    pub ATR2_AXI4_SLV0_TRSL_PARAM: u32,
    pub RESERVED30: u32,
    pub ATR2_AXI4_SLV0_TRSL_MASK_DW0: u32,
    pub ATR2_AXI4_SLV0_TRSL_MASK_DW1: u32,
    pub ATR3_AXI4_SLV0_SRCADDR_PARAM: u32,
    pub ATR3_AXI4_SLV0_SRC_ADDR: u32,
    pub ATR3_AXI4_SLV0_TRSL_ADDR_LSB: u32,
    pub ATR3_AXI4_SLV0_TRSL_ADDR_UDW: u32,
    pub ATR3_AXI4_SLV0_TRSL_PARAM: u32,
    pub RESERVED31: u32,
    pub ATR3_AXI4_SLV0_TRSL_MASK_DW0: u32,
    pub ATR3_AXI4_SLV0_TRSL_MASK_DW1: u32,
    pub ATR4_AXI4_SLV0_SRCADDR_PARAM: u32,
    pub ATR4_AXI4_SLV0_SRC_ADDR: u32,
    pub ATR4_AXI4_SLV0_TRSL_ADDR_LSB: u32,
    pub ATR4_AXI4_SLV0_TRSL_ADDR_UDW: u32,
    pub ATR4_AXI4_SLV0_TRSL_PARAM: u32,
    pub RESERVED32: u32,
    pub ATR4_AXI4_SLV0_TRSL_MASK_DW0: u32,
    pub ATR4_AXI4_SLV0_TRSL_MASK_DW1: u32,
    pub ATR5_AXI4_SLV0_SRCADDR_PARAM: u32,
    pub ATR5_AXI4_SLV0_SRC_ADDR: u32,
    pub ATR5_AXI4_SLV0_TRSL_ADDR_LSB: u32,
    pub ATR5_AXI4_SLV0_TRSL_ADDR_UDW: u32,
    pub ATR5_AXI4_SLV0_TRSL_PARAM: u32,
    pub RESERVED33: u32,
    pub ATR5_AXI4_SLV0_TRSL_MASK_DW0: u32,
    pub ATR5_AXI4_SLV0_TRSL_MASK_DW1: u32,
    pub ATR6_AXI4_SLV0_SRCADDR_PARAM: u32,
    pub ATR6_AXI4_SLV0_SRC_ADDR: u32,
    pub ATR6_AXI4_SLV0_TRSL_ADDR_LSB: u32,
    pub ATR6_AXI4_SLV0_TRSL_ADDR_UDW: u32,
    pub ATR6_AXI4_SLV0_TRSL_PARAM: u32,
    pub RESERVED34: u32,
    pub ATR6_AXI4_SLV0_TRSL_MASK_DW0: u32,
    pub ATR6_AXI4_SLV0_TRSL_MASK_DW1: u32,
    pub ATR7_AXI4_SLV0_SRCADDR_PARAM: u32,
    pub ATR7_AXI4_SLV0_SRC_ADDR: u32,
    pub ATR7_AXI4_SLV0_TRSL_ADDR_LSB: u32,
    pub ATR7_AXI4_SLV0_TRSL_ADDR_UDW: u32,
    pub ATR7_AXI4_SLV0_TRSL_PARAM: u32,
    pub RESERVED35: u32,
    pub ATR7_AXI4_SLV0_TRSL_MASK_DW0: u32,
    pub ATR7_AXI4_SLV0_TRSL_MASK_DW1: u32,

}

Fields§

§BRIDGE_VER: u32§BRIDGE_BUS: u32§BRIDGE_IMPL_IF: u32§RESERVED: u32§PCIE_IF_CONF: u32§PCIE_BASIC_CONF: u32§PCIE_BASIC_STATUS: u32§RESERVED0: [u32; 2]§AXI_SLVL_CONF: u32§RESERVED1: [u32; 2]§AXI_MST0_CONF: u32§AXI_SLV0_CONF: u32§RESERVED2: [u32; 18]§GEN_SETTINGS: u32§PCIE_CFGCTRL: u32§PCIE_PIPE_DW0: u32§PCIE_PIPE_DW1: u32§PCIE_VC_CRED_DW0: u32§PCIE_VC_CRED_DW1: u32§PCIE_PCI_IDS_DW0: u32§PCIE_PCI_IDS_DW1: u32§PCIE_PCI_IDS_DW2: u32§PCIE_PCI_LPM: u32§PCIE_PCI_IRQ_DW0: u32§PCIE_PCI_IRQ_DW1: u32§PCIE_PCI_IRQ_DW2: u32§PCIE_PCI_IOV_DW0: u32§PCIE_PCI_IOV_DW1: u32§RESERVED3: u32§PCIE_PEX_DEV: u32§PCIE_PEX_DEV2: u32§PCIE_PEX_LINK: u32§PCIE_PEX_SLOT: u32§PCIE_PEX_ROOT_VC: u32§PCIE_PEX_SPC: u32§PCIE_PEX_SPC2: u32§PCIE_PEX_NFTS: u32§PCIE_PEX_L1SS: u32§PCIE_BAR_01_DW0: u32§PCIE_BAR_01_DW1: u32§PCIE_BAR_23_DW0: u32§PCIE_BAR_23_DW1: u32§PCIE_BAR_45_DW0: u32§PCIE_BAR_45_DW1: u32§PCIE_BAR_WIN: u32§PCIE_EQ_PRESET_DW0: u32§PCIE_EQ_PRESET_DW1: u32§PCIE_EQ_PRESET_DW2: u32§PCIE_EQ_PRESET_DW3: u32§PCIE_EQ_PRESET_DW4: u32§PCIE_EQ_PRESET_DW5: u32§PCIE_EQ_PRESET_DW6: u32§PCIE_EQ_PRESET_DW7: u32§PCIE_SRIOV_DW0: u32§PCIE_SRIOV_DW1: u32§PCIE_SRIOV_DW2: u32§PCIE_SRIOV_DW3: u32§PCIE_SRIOV_DW4: u32§PCIE_SRIOV_DW5: u32§PCIE_SRIOV_DW6: u32§PCIE_SRIOV_DW7: u32§PCIE_CFGNUM: u32§RESERVED4: [u32; 12]§PM_CONF_DW0: u32§PM_CONF_DW1: u32§PM_CONF_DW2: u32§IMASK_LOCAL: u32§ISTATUS_LOCAL: u32§IMASK_HOST: u32§ISTATUS_HOST: u32§IMSI_ADDR: u32§ISTATUS_MSI: u32§ICMD_PM: u32§ISTATUS_PM: u32§ATS_PRI_REPORT: u32§LTR_VALUES: u32§RESERVED5: [u32; 2]§ISTATUS_DMA0: u32§ISTATUS_DMA1: u32§RESERVED6: [u32; 8]§ISTATUS_P_ADT_WIN0: u32§ISTATUS_P_ADT_WIN1: u32§ISTATUS_A_ADT_SLV0: u32§ISTATUS_A_ADT_SLV1: u32§ISTATUS_A_ADT_SLV2: u32§ISTATUS_A_ADT_SLV3: u32§RESERVED7: [u32; 4]§ROUTING_RULES_R_DW0: u32§ROUTING_RULES_R_DW1: u32§ROUTING_RULES_R_DW2: u32§ROUTING_RULES_R_DW3: u32§ROUTING_RULES_R_DW4: u32§ROUTING_RULES_R_DW5: u32§ROUTING_RULES_R_DW6: u32§ROUTING_RULES_R_DW7: u32§ROUTING_RULES_R_DW8: u32§ROUTING_RULES_R_DW9: u32§ROUTING_RULES_R_DW10: u32§ROUTING_RULES_R_DW11: u32§ROUTING_RULES_R_DW12: u32§ROUTING_RULES_R_DW13: u32§ROUTING_RULES_R_DW14: u32§ROUTING_RULES_R_DW15: u32§ROUTING_RULES_W_DW0: u32§ROUTING_RULES_W_DW1: u32§ROUTING_RULES_W_DW2: u32§ROUTING_RULES_W_DW3: u32§ROUTING_RULES_W_DW4: u32§ROUTING_RULES_W_DW5: u32§ROUTING_RULES_W_DW6: u32§ROUTING_RULES_W_DW7: u32§ROUTING_RULES_W_DW8: u32§ROUTING_RULES_W_DW9: u32§ROUTING_RULES_W_DW10: u32§ROUTING_RULES_W_DW11: u32§ROUTING_RULES_W_DW12: u32§ROUTING_RULES_W_DW13: u32§ROUTING_RULES_W_DW14: u32§ROUTING_RULES_W_DW15: u32§ARBITRATION_RULES_DW0: u32§ARBITRATION_RULES_DW1: u32§ARBITRATION_RULES_DW2: u32§ARBITRATION_RULES_DW3: u32§ARBITRATION_RULES_DW4: u32§ARBITRATION_RULES_DW5: u32§ARBITRATION_RULES_DW6: u32§ARBITRATION_RULES_DW7: u32§ARBITRATION_RULES_DW8: u32§ARBITRATION_RULES_DW9: u32§ARBITRATION_RULES_DW10: u32§ARBITRATION_RULES_DW11: u32§ARBITRATION_RULES_DW12: u32§ARBITRATION_RULES_DW13: u32§ARBITRATION_RULES_DW14: u32§ARBITRATION_RULES_DW15: u32§PRIORITY_RULES_DW0: u32§PRIORITY_RULES_DW1: u32§PRIORITY_RULES_DW2: u32§PRIORITY_RULES_DW3: u32§PRIORITY_RULES_DW4: u32§PRIORITY_RULES_DW5: u32§PRIORITY_RULES_DW6: u32§PRIORITY_RULES_DW7: u32§PRIORITY_RULES_DW8: u32§PRIORITY_RULES_DW9: u32§PRIORITY_RULES_DW10: u32§PRIORITY_RULES_DW11: u32§PRIORITY_RULES_DW12: u32§PRIORITY_RULES_DW13: u32§PRIORITY_RULES_DW14: u32§PRIORITY_RULES_DW15: u32§RESERVED8: [u32; 48]§P2A_TC_QOS_CONV: u32§P2A_ATTR_CACHE_CONV: u32§P2A_NC_BASE_ADDR_DW0: u32§P2A_NC_BASE_ADDR_DW1: u32§RESERVED9: [u32; 12]§DMA0_SRC_PARAM: u32§DMA0_DESTPARAM: u32§DMA0_SRCADDR_LDW: u32§DMA0_SRCADDR_UDW: u32§DMA0_DESTADDR_LDW: u32§DMA0_DESTADDR_UDW: u32§DMA0_LENGTH: u32§DMA0_CONTROL: u32§DMA0_STATUS: u32§DMA0_PRC_LENGTH: u32§DMA0_SHARE_ACCESS: u32§RESERVED10: [u32; 5]§DMA1_SRC_PARAM: u32§DMA1_DESTPARAM: u32§DMA1_SRCADDR_LDW: u32§DMA1_SRCADDR_UDW: u32§DMA1_DESTADDR_LDW: u32§DMA1_DESTADDR_UDW: u32§DMA1_LENGTH: u32§DMA1_CONTROL: u32§DMA1_STATUS: u32§DMA1_PRC_LENGTH: u32§DMA1_SHARE_ACCESS: u32§RESERVED11: [u32; 101]§ATR0_PCIE_WIN0_SRCADDR_PARAM: u32§ATR0_PCIE_WIN0_SRC_ADDR: u32§ATR0_PCIE_WIN0_TRSL_ADDR_LSB: u32§ATR0_PCIE_WIN0_TRSL_ADDR_UDW: u32§ATR0_PCIE_WIN0_TRSL_PARAM: u32§RESERVED12: u32§ATR0_PCIE_WIN0_TRSL_MASK_DW0: u32§ATR0_PCIE_WIN0_TRSL_MASK_DW1: u32§ATR1_PCIE_WIN0_SRCADDR_PARAM: u32§ATR1_PCIE_WIN0_SRC_ADDR: u32§ATR1_PCIE_WIN0_TRSL_ADDR_LSB: u32§ATR1_PCIE_WIN0_TRSL_ADDR_UDW: u32§ATR1_PCIE_WIN0_TRSL_PARAM: u32§RESERVED13: u32§ATR1_PCIE_WIN0_TRSL_MASK_DW0: u32§ATR1_PCIE_WIN0_TRSL_MASK_DW1: u32§ATR2_PCIE_WIN0_SRCADDR_PARAM: u32§ATR2_PCIE_WIN0_SRC_ADDR: u32§ATR2_PCIE_WIN0_TRSL_ADDR_LSB: u32§ATR2_PCIE_WIN0_TRSL_ADDR_UDW: u32§ATR2_PCIE_WIN0_TRSL_PARAM: u32§RESERVED14: u32§ATR2_PCIE_WIN0_TRSL_MASK_DW0: u32§ATR2_PCIE_WIN0_TRSL_MASK_DW1: u32§ATR3_PCIE_WIN0_SRCADDR_PARAM: u32§ATR3_PCIE_WIN0_SRC_ADDR: u32§ATR3_PCIE_WIN0_TRSL_ADDR_LSB: u32§ATR3_PCIE_WIN0_TRSL_ADDR_UDW: u32§ATR3_PCIE_WIN0_TRSL_PARAM: u32§RESERVED15: u32§ATR3_PCIE_WIN0_TRSL_MASK_DW0: u32§ATR3_PCIE_WIN0_TRSL_MASK_DW1: u32§ATR4_PCIE_WIN0_SRCADDR_PARAM: u32§ATR4_PCIE_WIN0_SRC_ADDR: u32§ATR4_PCIE_WIN0_TRSL_ADDR_LSB: u32§ATR4_PCIE_WIN0_TRSL_ADDR_UDW: u32§ATR4_PCIE_WIN0_TRSL_PARAM: u32§RESERVED16: u32§ATR4_PCIE_WIN0_TRSL_MASK_DW0: u32§ATR4_PCIE_WIN0_TRSL_MASK_DW1: u32§ATR5_PCIE_WIN0_SRCADDR_PARAM: u32§ATR5_PCIE_WIN0_SRC_ADDR: u32§ATR5_PCIE_WIN0_TRSL_ADDR_LSB: u32§ATR5_PCIE_WIN0_TRSL_ADDR_UDW: u32§ATR5_PCIE_WIN0_TRSL_PARAM: u32§RESERVED17: u32§ATR5_PCIE_WIN0_TRSL_MASK_DW0: u32§ATR5_PCIE_WIN0_TRSL_MASK_DW1: u32§ATR6_PCIE_WIN0_SRCADDR_PARAM: u32§ATR6_PCIE_WIN0_SRC_ADDR: u32§ATR6_PCIE_WIN0_TRSL_ADDR_LSB: u32§ATR6_PCIE_WIN0_TRSL_ADDR_UDW: u32§ATR6_PCIE_WIN0_TRSL_PARAM: u32§RESERVED18: u32§ATR6_PCIE_WIN0_TRSL_MASK_DW0: u32§ATR6_PCIE_WIN0_TRSL_MASK_DW1: u32§ATR7_PCIE_WIN0_SRCADDR_PARAM: u32§ATR7_PCIE_WIN0_SRC_ADDR: u32§ATR7_PCIE_WIN0_TRSL_ADDR_LSB: u32§ATR7_PCIE_WIN0_TRSL_ADDR_UDW: u32§ATR7_PCIE_WIN0_TRSL_PARAM: u32§RESERVED19: u32§ATR7_PCIE_WIN0_TRSL_MASK_DW0: u32§ATR7_PCIE_WIN0_TRSL_MASK_DW1: u32§ATR0_PCIE_WIN1_SRCADDR_PARAM: u32§ATR0_PCIE_WIN1_SRC_ADDR: u32§ATR0_PCIE_WIN1_TRSL_ADDR_LSB: u32§ATR0_PCIE_WIN1_TRSL_ADDR_UDW: u32§ATR0_PCIE_WIN1_TRSL_PARAM: u32§RESERVED20: u32§ATR0_PCIE_WIN1_TRSL_MASK_DW0: u32§ATR0_PCIE_WIN1_TRSL_MASK_DW1: u32§ATR1_PCIE_WIN1_SRCADDR_PARAM: u32§ATR1_PCIE_WIN1_SRC_ADDR: u32§ATR1_PCIE_WIN1_TRSL_ADDR_LSB: u32§ATR1_PCIE_WIN1_TRSL_ADDR_UDW: u32§ATR1_PCIE_WIN1_TRSL_PARAM: u32§RESERVED21: u32§ATR1_PCIE_WIN1_TRSL_MASK_DW0: u32§ATR1_PCIE_WIN1_TRSL_MASK_DW1: u32§ATR2_PCIE_WIN1_SRCADDR_PARAM: u32§ATR2_PCIE_WIN1_SRC_ADDR: u32§ATR2_PCIE_WIN1_TRSL_ADDR_LSB: u32§ATR2_PCIE_WIN1_TRSL_ADDR_UDW: u32§ATR2_PCIE_WIN1_TRSL_PARAM: u32§RESERVED22: u32§ATR2_PCIE_WIN1_TRSL_MASK_DW0: u32§ATR2_PCIE_WIN1_TRSL_MASK_DW1: u32§ATR3_PCIE_WIN1_SRCADDR_PARAM: u32§ATR3_PCIE_WIN1_SRC_ADDR: u32§ATR3_PCIE_WIN1_TRSL_ADDR_LSB: u32§ATR3_PCIE_WIN1_TRSL_ADDR_UDW: u32§ATR3_PCIE_WIN1_TRSL_PARAM: u32§RESERVED23: u32§ATR3_PCIE_WIN1_TRSL_MASK_DW0: u32§ATR3_PCIE_WIN1_TRSL_MASK_DW1: u32§ATR4_PCIE_WIN1_SRCADDR_PARAM: u32§ATR4_PCIE_WIN1_SRC_ADDR: u32§ATR4_PCIE_WIN1_TRSL_ADDR_LSB: u32§ATR4_PCIE_WIN1_TRSL_ADDR_UDW: u32§ATR4_PCIE_WIN1_TRSL_PARAM: u32§RESERVED24: u32§ATR4_PCIE_WIN1_TRSL_MASK_DW0: u32§ATR4_PCIE_WIN1_TRSL_MASK_DW1: u32§ATR5_PCIE_WIN1_SRCADDR_PARAM: u32§ATR5_PCIE_WIN1_SRC_ADDR: u32§ATR5_PCIE_WIN1_TRSL_ADDR_LSB: u32§ATR5_PCIE_WIN1_TRSL_ADDR_UDW: u32§ATR5_PCIE_WIN1_TRSL_PARAM: u32§RESERVED25: u32§ATR5_PCIE_WIN1_TRSL_MASK_DW0: u32§ATR5_PCIE_WIN1_TRSL_MASK_DW1: u32§ATR6_PCIE_WIN1_SRCADDR_PARAM: u32§ATR6_PCIE_WIN1_SRC_ADDR: u32§ATR6_PCIE_WIN1_TRSL_ADDR_LSB: u32§ATR6_PCIE_WIN1_TRSL_ADDR_UDW: u32§ATR6_PCIE_WIN1_TRSL_PARAM: u32§RESERVED26: u32§ATR6_PCIE_WIN1_TRSL_MASK_DW0: u32§ATR6_PCIE_WIN1_TRSL_MASK_DW1: u32§ATR7_PCIE_WIN1_SRCADDR_PARAM: u32§ATR7_PCIE_WIN1_SRC_ADDR: u32§ATR7_PCIE_WIN1_TRSL_ADDR_LSB: u32§ATR7_PCIE_WIN1_TRSL_ADDR_UDW: u32§ATR7_PCIE_WIN1_TRSL_PARAM: u32§RESERVED27: u32§ATR7_PCIE_WIN1_TRSL_MASK_DW0: u32§ATR7_PCIE_WIN1_TRSL_MASK_DW1: u32§ATR0_AXI4_SLV0_SRCADDR_PARAM: u32§ATR0_AXI4_SLV0_SRC_ADDR: u32§ATR0_AXI4_SLV0_TRSL_ADDR_LSB: u32§ATR0_AXI4_SLV0_TRSL_ADDR_UDW: u32§ATR0_AXI4_SLV0_TRSL_PARAM: u32§RESERVED28: u32§ATR0_AXI4_SLV0_TRSL_MASK_DW0: u32§ATR0_AXI4_SLV0_TRSL_MASK_DW1: u32§ATR1_AXI4_SLV0_SRCADDR_PARAM: u32§ATR1_AXI4_SLV0_SRC_ADDR: u32§ATR1_AXI4_SLV0_TRSL_ADDR_LSB: u32§ATR1_AXI4_SLV0_TRSL_ADDR_UDW: u32§ATR1_AXI4_SLV0_TRSL_PARAM: u32§RESERVED29: u32§ATR1_AXI4_SLV0_TRSL_MASK_DW0: u32§ATR1_AXI4_SLV0_TRSL_MASK_DW1: u32§ATR2_AXI4_SLV0_SRCADDR_PARAM: u32§ATR2_AXI4_SLV0_SRC_ADDR: u32§ATR2_AXI4_SLV0_TRSL_ADDR_LSB: u32§ATR2_AXI4_SLV0_TRSL_ADDR_UDW: u32§ATR2_AXI4_SLV0_TRSL_PARAM: u32§RESERVED30: u32§ATR2_AXI4_SLV0_TRSL_MASK_DW0: u32§ATR2_AXI4_SLV0_TRSL_MASK_DW1: u32§ATR3_AXI4_SLV0_SRCADDR_PARAM: u32§ATR3_AXI4_SLV0_SRC_ADDR: u32§ATR3_AXI4_SLV0_TRSL_ADDR_LSB: u32§ATR3_AXI4_SLV0_TRSL_ADDR_UDW: u32§ATR3_AXI4_SLV0_TRSL_PARAM: u32§RESERVED31: u32§ATR3_AXI4_SLV0_TRSL_MASK_DW0: u32§ATR3_AXI4_SLV0_TRSL_MASK_DW1: u32§ATR4_AXI4_SLV0_SRCADDR_PARAM: u32§ATR4_AXI4_SLV0_SRC_ADDR: u32§ATR4_AXI4_SLV0_TRSL_ADDR_LSB: u32§ATR4_AXI4_SLV0_TRSL_ADDR_UDW: u32§ATR4_AXI4_SLV0_TRSL_PARAM: u32§RESERVED32: u32§ATR4_AXI4_SLV0_TRSL_MASK_DW0: u32§ATR4_AXI4_SLV0_TRSL_MASK_DW1: u32§ATR5_AXI4_SLV0_SRCADDR_PARAM: u32§ATR5_AXI4_SLV0_SRC_ADDR: u32§ATR5_AXI4_SLV0_TRSL_ADDR_LSB: u32§ATR5_AXI4_SLV0_TRSL_ADDR_UDW: u32§ATR5_AXI4_SLV0_TRSL_PARAM: u32§RESERVED33: u32§ATR5_AXI4_SLV0_TRSL_MASK_DW0: u32§ATR5_AXI4_SLV0_TRSL_MASK_DW1: u32§ATR6_AXI4_SLV0_SRCADDR_PARAM: u32§ATR6_AXI4_SLV0_SRC_ADDR: u32§ATR6_AXI4_SLV0_TRSL_ADDR_LSB: u32§ATR6_AXI4_SLV0_TRSL_ADDR_UDW: u32§ATR6_AXI4_SLV0_TRSL_PARAM: u32§RESERVED34: u32§ATR6_AXI4_SLV0_TRSL_MASK_DW0: u32§ATR6_AXI4_SLV0_TRSL_MASK_DW1: u32§ATR7_AXI4_SLV0_SRCADDR_PARAM: u32§ATR7_AXI4_SLV0_SRC_ADDR: u32§ATR7_AXI4_SLV0_TRSL_ADDR_LSB: u32§ATR7_AXI4_SLV0_TRSL_ADDR_UDW: u32§ATR7_AXI4_SLV0_TRSL_PARAM: u32§RESERVED35: u32§ATR7_AXI4_SLV0_TRSL_MASK_DW0: u32§ATR7_AXI4_SLV0_TRSL_MASK_DW1: u32

Trait Implementations§

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impl Clone for PCIE_BRIDGE_TypeDef

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fn clone(&self) -> PCIE_BRIDGE_TypeDef

Returns a duplicate of the value. Read more
1.0.0 · Source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
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impl Debug for PCIE_BRIDGE_TypeDef

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fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
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impl Copy for PCIE_BRIDGE_TypeDef

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> CloneToUninit for T
where T: Clone,

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unsafe fn clone_to_uninit(&self, dest: *mut u8)

🔬This is a nightly-only experimental API. (clone_to_uninit)
Performs copy-assignment from self to dest. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T, U> TryFrom<U> for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.
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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.