Crate mpfs_pac Copy item path Source AXISW_TypeDef BEU_Type_ BEU_Types_ CACHE_CONFIG_typedef CACHE_CTRL_typedef CAN_device CFG_DDR_SGMII_PHY_BANK_STATUS_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_BCLKMUX_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_CH0_CNTL_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_CH1_CNTL_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_CLK_CNTL_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_DDRPHY_MODE_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_DDRPHY_STARTUP_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_DPC_BITS_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_DYN_CNTL_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_FMETER_ADDR_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_FMETER_DATAR_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_FMETER_DATAW_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_IOC_REG0_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_IOC_REG1_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_IOC_REG2_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_IOC_REG3_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_IOC_REG4_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_IOC_REG5_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_IOC_REG6_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_MSSCLKMUX_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_CAL_IOSCB_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_CAL_MAIN_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_CKMUX_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_CNTL_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_CTRL2_IOSCB_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_CTRL2_MAIN_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_CTRL_IOSCB_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_CTRL_MAIN_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_DIV_0_1_IOSCB_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_DIV_0_1_MAIN_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_DIV_2_3_IOSCB_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_DIV_2_3_MAIN_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_FRACN_IOSCB_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_FRACN_MAIN_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_PHADJ_IOSCB_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_PHADJ_MAIN_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_REF_FB_IOSCB_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PLL_REF_FB_MAIN_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_PVT_STAT_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_RECAL_CNTL_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_RPC_RESET_BANK_CTRL_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_RPC_RESET_CFM_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_RPC_RESET_IOCALIB_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_RPC_RESET_IOSCB_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_RPC_RESET_MAIN_PLL_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SGMII_MODE_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SOFT_RESET_SGMII_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SPARE0_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SPARE_CNTL_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SPARE_STAT_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SSCG_REG_0_IOSCB_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SSCG_REG_0_MAIN_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SSCG_REG_1_IOSCB_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SSCG_REG_1_MAIN_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SSCG_REG_2_IOSCB_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SSCG_REG_2_MAIN_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SSCG_REG_3_IOSCB_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_SSCG_REG_3_MAIN_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_TEST_CTRL_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_TypeDef CFG_DDR_SGMII_PHY_addcmd_answer_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_addcmd_status0_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_addcmd_status1_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_bclksclk_answer_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_delta0_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_delta1_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_dq_dqs_err_done_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_dqdqs_state_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_dqdqs_status0_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_dqdqs_status1_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_dqdqs_status2_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_dqdqs_status3_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_dqdqs_status4_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_dqdqs_status5_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_dqdqs_status6_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_dqdqs_window_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_dqdqs_wrcalib_offset_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_addcmd_ln_readback_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_calif_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_calif_readback1_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_calif_readback_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_dfi_status_override_to_shim_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_dlycnt_direction_reg0_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_dlycnt_direction_reg1_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_dlycnt_load_reg0_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_dlycnt_load_reg1_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_dlycnt_move_reg0_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_dlycnt_move_reg1_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_dlycnt_mv_rd_dly_reg_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_dlycnt_oor_reg0_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_dlycnt_oor_reg1_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_dlycnt_pause_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_dq_dqs_optimization0_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_dq_dqs_optimization1_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_dqlane_readback_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_mode_en_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_pllcnt_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_read_gate_controls_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_expert_wrcalib_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_gt_clk_sel_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_gt_err_comb_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_gt_state_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_gt_steps_180_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_gt_txdly_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_lane_alignment_fifo_control_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_lane_select_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_ovrt1_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_ovrt2_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_ovrt3_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_ovrt4_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_ovrt5_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_ovrt6_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_ovrt7_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_ovrt8_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_ovrt9_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_ovrt10_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_ovrt11_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_ovrt12_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_ovrt13_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_ovrt14_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_ovrt15_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_ovrt16_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rank_select_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc1_DRV_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc1_ODT_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc2_DRV_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc2_ODT_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc3_DRV_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc3_ODT_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc4_DRV_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc4_ODT_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc5_ODT_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc6_ODT_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc7_ODT_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc8_ODT_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc9_ODT_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc10_ODT_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc11_ODT_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc17_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc18_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc19_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc20_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc21_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc22_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc23_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc24_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc25_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc26_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc27_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc28_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc29_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc30_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc31_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc32_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc33_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc34_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc35_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc36_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc37_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc38_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc39_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc40_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc41_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc42_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc43_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc44_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc45_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc46_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc47_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc48_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc49_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc50_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc51_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc52_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc53_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc54_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc55_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc56_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc57_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc58_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc59_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc60_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc61_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc62_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc63_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc64_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc65_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc66_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc67_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc68_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc69_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc70_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc71_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc72_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc73_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc74_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc75_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc76_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc77_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc78_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc79_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc80_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc81_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc82_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc83_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc84_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc85_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc86_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc87_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc88_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc89_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc90_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc91_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc92_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc93_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc94_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc95_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc96_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc97_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc98_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc99_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc100_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc101_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc102_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc103_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc104_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc105_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc106_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc107_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc108_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc109_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc110_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc111_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc112_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc113_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc114_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc115_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc116_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc117_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc118_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc119_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc120_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc121_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc122_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc123_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc124_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc125_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc126_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc127_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc128_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc129_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc130_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc131_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc132_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc133_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc134_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc135_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc136_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc137_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc138_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc139_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc140_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc141_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc142_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc143_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc144_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc145_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc146_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc147_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc148_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc149_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc150_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc151_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc152_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc153_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc154_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc155_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc156_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc157_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc158_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc159_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc160_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc161_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc162_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc163_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc164_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc165_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc166_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc167_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc168_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc169_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc170_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc171_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc172_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc173_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc174_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc175_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc176_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc177_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc178_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc179_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc180_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc181_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc182_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc183_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc184_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc185_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc186_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc187_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc188_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc189_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc190_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc191_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc192_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc193_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc194_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc195_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc196_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc197_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc198_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc199_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc200_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc201_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc202_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc203_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc204_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc205_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc206_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc207_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc208_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc209_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc210_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc211_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc212_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc213_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc214_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc215_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc216_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc217_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc218_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc219_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc220_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc221_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc222_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc223_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc224_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc225_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc226_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc227_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc228_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc229_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc230_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc231_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc232_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc233_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc234_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc235_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc236_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc237_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc238_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc239_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc240_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc241_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc242_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc243_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc244_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc245_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc246_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc247_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc248_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc249_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc250_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_rpc_calib_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_spio251_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_spio252_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_spio253_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_tip_cfg_params_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_tip_vref_param_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_training_reset_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_training_skip_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_training_start_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_training_status_TypeDef__bindgen_ty_1 CFG_DDR_SGMII_PHY_wl_delay_0_TypeDef__bindgen_ty_1 CLINT_Type_t DDR_CSR_APB_ADDR_MAP_TypeDef DDR_CSR_APB_AXI_IF_TypeDef DDR_CSR_APB_CA_PAR_ERR_TypeDef DDR_CSR_APB_CFG_ACTIVE_DQ_SEL_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ADDR_MIRROR_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ADVANCE_ACTIVATE_READY_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_AL_MODE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ASYNC_ODT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_AUTO_REF_EN_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_AUTO_SR_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_AUTO_ZQ_CAL_EN_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_AXI_AUTO_PCH_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_AXI_END_ADDRESS_AXI1_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_AXI_END_ADDRESS_AXI1_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_AXI_END_ADDRESS_AXI2_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_AXI_END_ADDRESS_AXI2_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_AXI_START_ADDRESS_AXI1_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_AXI_START_ADDRESS_AXI1_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_AXI_START_ADDRESS_AXI2_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_AXI_START_ADDRESS_AXI2_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BANKADDR_MAP_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BANKADDR_MAP_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BG_INTERLEAVE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS0_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS0_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS1_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS1_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS2_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS2_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS3_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS3_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS4_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS4_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS5_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS5_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS6_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS6_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS7_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS7_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS8_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS8_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS9_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS9_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS10_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS10_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS11_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS11_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS12_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS12_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS13_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS13_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS14_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS14_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS15_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS15_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BL_MODE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BL_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_BURST_RW_REFRESH_HOLDOFF_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CAL_READ_PERIOD_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CA_ODT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CA_PARITY_ERR_STATUS_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CA_PARITY_LATENCY_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CA_PARITY_PERSIST_ERR_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CCD_L_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CCD_S_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CHIPADDR_MAP_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CIDADDR_MAP_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CKSRE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CKSRX_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CL_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_COLADDR_MAP_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_COLADDR_MAP_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_COLADDR_MAP_2_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CRC_ERROR_CLEAR_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CS_TO_CMDADDR_LATENCY_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CTRLR_BUSY_ENABLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CTRLR_BUSY_RESTART_HOLDOFF_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CTRLR_BUSY_SEL_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CTRLR_BUSY_TURN_OFF_DELAY_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CTRLR_BUSY_VALUE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CTRLR_INIT_DISABLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CTRLUPD_START_DELAY_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CTRLUPD_TRIG_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_CWL_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DATA_MASK_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DATA_SEL_FIRST_ERROR_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DATA_SEL_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DBI_CL_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DFI_DATA_BYTE_DISABLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DFI_LVL_PATTERN_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DFI_LVL_PERIODIC_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DFI_LVL_SEL_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DFI_PHYUPD_EN_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DFI_T_CTRLUPD_MAX_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DFI_T_CTRL_DELAY_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DFI_T_DRAM_CLK_ENABLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DFI_T_PHY_RDLAT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DFI_T_PHY_WRLAT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DFI_T_RDDATA_EN_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DLL_DISABLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DM_EN_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DQ_ODT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DQ_WIDTH_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_DS_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_EARLY_RANK_TO_RD_START_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_EARLY_RANK_TO_WR_START_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ECC_1BIT_INT_THRESH_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ECC_BYPASS_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ECC_CORRECTION_EN_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_EMR3_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ENABLE_BUS_HOLD_AXI1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ENABLE_BUS_HOLD_AXI2_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_EN_MASK_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ERROR_GROUP_SEL_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_FAW_DLR_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_FAW_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_FINE_GRAN_REF_MODE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_GEARDOWN_MODE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_GENERATE_REFRESH_ON_SRX_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_IDLE_TIME_TO_POWER_DOWN_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_IDLE_TIME_TO_SELF_REFRESH_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_INIT_DURATION_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_INTRAPORT_REORDER_EN_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_INT_VREF_MON_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_LOOKAHEAD_ACT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_LOOKAHEAD_PCH_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_LPDDR4_FSP_OP_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_LP_ASR_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_LRDIMM_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MAINTAIN_COHERENCY_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MANUAL_ADDRESS_MAP_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MAX_PWR_DOWN_MODE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MB_AUTOPCH_COL_BIT_POS_HIGH_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MB_AUTOPCH_COL_BIT_POS_LOW_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MEMORY_TYPE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MEM_BANKBITS_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MEM_COLBITS_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MEM_ROWBITS_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MEM_START_ADDRESS_AXI1_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MEM_START_ADDRESS_AXI1_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MEM_START_ADDRESS_AXI2_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MEM_START_ADDRESS_AXI2_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MIN_READ_IDLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MIRROR_X16_BG0_BG1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MOD_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MPR_READ_FORMAT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MRD_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MRRI_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MRR_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_MRW_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_NIBBLE_DEVICES_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_NON_DBI_CL_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_NUM_CAL_READS_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_NUM_LOGICAL_RANKS_PER_3DS_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_NUM_RANKS_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODTD_CA_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODTE_CK_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODTE_CS_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_INBUF_4_PD_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_POWERDOWN_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_RD_MAP_CS0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_RD_MAP_CS1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_RD_MAP_CS2_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_RD_MAP_CS3_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_RD_MAP_CS4_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_RD_MAP_CS5_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_RD_MAP_CS6_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_RD_MAP_CS7_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_RD_TURN_OFF_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_RD_TURN_ON_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_WR_MAP_CS0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_WR_MAP_CS1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_WR_MAP_CS2_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_WR_MAP_CS3_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_WR_MAP_CS4_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_WR_MAP_CS5_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_WR_MAP_CS6_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_WR_MAP_CS7_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_WR_TURN_OFF_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ODT_WR_TURN_ON_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ONLY_SRANK_CMDS_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_PARITY_RDIMM_DELAY_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_PASR_BANK_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_PASR_SEG_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_PASR_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_PER_DRAM_ADDR_EN_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_PHYUPD_ACK_DELAY_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_POST_TRIG_CYCS_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_PRE_TRIG_CYCS_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_PU_CAL_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_QOFF_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_QUAD_RANK_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_Q_AGE_LIMIT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RAS_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RCD_STAB_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RCD_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RC_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RDIMM_BSIDE_INVERT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RDIMM_LAT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RD_POSTAMBLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RD_PREAMBLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RD_PREAMB_TOGGLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RD_PREAMB_TRN_MODE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_READ_DBI_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_READ_TO_READ_ODT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_READ_TO_READ_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_READ_TO_WRITE_ODT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_READ_TO_WRITE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_REFRESH_DURING_PHY_TRAINING_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_REF_PER_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_REGDIMM_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_REORDER_EN_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_REORDER_QUEUE_EN_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_REORDER_RW_ONLY_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RFC1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RFC2_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RFC4_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RFC_DLR1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RFC_DLR2_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RFC_DLR4_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RFC_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RL_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RMW_EN_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ROWADDR_MAP_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ROWADDR_MAP_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ROWADDR_MAP_2_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ROWADDR_MAP_3_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RO_CLOSED_PAGE_POLICY_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RO_PRIORITY_EN_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RP_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RRD_DLR_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RRD_L_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RRD_S_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RRD_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RTP_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RTT_PARK_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RTT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_RTT_WR_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_SOC_ODT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_SRT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_SR_ABORT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_STARTUP_DELAY_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_STARVE_TIMEOUT_P0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_STARVE_TIMEOUT_P1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_STARVE_TIMEOUT_P2_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_STARVE_TIMEOUT_P3_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_STARVE_TIMEOUT_P4_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_STARVE_TIMEOUT_P5_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_STARVE_TIMEOUT_P6_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_STARVE_TIMEOUT_P7_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_TDQS_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_TEMP_CTRL_REF_MODE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_TEMP_CTRL_REF_RANGE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_TEMP_SENSOR_READOUT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_THERMAL_OFFSET_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_TRIG_ERR_MASK_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_TRIG_ERR_MASK_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_TRIG_ERR_MASK_2_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_TRIG_ERR_MASK_3_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_TRIG_ERR_MASK_4_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_TRIG_MASK_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_TRIG_MODE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_TRIG_MT_ADDR_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_TRIG_MT_ADDR_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_TWO_T_SEL_CYCLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_TWO_T_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_VRCG_DISABLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_VRCG_ENABLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_VREFDQ_TRN_ENABLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_VREFDQ_TRN_RANGE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_VREFDQ_TRN_VALUE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WL_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WRITE_CRC_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WRITE_DBI_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WRITE_LATENCY_SET_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WRITE_TO_READ_ODT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WRITE_TO_READ_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WRITE_TO_WRITE_ODT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WRITE_TO_WRITE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WR_CMD_LAT_CRC_DM_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WR_CRC_DM_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WR_POSTAMBLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WR_PREAMBLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WR_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WTR_L_CRC_DM_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WTR_L_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WTR_S_CRC_DM_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WTR_S_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_WTR_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_XPR_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_XP_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_XSDLL_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_XSR_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_XS_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ZQINIT_CAL_DURATION_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ZQLATCH_DURATION_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ZQ_CAL_DURATION_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ZQ_CAL_L_DURATION_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ZQ_CAL_PER_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ZQ_CAL_R_DURATION_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ZQ_CAL_S_DURATION_TypeDef__bindgen_ty_1 DDR_CSR_APB_CFG_ZQ_CAL_TYPE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CTRLR_INIT_DONE_TypeDef__bindgen_ty_1 DDR_CSR_APB_CTRLR_INIT_TypeDef__bindgen_ty_1 DDR_CSR_APB_CTRLR_READY_TypeDef__bindgen_ty_1 DDR_CSR_APB_CTRLR_SOFT_RESET_N_TypeDef__bindgen_ty_1 DDR_CSR_APB_DFI_TypeDef DDR_CSR_APB_DYN_WIDTH_ADJ_TypeDef DDR_CSR_APB_ECC_TypeDef DDR_CSR_APB_INIT_ACK_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_AUTOINIT_DISABLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_CAL_L_ADDR_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_CAL_L_ADDR_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_CAL_L_B_SIZE_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_CAL_L_READ_COMPLETE_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_CAL_L_R_ACK_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_CAL_L_R_REQ_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_CAL_SELECT_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_CA_PARITY_ERROR_GEN_ACK_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_CA_PARITY_ERROR_GEN_CMD_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_CA_PARITY_ERROR_GEN_REQ_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_CS_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_DFI_DRAM_CLK_DISABLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_DFI_LP_CTRL_REQ_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_DFI_LP_DATA_REQ_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_DFI_LP_WAKEUP_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_DISABLE_CKE_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_FORCE_RESET_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_FORCE_WRITE_CS_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_FORCE_WRITE_DATA_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_FORCE_WRITE_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_GEARDOWN_EN_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_MEMORY_RESET_MASK_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_MRR_MODE_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_MR_ADDR_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_MR_WR_DATA_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_MR_WR_MASK_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_MR_W_REQ_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_NOP_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_ODT_FORCE_EN_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_ODT_FORCE_RANK_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_PDA_MR_W_REQ_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_PDA_NIBBLE_SELECT_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_POWER_DOWN_STATUS_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_POWER_DOWN_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_PRECHARGE_ALL_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_RDIMM_COMPLETE_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_RDIMM_READY_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_RD_DQCAL_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_READ_CAPTURE_ADDR_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_READ_CAPTURE_DATA_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_READ_CAPTURE_DATA_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_READ_CAPTURE_DATA_2_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_READ_CAPTURE_DATA_3_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_READ_CAPTURE_DATA_4_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_REFRESH_COUNT_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_REFRESH_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_RWFIFO_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_SELF_REFRESH_STATUS_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_SELF_REFRESH_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_START_DQSOSC_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_STOP_DQSOSC_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_WRITE_DATA_1B_ECC_ERROR_GEN_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_WRITE_DATA_2B_ECC_ERROR_GEN_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_ZQ_CAL_REQ_TypeDef__bindgen_ty_1 DDR_CSR_APB_INIT_ZQ_CAL_START_TypeDef__bindgen_ty_1 DDR_CSR_APB_MC_BASE1_TypeDef DDR_CSR_APB_MC_BASE2_TypeDef DDR_CSR_APB_MC_BASE3_TypeDef DDR_CSR_APB_MEM_TEST_TypeDef DDR_CSR_APB_MPFE_TypeDef DDR_CSR_APB_MTA_TypeDef DDR_CSR_APB_MTC_ACK_TypeDef__bindgen_ty_1 DDR_CSR_APB_MTC_ACQ_ADDR_TypeDef__bindgen_ty_1 DDR_CSR_APB_MTC_ACQ_CYCS_STORED_TypeDef__bindgen_ty_1 DDR_CSR_APB_MTC_ACQ_ERROR_CNT_OVFL_TypeDef__bindgen_ty_1 DDR_CSR_APB_MTC_ACQ_ERROR_CNT_TypeDef__bindgen_ty_1 DDR_CSR_APB_MTC_ACQ_MEM_LAST_ADDR_TypeDef__bindgen_ty_1 DDR_CSR_APB_MTC_ACQ_MEM_TRIG_ADDR_TypeDef__bindgen_ty_1 DDR_CSR_APB_MTC_ACQ_RD_DATA_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_MTC_ACQ_RD_DATA_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_MTC_ACQ_RD_DATA_2_TypeDef__bindgen_ty_1 DDR_CSR_APB_MTC_ACQ_TRIG_DETECT_TypeDef__bindgen_ty_1 DDR_CSR_APB_MTC_ACQ_WR_DATA_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_MTC_ACQ_WR_DATA_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_MTC_ACQ_WR_DATA_2_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_ADDR_BITS_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_ADDR_PATTERN_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_ALG_AUTO_PCH_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_DATA_INVERT_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_DATA_PATTERN_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_DONE_ACK_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_EN_SINGLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_EN_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_ERROR_MASK_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_ERROR_MASK_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_ERROR_MASK_2_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_ERROR_MASK_3_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_ERROR_MASK_4_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_ERROR_STS_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_RD_ONLY_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_START_ADDR_0_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_START_ADDR_1_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_STOP_ON_ERROR_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_USER_DATA_PATTERN_TypeDef__bindgen_ty_1 DDR_CSR_APB_MT_WR_ONLY_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_CLR_DFI_LVL_PERIODIC_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_DFI_INIT_START_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_ENCODED_QUAD_CS_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_EYE_PAT_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_EYE_TRAIN_DELAY_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_GATE_TRAIN_DELAY_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_HALF_CLK_DLY_ENABLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_INDPNDT_TRAINING_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_LPDDR_DQ_CAL_PAT_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_PC_RANK_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_RANKS_TO_TRAIN_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_READ_REQUEST_DONE_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_READ_REQUEST_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_RESET_CONTROL_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_START_RECAL_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_TRAIN_STEP_ENABLE_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_WRITE_LEVEL_DELAY_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_WRITE_REQUEST_DONE_TypeDef__bindgen_ty_1 DDR_CSR_APB_PHY_WRITE_REQUEST_TypeDef__bindgen_ty_1 DDR_CSR_APB_READ_CAPT_TypeDef DDR_CSR_APB_REORDER_TypeDef DDR_CSR_APB_RMW_TypeDef DDR_CSR_APB_STAT_CA_PARITY_ERROR_TypeDef__bindgen_ty_1 DDR_CSR_APB_STAT_DFI_ERROR_INFO_TypeDef__bindgen_ty_1 DDR_CSR_APB_STAT_DFI_ERROR_TypeDef__bindgen_ty_1 DDR_CSR_APB_STAT_DFI_INIT_COMPLETE_TypeDef__bindgen_ty_1 DDR_CSR_APB_STAT_DFI_LP_ACK_TypeDef__bindgen_ty_1 DDR_CSR_APB_STAT_DFI_TRAINING_COMPLETE_TypeDef__bindgen_ty_1 DDR_CSR_APB_STAT_DFI_TRAINING_ERROR_TypeDef__bindgen_ty_1 DDR_CSR_APB_STAT_INT_ECC_1BIT_THRESH_TypeDef__bindgen_ty_1 DDR_CSR_APB_TypeDef DDR_CSR_APB_csr_custom_TypeDef GPIO_TypeDef HLS_DATA_ HSS_MSSIO_Bank_Config_ \brief Bank 2 and 4 voltage settings I2C_TypeDef IOMUX_CONFIG_ \brief IOMUX configuration IOSCBCFG_CONTROL__1_TypeDef__bindgen_ty_1 IOSCBCFG_STATUS_TypeDef__bindgen_ty_1 IOSCBCFG_TIMER_TypeDef__bindgen_ty_1 IOSCBCFG_TypeDef IOSCB_BANKCONT_DDR_ \brief dll sgmii SCB regs IOSCB_BANK_CNTL_SGMII_ \brief bank control sgmii SCB regs IOSCB_CFM_MSS IOSCB_CFM_SGMII IOSCB_DLL_SGMII_ \brief dll sgmii SCB regs IOSCB_GEM_X_LO_STRUCT_ \brief GEM_A_LO GEM_B_LO IOSCB_IO_CALIB_STRUCT IRQ_Target_Type M2F_CONTROLLER_Type MAC_TypeDef MPU_CFG MPU_CFG__bindgen_ty_1__bindgen_ty_1 MPU_FailStatus_TypeDef MPU_TypeDef MSSIO_Bank2_IO_Config_ \brief MSS IO Bank 2 configuration MSSIO_Bank4_IO_Config_ \brief MSS IO Bank 4 configuration MSS_UART_TypeDef MSS_USB_TypeDef PATTERN_TEST_PARAMS_ PCIESS_MAIN_TypeDef PCIE_BRIDGE_TypeDef PCIE_CTRL_TypeDef PCIE_END_CONF_TypeDef PCIE_ROOT_CONF_TypeDef PCS_CMN_TypeDef PCS_LANE_TypeDef PLIC_Type PLL_TypeDef PMA_LANE_TypeDef QSPI_TypeDef //**
These are register map of the PolarFire SoC MSS QSPI driver. SCBCTRL_TypeDef SGMIIPHY_LANE01_ \brief gmiiphy_lanexx TIMER_TypeDef TXPLL_SSC_TypeDef TXPLL_TypeDef Target_Enables_Type USB_DMA_channel USB_endpoint_regs_t USB_fifo_t__bindgen_ty_1 USB_fifo_t__bindgen_ty_2 USB_fifo_t__bindgen_ty_3 USB_indexed_csr_t__bindgen_ty_1 USB_indexed_csr_t__bindgen_ty_2 USB_indexed_csr_t__bindgen_ty_3 USB_indexed_csr_t__bindgen_ty_4 USB_tar_t WATCHDOG_TypeDef //**
The WATCHDOG_TypeDef is the hardware register structure for the PolarFire SoC
MSS Watchdog. _CAN_filterobject _CAN_filterobject__bindgen_ty_1__bindgen_ty_1 _CAN_filterobject__bindgen_ty_2__bindgen_ty_1 _CAN_filterobject__bindgen_ty_3__bindgen_ty_1 _CAN_txmsgobject _CAN_txmsgobject__bindgen_ty_2 _CAN_txmsgobject__bindgen_ty_1__bindgen_ty_1 _CAN_txmsgobject__bindgen_ty_3__bindgen_ty_1 __BindgenBitfieldUnit __gpio_instance_t Structure instance holding all data regarding the CoreGPIO __mss_mac_cfg_t //**
PolarFire SoC MSS Ethernet MAC Configuration Structure. _cfmChannelMode _cfmRegs _mss_can_msgobject _mss_can_msgobject__bindgen_ty_1 _mss_can_msgobject__bindgen_ty_2__bindgen_ty_1 _mss_can_msgobject__bindgen_ty_3__bindgen_ty_1 _mss_can_rxmsgobject _mss_can_rxmsgobject__bindgen_ty_2 _mss_can_rxmsgobject__bindgen_ty_1__bindgen_ty_1 _mss_can_rxmsgobject__bindgen_ty_3__bindgen_ty_1 _mss_can_rxmsgobject__bindgen_ty_4__bindgen_ty_1 _mss_can_rxmsgobject__bindgen_ty_5__bindgen_ty_1 _mss_sysreg TOP LEVEL REGISTER STRUCTURE*************************** _pdmachannelconfig The mss_pdma_channel_config_t structure is used to configure the desired
Platform DMA channel. PDMA channel configuration includes configuration of
source, destination address and the number of bytes for the DMA transfer.
Single DMA transfer may require multiple DMA transactions, the size and
alignment of the individual DMA transaction can be forced. The PDMA can be
programmed to automatically repeat a transfer.
The MSS PDMA have two interrupts per channel, transfer complete interrupt and
transfer error interrupt. The two interrupts can be enabled by configuring
respective bits in the mss_pdma_channel_config_t structure. _pdmaregs The mss_pdma_t structure will describe the functionality of the memory mapped
registers in the Platform DMA Engine. buffer_status can_config_reg__bindgen_ty_1 can_instance The structure mss_can_instance_t is used by the driver to manage the
configuration and operation of each MSS CAN peripheral. The instance content
should only be accessed by using the respective API functions. command_reg__bindgen_ty_1 def_conf_desc_t The def_conf_desc_t provides the prototype of the structure for the standard
USB configuration descriptor. All the parameters of this structure are as per
the standard setup packet defined in the USB2.0 specification. dev_desc_t The dev_desc_t provides the prototype of the structure for the standard USB
device descriptor. All the parameters of this structure are as per the
standard setup packet defined in the USB2.0 specification. eMAC_TypeDef error_status__bindgen_ty_1 g5_mss_top_scb_regs_ATHENA_CR_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_AXI_CONTROL_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_AXI_RADDR_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_AXI_RDATA_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_AXI_RSETUP_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_AXI_STATUS_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_AXI_WADDR_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_AXI_WDATA_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_AXI_WSETUP_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_BIST_COMMAND_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_BIST_CONFIG_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_BIST_DATA_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_BOOT_ADDR0_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_BOOT_ADDR1_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_BOOT_ADDR2_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_BOOT_ADDR3_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_BOOT_ADDR4_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_BOOT_ROM0_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_BOOT_ROM1_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_BOOT_ROM2_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_BOOT_ROM3_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_BOOT_ROM4_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_BOOT_ROM5_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_BOOT_ROM6_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_BOOT_ROM7_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DEVICE_CONFIG_CR_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DEVICE_ID_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DEVRST_INT_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL0_CTRL0_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL0_CTRL1_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL0_STAT0_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL0_STAT1_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL0_STAT2_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL0_TEST_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL1_CTRL0_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL1_CTRL1_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL1_STAT0_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL1_STAT1_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL1_STAT2_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL1_TEST_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL2_CTRL0_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL2_CTRL1_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL2_STAT0_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL2_STAT1_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL2_STAT2_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL2_TEST_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL3_CTRL0_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL3_CTRL1_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL3_STAT0_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL3_STAT1_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL3_STAT2_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_DLL3_TEST_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_ENVM_CR_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_ENVM_POWER_CR_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_FLASH_FREEZE_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_G5CIO_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_MESSAGE_INT_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_MESSAGE_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_MSSIO_BANK2_CFG_CR_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_MSSIO_BANK4_CFG_CR_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_MSSIO_CONTROL_CR_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_MSSIO_VB2_CFG_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_MSSIO_VB4_CFG_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_MSS_INTERRUPT_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_MSS_IO_LOCKDOWN_CR_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_MSS_RESET_CR_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_MSS_STATUS_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_RAM_MARGIN_CR_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_RAM_SHUTDOWN_CR_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_REDUNDANCY_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_SCB_INTERRUPT_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_SOFT_RESET_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_TRACE_CR_TypeDef__bindgen_ty_1 g5_mss_top_scb_regs_TypeDef hls_t int_enable__bindgen_ty_1 int_status__bindgen_ty_1 max_align_t mss_ddr_calibration_ //**
Calibration settings derived during write training mss_ddr_diags_ //** mss_ddr_fpga_vref_ //** mss_ddr_write_calibration_ //** mss_i2c_instance mss_i2c_instance_t mss_lpddr4_dq_calibration_ //** mss_mac_instance //**
G5SoC Ethernet MAC instance
A local record of this type will be created and maintained by the driver for
each pMAC and eMAC. mss_mac_mmsl_config mss_mac_mmsl_stats mss_mac_queue //**
Per queue specific info for device management structure. mss_mac_rx_desc mss_mac_tsu_config mss_mac_tsu_time mss_mac_tx_desc mss_mac_tx_pkt_info mss_mac_type_1_filter mss_mac_type_2_compare mss_mac_type_2_filter mss_mmc_cfg The mss_mmc_cfg_t type provides the prototype for the configuration values of
the MSS eMMC SD driver. The application need to create a record of this type
to hold the configuration of the eMMC/SD/SDIO. The MSS_MMC_init() function
initializes the MSS eMMC SD using this structure. A pointer to an initialized
of this structure should be passed as the first parameter to the
MSS_MMC_init() function. mss_qspi_config //**
This is the structure definition for the MSS QSPI configuration instance. It
defines the configuration data that the application exchanges with the driver. mss_uart_instance / /**
mss_uart_instance.
There is one instance of this structure for each instance of the
microprocessor subsystemโs UARTs. Instances of this structure are used to
identify a specific UART. A pointer to an initialized instance of the
mss_uart_instance_t structure is passed as the first parameter to
MSS UART driver functions to identify which UART should perform the
requested operation. mss_usb_core_info_t mss_usb_dma_t mss_usb_ep_t Data structures of USB-CIFL which are shared with USB-LL. mss_usbd_cb_t mss_usbd_dev_conf_t Data structures which are used internally by the driver. mss_usbh_cb_t mss_usbh_class_cb The mss_usbh_class_cb_t provides the prototype of the structure that must be
implemented by the USBH-Class driver to provide the call-back functions which
will be called by the USBH driver to communicate events on the target device. mss_usbh_target_info The mss_usbh_tdev_info_t type provides the prototype for the detailed
information of the attached device. Some of the parameters are only applicable
when multi-point support is enabled on MSS USB. Multi-point support is
currently not enabled in the USBH driver. mss_usbh_user_cb The mss_usbh_user_cb_t provides the prototype of the structure that must be
implemented by the application to provide the call-back functions which will
be called by the USBH driver to communicate events on the target device. These
call-back functions can be used by the application to know the USBH driver
state and information about the attached device from the USBH driver.
These events are not specific to any USB class. mss_watchdog_config //**
The mss_watchdog_config_t type is for the watchdog configuration structure.
This type is used as a parameter for the MSS_WD_configure() and the
MSS_WD_get_config() functions. pf_pcie_bar_info_t The pf_pcie_bar_info_t structure contains information about the memory
allocated on the host processor for the PCIe endpoint. It is used in the
PF_PCIE_allocate_memory() function. pf_pcie_ebuff_t The pf_pcie_ebuff_t structure is used in PCIe enumeration process to store
the number of bridges and devices attached to the PCIe root port. The
PF_PCIE_enumeration() function returns this structure to the application
during PCIe enumeration. pf_pcie_info_t The pf_pcie_info_t structure contains the PCIe system(device or bridge) vendor id,
bus, device and function number. pf_pcie_master_atr_cfg_t PCIe AXI4 Master ATR table configuration structure.
The user must create a record of the pf_pcie_master_atr_cfg_t type to hold
the configuration of the PCIe AXI4 master ATR table. The
PF_PCIE_master_atr_table_init() function is used to create this configuration
record by entering the desired values. pf_pcie_slave_atr_cfg_t PCIe AXI4 Slave ATR table configuration structure.
The user must create a record of the pf_pcie_slave_atr_cfg_t type to hold the
configuration of the PCIe AXI4 slave ATR table. The PF_PCIE_slave_atr_table_init()
function is used to craete this configuration record by entering the desired values. seg_t seg_t__bindgen_ty_1__bindgen_ty_1 sweep_index_ //**
sweep indexโs ABNORMAL_RETRAIN_CA_DECREASE_COUNT ABNORMAL_RETRAIN_CA_DLY_DECREASE_COUNT ADDCMD_BIT ADDRESS_CMD_OFFSETT_MASK ADD_CMD_INC_FREQ_DDR3 ADD_CMD_INC_FREQ_DDR4 ADD_CMD_INC_FREQ_DDR3L ADD_CMD_INC_FREQ_LPDDR3 ADD_CMD_INC_FREQ_LPDDR4 ADD_CMD_TRANS_A5_THRES_DDR3 ADD_CMD_TRANS_A5_THRES_DDR4 ADD_CMD_TRANS_A5_THRES_DDR3L ADD_CMD_TRANS_A5_THRES_LPDDR3 ADD_CMD_TRANS_A5_THRES_LPDDR4 ADD_ZLP_TO_XFR ADVERTISED_10baseT_Full ADVERTISED_10baseT_Half ADVERTISED_100baseT_Full ADVERTISED_100baseT_Half ADVERTISED_1000baseKX_Full ADVERTISED_1000baseT_Full ADVERTISED_1000baseT_Half ADVERTISED_2500baseX_Full ADVERTISED_10000baseKR_Full ADVERTISED_10000baseKX4_Full ADVERTISED_10000baseR_FEC ADVERTISED_10000baseT_Full ADVERTISED_AUI ADVERTISED_Asym_Pause ADVERTISED_Autoneg ADVERTISED_BNC ADVERTISED_Backplane ADVERTISED_FIBRE ADVERTISED_MII ADVERTISED_Pause ADVERTISED_TP ADVERTISE_10FULL ADVERTISE_10HALF ADVERTISE_100BASE4 ADVERTISE_100FULL ADVERTISE_100HALF ADVERTISE_1000FULL ADVERTISE_1000HALF ADVERTISE_1000XFULL ADVERTISE_1000XHALF ADVERTISE_1000XPAUSE ADVERTISE_1000XPSE_ASYM ADVERTISE_ALL ADVERTISE_CSMA ADVERTISE_FULL ADVERTISE_LPACK ADVERTISE_NPAGE ADVERTISE_PAUSE_ASYM ADVERTISE_PAUSE_CAP ADVERTISE_RESV ADVERTISE_RFAULT ADVERTISE_SLCT AHBAPB_CR_APB0_POSTED_MASK AHBAPB_CR_APB0_POSTED_OFFSET AHBAPB_CR_APB1_POSTED_MASK AHBAPB_CR_APB1_POSTED_OFFSET AHBAPB_CR_OFFSET AHBAXI_CR_ATHENA_RBCNT_MASK AHBAXI_CR_ATHENA_RBCNT_OFFSET AHBAXI_CR_ATHENA_WBCNT_MASK AHBAXI_CR_ATHENA_WBCNT_OFFSET AHBAXI_CR_OFFSET AHBAXI_CR_USB_RBCNT_MASK AHBAXI_CR_USB_RBCNT_OFFSET AHBAXI_CR_USB_WBCNT_MASK AHBAXI_CR_USB_WBCNT_OFFSET APBBUS_CR_CAN0_MASK APBBUS_CR_CAN0_OFFSET APBBUS_CR_CAN1_MASK APBBUS_CR_CAN1_OFFSET APBBUS_CR_GEM0_MASK APBBUS_CR_GEM0_OFFSET APBBUS_CR_GEM1_MASK APBBUS_CR_GEM1_OFFSET APBBUS_CR_GPIO0_MASK APBBUS_CR_GPIO0_OFFSET APBBUS_CR_GPIO1_MASK APBBUS_CR_GPIO1_OFFSET APBBUS_CR_GPIO2_MASK APBBUS_CR_GPIO2_OFFSET APBBUS_CR_I2C0_MASK APBBUS_CR_I2C0_OFFSET APBBUS_CR_I2C1_MASK APBBUS_CR_I2C1_OFFSET APBBUS_CR_M2FINT_MASK APBBUS_CR_M2FINT_OFFSET APBBUS_CR_MMUART0_MASK APBBUS_CR_MMUART0_OFFSET APBBUS_CR_MMUART1_MASK APBBUS_CR_MMUART1_OFFSET APBBUS_CR_MMUART2_MASK APBBUS_CR_MMUART2_OFFSET APBBUS_CR_MMUART3_MASK APBBUS_CR_MMUART3_OFFSET APBBUS_CR_MMUART4_MASK APBBUS_CR_MMUART4_OFFSET APBBUS_CR_OFFSET APBBUS_CR_RTC_MASK APBBUS_CR_RTC_OFFSET APBBUS_CR_SPI0_MASK APBBUS_CR_SPI0_OFFSET APBBUS_CR_SPI1_MASK APBBUS_CR_SPI1_OFFSET APBBUS_CR_TIMER_MASK APBBUS_CR_TIMER_OFFSET APBBUS_CR_WDOG0_MASK APBBUS_CR_WDOG0_OFFSET APBBUS_CR_WDOG1_MASK APBBUS_CR_WDOG1_OFFSET APBBUS_CR_WDOG2_MASK APBBUS_CR_WDOG2_OFFSET APBBUS_CR_WDOG3_MASK APBBUS_CR_WDOG3_OFFSET APBBUS_CR_WDOG4_MASK APBBUS_CR_WDOG4_OFFSET ARO_REF_PCODE_MASK ARO_REF_PCODE_REVC_THRESHOLD ASC_ADDRESS_OUT_OF_RANGE ASC_INVALID_CDB ASC_INVALID_FIELD_IN_PARAMETER_LIST ASC_INVALID_FIELED_IN_COMMAND ASC_MEDIUM_HAS_CHANGED ASC_MEDIUM_NOT_PRESENT ASC_PARAMETER_LIST_LENGTH_ERROR ASC_UNRECOVERED_READ_ERROR ASC_WRITE_FAULT ASC_WRITE_PROTECTED AXISW_CMD_CMD AXISW_CMD_CMD_MASK AXISW_CMD_EN AXISW_CMD_ERR AXISW_CMD_RW AXISW_CMD_RWCHAN AXISW_CMD_SWRST AXISW_DATA_BURSTI AXISW_DATA_BURSTI_MASK AXISW_DATA_PEAKRT AXISW_DATA_PEAKRT_MASK AXISW_DATA_QOSVAL AXISW_DATA_QOSVAL_MASK AXISW_DATA_XCTRT AXISW_DATA_XCTRT_MASK BABBLE_IRQ_MASK BASE32_ADDR_MSS_SYSREG BASE_ADDRESS_CACHED_32_DDR BASE_ADDRESS_CACHED_64_DDR BASE_ADDRESS_NON_CACHED_32_DDR BASE_ADDRESS_NON_CACHED_64_DDR BCLK_DPC_VRGEN_H_MASK BCLK_DPC_VRGEN_H_SHIFT BCLK_DPC_VRGEN_VS_MASK BCLK_DPC_VRGEN_VS_SHIFT BCLK_DPC_VRGEN_V_MASK BCLK_DPC_VRGEN_V_SHIFT BCLK_SCLK_BIT BCLK_SCLK_OFFSET_MASK BCLK_SCLK_OFFSET_SHIFT BEU_ENABLE BEU_LOCAL_INT BEU_PLIC_INT BEU_event_cause_BEU_EVENT_DATA_CACHE_CORRECTABLE BEU_event_cause_BEU_EVENT_DATA_CACHE_UNCORRECTABLE BEU_event_cause_BEU_EVENT_ITIM_CORRECTABLE BEU_event_cause_BEU_EVENT_ITIM_UNCORRECTABLE BEU_event_cause_BEU_EVENT_NO_ERROR BEU_event_cause_BEU_EVENT_RESERVED2 BEU_event_cause_BEU_EVENT_RESEVERD1 BEU_event_cause_BEU_EVENT_TILELINK_BUS_ERROR BEU_event_cause_MAX_BEU_CAUSES BMCR_ANENABLE BMCR_ANRESTART BMCR_CTST BMCR_FULLDPLX BMCR_ISOLATE BMCR_LOOPBACK BMCR_PDOWN BMCR_RESET BMCR_RESV BMCR_SPEED100 BMCR_SPEED1000 BMSR_10FULL BMSR_10HALF BMSR_100BASE4 BMSR_100FULL BMSR_100FULL2 BMSR_100HALF BMSR_100HALF2 BMSR_ANEGCAPABLE BMSR_ANEGCOMPLETE BMSR_ERCAP BMSR_ESTATEN BMSR_JCD BMSR_LSTATUS BMSR_RESV BMSR_RFAULT BOOT_FAIL_CR_BOOT_MASK BOOT_FAIL_CR_BOOT_OFFSET BOOT_FAIL_CR_OFFSET CACHE_BLOCK_BYTE_LENGTH CACHE_CTRL_BASE CAN_ARB_FIXED_PRIO CAN_ARB_ROUNDROBIN CAN_AUTO_RESTART CAN_BASIC_CAN_MAILBOX CAN_BIG_ENDIAN CAN_ERR CAN_INT_ACK_ERR CAN_INT_ARB_LOSS CAN_INT_BIT_ERR CAN_INT_BUS_OFF CAN_INT_CRC_ERR CAN_INT_FORM_ERR CAN_INT_GLOBAL CAN_INT_OVR_LOAD CAN_INT_RTR_MSG CAN_INT_RX_MSG CAN_INT_RX_MSG_LOST CAN_INT_SST_FAILURE CAN_INT_STUCK_AT_0 CAN_INT_STUFF_ERR CAN_INT_TX_MSG CAN_INVALID_MAILBOX CAN_LITTLE_ENDIAN CAN_NO_MSG CAN_NO_RTR_MAILBOX CAN_OK CAN_RX_BUFFER_EBL CAN_RX_INT_EBL CAN_RX_LINK_EBL CAN_RX_MAILBOX CAN_RX_MSGAV CAN_RX_RTRP CAN_RX_RTR_ABORT CAN_RX_RTR_REPLY_EBL CAN_RX_WPNH_EBL CAN_RX_WPNL_EBL CAN_SAMPLE_BOTH_EDGES CAN_SJW_TOO_BIG CAN_SPEED_MANUAL CAN_THREE_SAMPLES CAN_TSEG1_TOO_SMALL CAN_TSEG2_TOO_SMALL CAN_TX_ABORT CAN_TX_INT_EBL CAN_TX_MAILBOX CAN_TX_REQ CAN_TX_WPNH_EBL CAN_TX_WPNL_EBL CAN_VALID_MSG CAUSE_BREAKPOINT CAUSE_FETCH_ACCESS CAUSE_FETCH_PAGE_FAULT CAUSE_HYPERVISOR_ECALL CAUSE_ILLEGAL_INSTRUCTION CAUSE_LOAD_ACCESS CAUSE_LOAD_PAGE_FAULT CAUSE_MACHINE_ECALL CAUSE_MISALIGNED_FETCH CAUSE_MISALIGNED_LOAD CAUSE_MISALIGNED_STORE CAUSE_STORE_ACCESS CAUSE_STORE_PAGE_FAULT CAUSE_SUPERVISOR_ECALL CAUSE_USER_ECALL CA_SWEEP_END CA_SWEEP_INCREMENT CA_SWEEP_START CEP_MAX_PKT_SIZE CFG_DDR_SGMII_PHY_BASE CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_BLOCKID_BANK_CTRL_TypeDef_block_address_bank_ctrl CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_NV_MAP_BANK_CTRL_TypeDef_scb_nv_regs_not_in_soft_reset_bank_ctrl CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_NV_MAP_BANK_CTRL_TypeDef_scb_nv_regs_reset_bank_ctrl CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_PERIPH_BANK_CTRL_TypeDef_scb_periph_not_in_soft_reset_bank_ctrl CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_PERIPH_BANK_CTRL_TypeDef_scb_periph_reset_bank_ctrl CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_V_MAP_BANK_CTRL_TypeDef_scb_v_regs_not_in_soft_reset_bank_ctrl CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_V_MAP_BANK_CTRL_TypeDef_scb_v_regs_reset_bank_ctrl CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_BLOCKID_CFM_TypeDef_block_address_cfm CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_NV_MAP_CFM_TypeDef_scb_nv_regs_not_in_soft_reset_cfm CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_NV_MAP_CFM_TypeDef_scb_nv_regs_reset_cfm CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_PERIPH_CFM_TypeDef_scb_periph_not_in_soft_reset_cfm CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_PERIPH_CFM_TypeDef_scb_periph_reset_cfm CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_V_MAP_CFM_TypeDef_scb_v_regs_not_in_soft_reset_cfm CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_V_MAP_CFM_TypeDef_scb_v_regs_reset_cfm CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_NV_MAP_DDR_PHY_TypeDef_scb_nv_regs_not_in_soft_reset_ddr_phy CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_NV_MAP_DDR_PHY_TypeDef_scb_nv_regs_reset_ddr_phy CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_PERIPH_DDR_PHY_TypeDef_scb_periph_not_in_soft_reset_ddr_phy CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_PERIPH_DDR_PHY_TypeDef_scb_periph_reset_ddr_phy CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_V_MAP_DDR_PHY_TypeDef_scb_v_regs_not_in_soft_reset_ddr_phy CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_V_MAP_DDR_PHY_TypeDef_scb_v_regs_reset_ddr_phy CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_BLOCKID_DECODER_DRIVER_TypeDef_block_address_decoder_driver CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_NV_MAP_DECODER_DRIVER_TypeDef_scb_nv_regs_not_in_soft_reset_decoder_driver CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_NV_MAP_DECODER_DRIVER_TypeDef_scb_nv_regs_reset_decoder_driver CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_PERIPH_DECODER_DRIVER_TypeDef_scb_periph_not_in_soft_reset_decoder_driver CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_PERIPH_DECODER_DRIVER_TypeDef_scb_periph_reset_decoder_driver CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_V_MAP_DECODER_DRIVER_TypeDef_scb_v_regs_not_in_soft_reset_decoder_driver CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_V_MAP_DECODER_DRIVER_TypeDef_scb_v_regs_reset_decoder_driver CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_BLOCKID_DECODER_IO_TypeDef_block_address_decoder_io CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_NV_MAP_DECODER_IO_TypeDef_scb_nv_regs_not_in_soft_reset_decoder_io CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_NV_MAP_DECODER_IO_TypeDef_scb_nv_regs_reset_decoder_io CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_PERIPH_DECODER_IO_TypeDef_scb_periph_not_in_soft_reset_decoder_io CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_PERIPH_DECODER_IO_TypeDef_scb_periph_reset_decoder_io CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_V_MAP_DECODER_IO_TypeDef_scb_v_regs_not_in_soft_reset_decoder_io CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_V_MAP_DECODER_IO_TypeDef_scb_v_regs_reset_decoder_io CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_BLOCKID_DECODER_ODT_TypeDef_block_address_decoder_odt CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_NV_MAP_DECODER_ODT_TypeDef_scb_nv_regs_not_in_soft_reset_decoder_odt CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_NV_MAP_DECODER_ODT_TypeDef_scb_nv_regs_reset_decoder_odt CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_PERIPH_DECODER_ODT_TypeDef_scb_periph_not_in_soft_reset_decoder_odt CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_PERIPH_DECODER_ODT_TypeDef_scb_periph_reset_decoder_odt CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_V_MAP_DECODER_ODT_TypeDef_scb_v_regs_not_in_soft_reset_decoder_odt CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_V_MAP_DECODER_ODT_TypeDef_scb_v_regs_reset_decoder_odt CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_BLOCKID_IOCALIB_TypeDef_block_address_iocalib CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_NV_MAP_IOCALIB_TypeDef_scb_nv_regs_not_in_soft_reset_iocalib CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_NV_MAP_IOCALIB_TypeDef_scb_nv_regs_reset_iocalib CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_PERIPH_IOCALIB_TypeDef_scb_periph_not_in_soft_reset_iocalib CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_PERIPH_IOCALIB_TypeDef_scb_periph_reset_iocalib CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_V_MAP_IOCALIB_TypeDef_scb_v_regs_not_in_soft_reset_iocalib CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_V_MAP_IOCALIB_TypeDef_scb_v_regs_reset_iocalib CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_BLOCKID_IOSCB_PLL_TypeDef_block_address_ioscb_pll CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_NV_MAP_IOSCB_PLL_TypeDef_scb_nv_regs_not_in_soft_reset_ioscb_pll CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_NV_MAP_IOSCB_PLL_TypeDef_scb_nv_regs_reset_ioscb_pll CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_PERIPH_IOSCB_PLL_TypeDef_scb_periph_not_in_soft_reset_ioscb_pll CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_PERIPH_IOSCB_PLL_TypeDef_scb_periph_reset_ioscb_pll CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_V_MAP_IOSCB_PLL_TypeDef_scb_v_regs_not_in_soft_reset_ioscb_pll CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_V_MAP_IOSCB_PLL_TypeDef_scb_v_regs_reset_ioscb_pll CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_BLOCKID_MAIN_PLL_TypeDef_block_address_main_pll CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_NV_MAP_MAIN_PLL_TypeDef_scb_nv_regs_not_in_soft_reset_main_pll CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_NV_MAP_MAIN_PLL_TypeDef_scb_nv_regs_reset_main_pll CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_PERIPH_MAIN_PLL_TypeDef_scb_periph_not_in_soft_reset_main_pll CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_PERIPH_MAIN_PLL_TypeDef_scb_periph_reset_main_pll CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_V_MAP_MAIN_PLL_TypeDef_scb_v_regs_not_in_soft_reset_main_pll CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_V_MAP_MAIN_PLL_TypeDef_scb_v_regs_reset_main_pll CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_NV_MAP_TIP_TypeDef_scb_nv_regs_not_in_soft_reset_ddr_tip CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_NV_MAP_TIP_TypeDef_scb_nv_regs_reset_ddr_tip CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_PERIPH_TIP_TypeDef_scb_periph_not_in_soft_reset_ddr_tip CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_PERIPH_TIP_TypeDef_scb_periph_reset_ddr_tip CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_V_MAP_TIP_TypeDef_scb_v_regs_not_in_soft_reset_ddr_tip CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_V_MAP_TIP_TypeDef_scb_v_regs_reset_ddr_tip CFM_CH0_SHIFT_MASK CFM_CH1_SHIFT_MASK CFM_CH2_SHIFT_MASK CFM_CH3_SHIFT_MASK CFM_CH4_SHIFT_MASK CFM_CH5_SHIFT_MASK CFM_CH6_SHIFT_MASK CFM_CH7_SHIFT_MASK CFM_CHANNEL_MODE_MASK CFM_CLK_MONEN_MASK CFM_CLK_MONEN_SHIFT CFM_CLK_MONSEL_MASK CFM_CLK_MONSEL_SHIFT CFM_CLK_REFSEL0SHIFT CFM_CLK_REFSEL0_MASK CFM_CLK_REFSEL1SHIFT CFM_CLK_REFSEL1_MASK CFM_CLK_SEL_MASK CFM_CONTROL_REG_BUSY_MASK CFM_CONTROL_REG_START_MASK CFM_CONTROL_REG_STOP_BITS_SHIFT CFM_REG_BASE CFM_RUNTIME_REG_MASK CFM_TIMER_CR_ENABLE_MASK CFM_TIMER_CR_ENABLE_OFFSET CFM_TIMER_CR_OFFSET CLASS_DRIVER_NOT_FREE CLASS_DRIVER_NOT_MATCHED CLINT CLINT_BASE CLINT_SIZE CLOCK_CONFIG_CR_DIVIDER_MASK CLOCK_CONFIG_CR_DIVIDER_OFFSET CLOCK_CONFIG_CR_ENABLE_1MHZ_MASK CLOCK_CONFIG_CR_ENABLE_1MHZ_OFFSET CLOCK_CONFIG_CR_OFFSET CMD_SD_EMMC_DEMUX_EMMC_ON CMD_SD_EMMC_DEMUX_SD_ON CONFIG_LOCK_CR_LOCK_MASK CONFIG_LOCK_CR_LOCK_OFFSET CONFIG_LOCK_CR_OFFSET CONF_DESC_POWER_LIM_EXCEED CONF_DESC_WRONG_DESC_TYPE CONF_DESC_WRONG_LENGTH CONNECT_IRQ_MASK CONTEXT_EN_INDEX CONTEXT_EN_INDEX_FIC CONTEXT_EN_MASK_ATHENA CONTEXT_EN_MASK_CAN0 CONTEXT_EN_MASK_CAN1 CONTEXT_EN_MASK_CFM CONTEXT_EN_MASK_CRYPTO CONTEXT_EN_MASK_FIC0 CONTEXT_EN_MASK_FIC1 CONTEXT_EN_MASK_FIC2 CONTEXT_EN_MASK_FIC3 CONTEXT_EN_MASK_GPIO0 CONTEXT_EN_MASK_GPIO1 CONTEXT_EN_MASK_GPIO2 CONTEXT_EN_MASK_I2C0 CONTEXT_EN_MASK_I2C1 CONTEXT_EN_MASK_M2FINT CONTEXT_EN_MASK_MAC0 CONTEXT_EN_MASK_MAC1 CONTEXT_EN_MASK_MAILBOX_SC CONTEXT_EN_MASK_MMC CONTEXT_EN_MASK_MMUART0 CONTEXT_EN_MASK_MMUART1 CONTEXT_EN_MASK_MMUART2 CONTEXT_EN_MASK_MMUART3 CONTEXT_EN_MASK_MMUART4 CONTEXT_EN_MASK_QSPIXIP CONTEXT_EN_MASK_RTC CONTEXT_EN_MASK_SPI0 CONTEXT_EN_MASK_SPI1 CONTEXT_EN_MASK_TIMER CONTEXT_EN_MASK_TRACE CONTEXT_EN_MASK_USB CONTEXT_EN_MASK_WDOG0 CONTEXT_EN_MASK_WDOG1 CONTEXT_EN_MASK_WDOG2 CONTEXT_EN_MASK_WDOG3 CONTEXT_EN_MASK_WDOG4 CORE_LIBRARY CORE_NAME CORE_VENDOR CORE_VERSION COUNT0_REG_MASK CSR0H_DEV_FLUSH_FIFO_MASK CSR0H_HOST_DATA_TOG_MASK CSR0H_HOST_DATA_TOG_WE_MASK CSR0H_HOST_DISABLE_PING_MASK CSR0H_HOST_FLUSH_FIFO_MASK CSR0L_DEV_DATA_END_MASK CSR0L_DEV_RX_PKT_RDY_MASK CSR0L_DEV_SEND_STALL_MASK CSR0L_DEV_SERVICED_RX_PKT_RDY_MASK CSR0L_DEV_SERVICED_SETUP_END_MASK CSR0L_DEV_SETUP_END_MASK CSR0L_DEV_STALL_SENT_MASK CSR0L_DEV_TX_PKT_RDY_MASK CSR0L_HOST_IN_PKT_REQ_MASK CSR0L_HOST_NAK_TIMEOUT_MASK CSR0L_HOST_RETRY_ERR_MASK CSR0L_HOST_RX_PKT_RDY_MASK CSR0L_HOST_SETUP_PKT_MASK CSR0L_HOST_STALL_RCVD_MASK CSR0L_HOST_STATUS_PKT_MASK CSR0L_HOST_TX_PKT_RDY_MASK CSR_CYCLE CSR_CYCLEH CSR_DCSR CSR_DPC CSR_DSCRATCH CSR_FCSR CSR_FFLAGS CSR_FRM CSR_HPMCOUNTER3 CSR_HPMCOUNTER4 CSR_HPMCOUNTER5 CSR_HPMCOUNTER6 CSR_HPMCOUNTER7 CSR_HPMCOUNTER8 CSR_HPMCOUNTER9 CSR_HPMCOUNTER3H CSR_HPMCOUNTER4H CSR_HPMCOUNTER5H CSR_HPMCOUNTER6H CSR_HPMCOUNTER7H CSR_HPMCOUNTER8H CSR_HPMCOUNTER9H CSR_HPMCOUNTER10 CSR_HPMCOUNTER11 CSR_HPMCOUNTER12 CSR_HPMCOUNTER13 CSR_HPMCOUNTER14 CSR_HPMCOUNTER15 CSR_HPMCOUNTER16 CSR_HPMCOUNTER17 CSR_HPMCOUNTER18 CSR_HPMCOUNTER19 CSR_HPMCOUNTER20 CSR_HPMCOUNTER21 CSR_HPMCOUNTER22 CSR_HPMCOUNTER23 CSR_HPMCOUNTER24 CSR_HPMCOUNTER25 CSR_HPMCOUNTER26 CSR_HPMCOUNTER27 CSR_HPMCOUNTER28 CSR_HPMCOUNTER29 CSR_HPMCOUNTER30 CSR_HPMCOUNTER31 CSR_HPMCOUNTER10H CSR_HPMCOUNTER11H CSR_HPMCOUNTER12H CSR_HPMCOUNTER13H CSR_HPMCOUNTER14H CSR_HPMCOUNTER15H CSR_HPMCOUNTER16H CSR_HPMCOUNTER17H CSR_HPMCOUNTER18H CSR_HPMCOUNTER19H CSR_HPMCOUNTER20H CSR_HPMCOUNTER21H CSR_HPMCOUNTER22H CSR_HPMCOUNTER23H CSR_HPMCOUNTER24H CSR_HPMCOUNTER25H CSR_HPMCOUNTER26H CSR_HPMCOUNTER27H CSR_HPMCOUNTER28H CSR_HPMCOUNTER29H CSR_HPMCOUNTER30H CSR_HPMCOUNTER31H CSR_INSTRET CSR_INSTRETH CSR_MARCHID CSR_MBADADDR CSR_MCAUSE CSR_MCOUNTEREN CSR_MCYCLE CSR_MCYCLEH CSR_MEDELEG CSR_MEPC CSR_MHARTID CSR_MHPMCOUNTER3 CSR_MHPMCOUNTER4 CSR_MHPMCOUNTER5 CSR_MHPMCOUNTER6 CSR_MHPMCOUNTER7 CSR_MHPMCOUNTER8 CSR_MHPMCOUNTER9 CSR_MHPMCOUNTER3H CSR_MHPMCOUNTER4H CSR_MHPMCOUNTER5H CSR_MHPMCOUNTER6H CSR_MHPMCOUNTER7H CSR_MHPMCOUNTER8H CSR_MHPMCOUNTER9H CSR_MHPMCOUNTER10 CSR_MHPMCOUNTER11 CSR_MHPMCOUNTER12 CSR_MHPMCOUNTER13 CSR_MHPMCOUNTER14 CSR_MHPMCOUNTER15 CSR_MHPMCOUNTER16 CSR_MHPMCOUNTER17 CSR_MHPMCOUNTER18 CSR_MHPMCOUNTER19 CSR_MHPMCOUNTER20 CSR_MHPMCOUNTER21 CSR_MHPMCOUNTER22 CSR_MHPMCOUNTER23 CSR_MHPMCOUNTER24 CSR_MHPMCOUNTER25 CSR_MHPMCOUNTER26 CSR_MHPMCOUNTER27 CSR_MHPMCOUNTER28 CSR_MHPMCOUNTER29 CSR_MHPMCOUNTER30 CSR_MHPMCOUNTER31 CSR_MHPMCOUNTER10H CSR_MHPMCOUNTER11H CSR_MHPMCOUNTER12H CSR_MHPMCOUNTER13H CSR_MHPMCOUNTER14H CSR_MHPMCOUNTER15H CSR_MHPMCOUNTER16H CSR_MHPMCOUNTER17H CSR_MHPMCOUNTER18H CSR_MHPMCOUNTER19H CSR_MHPMCOUNTER20H CSR_MHPMCOUNTER21H CSR_MHPMCOUNTER22H CSR_MHPMCOUNTER23H CSR_MHPMCOUNTER24H CSR_MHPMCOUNTER25H CSR_MHPMCOUNTER26H CSR_MHPMCOUNTER27H CSR_MHPMCOUNTER28H CSR_MHPMCOUNTER29H CSR_MHPMCOUNTER30H CSR_MHPMCOUNTER31H CSR_MHPMEVENT3 CSR_MHPMEVENT4 CSR_MHPMEVENT5 CSR_MHPMEVENT6 CSR_MHPMEVENT7 CSR_MHPMEVENT8 CSR_MHPMEVENT9 CSR_MHPMEVENT10 CSR_MHPMEVENT11 CSR_MHPMEVENT12 CSR_MHPMEVENT13 CSR_MHPMEVENT14 CSR_MHPMEVENT15 CSR_MHPMEVENT16 CSR_MHPMEVENT17 CSR_MHPMEVENT18 CSR_MHPMEVENT19 CSR_MHPMEVENT20 CSR_MHPMEVENT21 CSR_MHPMEVENT22 CSR_MHPMEVENT23 CSR_MHPMEVENT24 CSR_MHPMEVENT25 CSR_MHPMEVENT26 CSR_MHPMEVENT27 CSR_MHPMEVENT28 CSR_MHPMEVENT29 CSR_MHPMEVENT30 CSR_MHPMEVENT31 CSR_MIDELEG CSR_MIE CSR_MIMPID CSR_MINSTRET CSR_MINSTRETH CSR_MIP CSR_MISA CSR_MSCRATCH CSR_MSTATUS CSR_MTVEC CSR_MVENDORID CSR_PMPADDR0 CSR_PMPADDR1 CSR_PMPADDR2 CSR_PMPADDR3 CSR_PMPADDR4 CSR_PMPADDR5 CSR_PMPADDR6 CSR_PMPADDR7 CSR_PMPADDR8 CSR_PMPADDR9 CSR_PMPADDR10 CSR_PMPADDR11 CSR_PMPADDR12 CSR_PMPADDR13 CSR_PMPADDR14 CSR_PMPADDR15 CSR_PMPCFG0 CSR_PMPCFG1 CSR_PMPCFG2 CSR_PMPCFG3 CSR_SBADADDR CSR_SCAUSE CSR_SCOUNTEREN CSR_SEPC CSR_SIE CSR_SIP CSR_SPTBR CSR_SSCRATCH CSR_SSTATUS CSR_STVEC CSR_TDATA1 CSR_TDATA2 CSR_TDATA3 CSR_TIME CSR_TIMEH CSR_TSELECT CTRL_CLKIDL CTRL_CLKIDL_MASK CTRL_CLKRATE CTRL_CLKRATE_MASK CTRL_EN CTRL_EN_MASK CTRL_EP_SETUP_END_ERROR CTRL_EP_STALL_ERROR CTRL_FLAGSX4 CTRL_FLAGSX4_MASK CTRL_QMODE0 CTRL_QMODE0_MASK CTRL_QMODE12 CTRL_QMODE12_MASK CTRL_SAMPLE CTRL_SAMPLE_HCLKF CTRL_SAMPLE_HCLKR CTRL_SAMPLE_MASK CTRL_SAMPLE_SCK CTRL_SW_RESET CTRL_SW_RESTART CTRL_XIP CTRL_XIPADDR CTRL_XIPADDR_MASK CTRL_XIP_MASK DCSR_CAUSE DCSR_CAUSE_DEBUGINT DCSR_CAUSE_HALT DCSR_CAUSE_HWBP DCSR_CAUSE_NONE DCSR_CAUSE_STEP DCSR_CAUSE_SWBP DCSR_DEBUGINT DCSR_EBREAKH DCSR_EBREAKM DCSR_EBREAKS DCSR_EBREAKU DCSR_FULLRESET DCSR_HALT DCSR_NDRESET DCSR_PRV DCSR_STEP DCSR_STOPCYCLE DCSR_STOPTIME DCSR_XDEBUGVER DDRCFG_BASE DDRPHY_MODE_BUS_WIDTH_4_LANE DDRPHY_MODE_BUS_WIDTH_MASK DDRPHY_MODE_ECC_MASK DDRPHY_MODE_ECC_ON DDRPHY_MODE_MASK DDRPHY_MODE_ONE_RANK DDRPHY_MODE_RANK_MASK DDRPHY_MODE_TWO_RANKS DDR_1067_MHZ DDR_1333_MHZ DDR_1600_MHZ DDR_ACCESS_SIZE__DDR_8_BIT DDR_ACCESS_SIZE__DDR_16_BIT DDR_ACCESS_SIZE__DDR_32_BIT DDR_ACCESS_SIZE__DDR_64_BIT DDR_ADD_CMD_A5_OFFSET_FAIL DDR_ADD_CMD_A5_OFFSET_FAIL_LOW_FREQ DDR_ADD_CMD_A5_OFFSET_PASS DDR_CALIBRATION_FAILED DDR_CALIBRATION_PASSED DDR_CALIBRATION_SUCCESS DDR_CAL_MAX_LATENCY DDR_CAL_MIN_LATENCY DDR_DPC_MOVE_EN_H_MASK DDR_DPC_MOVE_EN_H_SHIFT DDR_DPC_MOVE_EN_V_MASK DDR_DPC_MOVE_EN_V_SHIFT DDR_DPC_VRGEN_EN_H_MASK DDR_DPC_VRGEN_EN_H_SHIFT DDR_DPC_VRGEN_EN_V_MASK DDR_DPC_VRGEN_EN_V_SHIFT DDR_DPC_VRGEN_H_MASK DDR_DPC_VRGEN_H_SHIFT DDR_DPC_VRGEN_V_MASK DDR_DPC_VRGEN_V_SHIFT DDR_DPC_VS_MASK DDR_DPC_VS_SHIFT DDR_FILL_TYPE__DDR_INIT_FILL DDR_FILL_TYPE__DDR_TEST_FILL DDR_FREQ_MARGIN DDR_FULL_32BIT_CACHED_CHECK_EN DDR_FULL_32BIT_NC_CHECK_EN DDR_MEMORY_ACCESS__DDR_NC_2GB DDR_MEMORY_ACCESS__DDR_NC_256MB DDR_MEMORY_ACCESS__DDR_NC_WCB_2GB DDR_MEMORY_ACCESS__DDR_NC_WCB_256MB DDR_MODE_REG_VREF DDR_MODE_REG_VREF_VALUE DDR_SM_STATES__DDR_STATE_INIT < 0 DDR_STATE_INIT DDR_SM_STATES__DDR_STATE_MONITOR < 1 DDR_STATE_MONITOR DDR_SM_STATES__DDR_STATE_TRAINING < 2 DDR_STATE_TRAINING DDR_SM_STATES__DDR_STATE_VERIFY < 3 DDR_STATE_VERIFY DDR_SS_COMMAND__DDR_SS_MONITOR < 1 DDR_SS_MONITOR DDR_SS_COMMAND__DDR_SS__INIT < 0 DDR_SS__INIT DDR_SS_STATUS__DDR_SETUP_DONE < 0 DDR_SETUP_DONE DDR_SS_STATUS__DDR_SETUP_FAIL < 1 DDR_SETUP_FAIL DDR_SS_STATUS__DDR_SETUP_OFF_MODE < 4 DDR_SETUP_OFF_MODE DDR_SS_STATUS__DDR_SETUP_SUCCESS < 2 DDR_SETUP_SUCCESS DDR_TRAINING_SM__DDR_CHECK_TRAINING_SWEEP DDR_TRAINING_SM__DDR_FULL_32BIT_CACHE_CHECK DDR_TRAINING_SM__DDR_FULL_32BIT_NC_CHECK DDR_TRAINING_SM__DDR_FULL_32BIT_WRC_CHECK DDR_TRAINING_SM__DDR_FULL_64BIT_CACHE_CHECK DDR_TRAINING_SM__DDR_FULL_64BIT_NC_CHECK DDR_TRAINING_SM__DDR_FULL_64BIT_WRC_CHECK DDR_TRAINING_SM__DDR_FULL_MTC_CHECK DDR_TRAINING_SM__DDR_LOAD_PATTERN_TO_CACHE DDR_TRAINING_SM__DDR_LOAD_PATTERN_TO_CACHE_SETUP DDR_TRAINING_SM__DDR_MANUAL_ADDCMD_TRAINING_SW DDR_TRAINING_SM__DDR_SANITY_CHECKS DDR_TRAINING_SM__DDR_SWEEP_AGAIN DDR_TRAINING_SM__DDR_SWEEP_CHECK DDR_TRAINING_SM__DDR_TRAINING_CALIBRATE_IO DDR_TRAINING_SM__DDR_TRAINING_CHECK_FOR_OFFMODE < DDR_TRAINING_OFFMODE DDR_TRAINING_SM__DDR_TRAINING_CONFIG_PLL DDR_TRAINING_SM__DDR_TRAINING_CORRECT_RPC DDR_TRAINING_SM__DDR_TRAINING_FAIL DDR_TRAINING_SM__DDR_TRAINING_FAIL_32BIT_CACHE_CHECK DDR_TRAINING_SM__DDR_TRAINING_FAIL_BCLKSCLK_SW DDR_TRAINING_SM__DDR_TRAINING_FAIL_DDR_SANITY_CHECKS DDR_TRAINING_SM__DDR_TRAINING_FAIL_FULL_32BIT_NC_CHECK DDR_TRAINING_SM__DDR_TRAINING_FAIL_MIN_LATENCY DDR_TRAINING_SM__DDR_TRAINING_FAIL_PLL_LOCK DDR_TRAINING_SM__DDR_TRAINING_FAIL_SM2_VERIFY DDR_TRAINING_SM__DDR_TRAINING_FAIL_SM_ADDCMD DDR_TRAINING_SM__DDR_TRAINING_FAIL_SM_BCLKSCLK DDR_TRAINING_SM__DDR_TRAINING_FAIL_SM_DQ_DQS DDR_TRAINING_SM__DDR_TRAINING_FAIL_SM_RDGATE DDR_TRAINING_SM__DDR_TRAINING_FAIL_SM_VERIFY DDR_TRAINING_SM__DDR_TRAINING_FAIL_SM_WRLVL DDR_TRAINING_SM__DDR_TRAINING_FAIL_START_CHECK DDR_TRAINING_SM__DDR_TRAINING_FINISHED DDR_TRAINING_SM__DDR_TRAINING_FINISH_CHECK DDR_TRAINING_SM__DDR_TRAINING_FLASH_REGS DDR_TRAINING_SM__DDR_TRAINING_FPGA_VREFDQ_CALIB DDR_TRAINING_SM__DDR_TRAINING_INIT < DDR_TRAINING_INIT DDR_TRAINING_SM__DDR_TRAINING_INIT_ALL_MEMORY DDR_TRAINING_SM__DDR_TRAINING_IP_SM_ADDCMD DDR_TRAINING_SM__DDR_TRAINING_IP_SM_BCLKSCLK DDR_TRAINING_SM__DDR_TRAINING_IP_SM_BCLKSCLK_SW DDR_TRAINING_SM__DDR_TRAINING_IP_SM_DQ_DQS DDR_TRAINING_SM__DDR_TRAINING_IP_SM_RDGATE DDR_TRAINING_SM__DDR_TRAINING_IP_SM_START DDR_TRAINING_SM__DDR_TRAINING_IP_SM_START_CHECK DDR_TRAINING_SM__DDR_TRAINING_IP_SM_VERIFY DDR_TRAINING_SM__DDR_TRAINING_IP_SM_WRLVL DDR_TRAINING_SM__DDR_TRAINING_RESET DDR_TRAINING_SM__DDR_TRAINING_ROTATE_CLK DDR_TRAINING_SM__DDR_TRAINING_SETUP_DDRC DDR_TRAINING_SM__DDR_TRAINING_SETUP_SEGS DDR_TRAINING_SM__DDR_TRAINING_SET_FINAL_MODE DDR_TRAINING_SM__DDR_TRAINING_SET_MODE_VS_BITS DDR_TRAINING_SM__DDR_TRAINING_SET_TRAINING_PARAMETERS DDR_TRAINING_SM__DDR_TRAINING_SOFT_RESET DDR_TRAINING_SM__DDR_TRAINING_SWEEP DDR_TRAINING_SM__DDR_TRAINING_VERIFY_PLL_LOCK DDR_TRAINING_SM__DDR_TRAINING_VREFDQ_CALIB DDR_TRAINING_SM__DDR_TRAINING_WRITE_CALIBRATION DDR_TRAINING_SM__DDR_TRAINING_WRITE_CALIBRATION_RETRY < Retry on calibration fail DDR_TRAINING_SM__DDR_VERIFY_PATTERN_IN_CACHE DDR_TYPE__DDR3 < 0 DDR3 DDR_TYPE__DDR4 < 2 DDR4 DDR_TYPE__DDR3L < 1 DDR3L DDR_TYPE__DDR_OFF_MODE < 4 LPDDR4 DDR_TYPE__LPDDR3 < 3 LPDDR3 DDR_TYPE__LPDDR4 < 4 LPDDR4 DDR_USER_GET_COMMANDS_t_USR_CMD_GET_DDR_STATUS !< USR_CMD_GET_DDR_STATUS DDR_USER_GET_COMMANDS_t_USR_CMD_GET_GREEN_ZONE !< USR_CMD_GET_GREEN_ZONE DDR_USER_GET_COMMANDS_t_USR_CMD_GET_MODE_SETTING !< USR_CMD_GET_MODE_SETTING DDR_USER_GET_COMMANDS_t_USR_CMD_GET_REG !< USR_CMD_GET_REG DDR_USER_GET_COMMANDS_t_USR_CMD_GET_W_CALIBRATION !< USR_CMD_GET_W_CALIBRATION DDR_USER_SET_COMMANDS_t_USR_CMD_SET_GREEN_ZONE_DQ !< USR_CMD_SET_GREEN_ZONE_DQ DDR_USER_SET_COMMANDS_t_USR_CMD_SET_GREEN_ZONE_DQS !< USR_CMD_SET_GREEN_ZONE_DQS DDR_USER_SET_COMMANDS_t_USR_CMD_SET_GREEN_ZONE_VREF_MAX !< USR_CMD_SET_GREEN_ZONE_VREF DDR_USER_SET_COMMANDS_t_USR_CMD_SET_GREEN_ZONE_VREF_MIN !< USR_CMD_SET_GREEN_ZONE_VREF DDR_USER_SET_COMMANDS_t_USR_CMD_SET_REG !< USR_CMD_SET_REG DDR_USER_SET_COMMANDS_t_USR_CMD_SET_RETRAIN !< USR_CMD_SET_RETRAIN DEFAULT_ON_START_MASK DEFAULT_RPC_166_VALUE DEFAULT_RSTVEC DEVICE_BAR0 DEVICE_BAR1 DEVICE_BAR2 DEVICE_BAR3 DEVICE_BAR4 DEVICE_BAR5 DEVICE_BIST_HEADER DEVICE_CAPAB_LIST DEVICE_CAPAB_POINTER DEVICE_CFG_PRMSCR DEVICE_CLASS_CODE DEVICE_DEVICE2_CAPAB DEVICE_DEVICE2_CTRL_STAT DEVICE_DEVICE_CAPAB DEVICE_DEVICE_CTRL_STAT DEVICE_EXPAN_ROM DEVICE_EXPAN_ROM_BASE DEVICE_INT_LINE_PIN DEVICE_LINK2_CAPAB DEVICE_LINK2_CTRL_STAT DEVICE_LINK_CAPAB DEVICE_LINK_CTRL_STAT DEVICE_MSI_CAPAB_CTRL DEVICE_MSI_DATA DEVICE_MSI_LOWER_ADDRESS DEVICE_MSI_UPPER_ADDRESS DEVICE_MSI_X_CAPAB_CTRL DEVICE_MSI_X_PBA DEVICE_MSI_X_TABLE DEVICE_POWER_CTRL_STAT DEVICE_POWER_MNGM_CAPAB DEVICE_ROOT_CTRL DEVICE_ROOT_STAT DEVICE_SLOT2_CAPAB DEVICE_SLOT2_CTRL_STAT DEVICE_SLOT_CAPAB DEVICE_SLOT_CTRL_STAT DEVICE_STATUS_CORE_UP_MASK DEVICE_STATUS_CORE_UP_OFFSET DEVICE_STATUS_FF_IN_PROGRESS_MASK DEVICE_STATUS_FF_IN_PROGRESS_OFFSET DEVICE_STATUS_FLASH_VALID_MASK DEVICE_STATUS_FLASH_VALID_OFFSET DEVICE_STATUS_IO_BANK_B2_STATUS_MASK DEVICE_STATUS_IO_BANK_B2_STATUS_OFFSET DEVICE_STATUS_IO_BANK_B4_STATUS_MASK DEVICE_STATUS_IO_BANK_B4_STATUS_OFFSET DEVICE_STATUS_IO_BANK_B5_STATUS_MASK DEVICE_STATUS_IO_BANK_B5_STATUS_OFFSET DEVICE_STATUS_IO_BANK_B6_STATUS_MASK DEVICE_STATUS_IO_BANK_B6_STATUS_OFFSET DEVICE_STATUS_IO_EN_MASK DEVICE_STATUS_IO_EN_OFFSET DEVICE_STATUS_LP_STATE_MASK DEVICE_STATUS_LP_STATE_OFFSET DEVICE_STATUS_OFFSET DEVICE_SUBSYSTEM_ID DEVICE_VID_DEVID DEV_CTRL_B_DEVICE_MASK DEV_CTRL_FS_DEV_MASK DEV_CTRL_HOST_MODE_MASK DEV_CTRL_HOST_REQ_MASK DEV_CTRL_LS_DEV_MASK DEV_CTRL_SESSION_MASK DEV_CTRL_VBUS_MASK DEV_DESC_HS_MAXPKTSZ0_NOT64 DEV_DESC_HS_USBBCD_NOT200 DEV_DESC_LS_MAXPKTSZ0_NOT8 DEV_DESC_WRONG_DESC_TYPE DEV_DESC_WRONG_LENGTH DEV_DESC_WRONG_MAXPKTSZ0 DEV_DESC_WRONG_USBBCD DFIAPB_CR_CLOCKON_MASK DFIAPB_CR_CLOCKON_OFFSET DFIAPB_CR_OFFSET DFIAPB_CR_RESET_MASK DFIAPB_CR_RESET_OFFSET DIRECT_EN_SCLK DIRECT_EN_SCLK_MASK DIRECT_EN_SDO DIRECT_EN_SDO_MASK DIRECT_EN_SSEL DIRECT_EN_SSEL_MASK DIRECT_IDLE DIRECT_IDLE_MASK DIRECT_IP_SCLK DIRECT_IP_SCLK_MASK DIRECT_IP_SDI DIRECT_IP_SDI_MASK DIRECT_IP_SSEL DIRECT_IP_SSEL_MASK DIRECT_OP_SCLK DIRECT_OP_SCLK_MASK DIRECT_OP_SDO DIRECT_OP_SDOE DIRECT_OP_SDOE_MASK DIRECT_OP_SDO_MASK DIRECT_OP_SSEL DIRECT_OP_SSEL_MASK DIRECT_Reserved DIRECT_Reserved_MASK DISCONNECT_IRQ_MASK DLL_STATUS_CR_FIC0_LOCK_MASK DLL_STATUS_CR_FIC0_LOCK_OFFSET DLL_STATUS_CR_FIC0_UNLOCK_MASK DLL_STATUS_CR_FIC0_UNLOCK_OFFSET DLL_STATUS_CR_FIC1_LOCK_MASK DLL_STATUS_CR_FIC1_LOCK_OFFSET DLL_STATUS_CR_FIC1_UNLOCK_MASK DLL_STATUS_CR_FIC1_UNLOCK_OFFSET DLL_STATUS_CR_FIC2_LOCK_MASK DLL_STATUS_CR_FIC2_LOCK_OFFSET DLL_STATUS_CR_FIC2_UNLOCK_MASK DLL_STATUS_CR_FIC2_UNLOCK_OFFSET DLL_STATUS_CR_FIC3_LOCK_MASK DLL_STATUS_CR_FIC3_LOCK_OFFSET DLL_STATUS_CR_FIC3_UNLOCK_MASK DLL_STATUS_CR_FIC3_UNLOCK_OFFSET DLL_STATUS_CR_FIC4_LOCK_MASK DLL_STATUS_CR_FIC4_LOCK_OFFSET DLL_STATUS_CR_FIC4_UNLOCK_MASK DLL_STATUS_CR_FIC4_UNLOCK_OFFSET DLL_STATUS_CR_OFFSET DLL_STATUS_SR_FIC0_LOCK_MASK DLL_STATUS_SR_FIC0_LOCK_NOW_MASK DLL_STATUS_SR_FIC0_LOCK_NOW_OFFSET DLL_STATUS_SR_FIC0_LOCK_OFFSET DLL_STATUS_SR_FIC0_UNLOCK_MASK DLL_STATUS_SR_FIC0_UNLOCK_OFFSET DLL_STATUS_SR_FIC1_LOCK_MASK DLL_STATUS_SR_FIC1_LOCK_NOW_MASK DLL_STATUS_SR_FIC1_LOCK_NOW_OFFSET DLL_STATUS_SR_FIC1_LOCK_OFFSET DLL_STATUS_SR_FIC1_UNLOCK_MASK DLL_STATUS_SR_FIC1_UNLOCK_OFFSET DLL_STATUS_SR_FIC2_LOCK_MASK DLL_STATUS_SR_FIC2_LOCK_NOW_MASK DLL_STATUS_SR_FIC2_LOCK_NOW_OFFSET DLL_STATUS_SR_FIC2_LOCK_OFFSET DLL_STATUS_SR_FIC2_UNLOCK_MASK DLL_STATUS_SR_FIC2_UNLOCK_OFFSET DLL_STATUS_SR_FIC3_LOCK_MASK DLL_STATUS_SR_FIC3_LOCK_NOW_MASK DLL_STATUS_SR_FIC3_LOCK_NOW_OFFSET DLL_STATUS_SR_FIC3_LOCK_OFFSET DLL_STATUS_SR_FIC3_UNLOCK_MASK DLL_STATUS_SR_FIC3_UNLOCK_OFFSET DLL_STATUS_SR_FIC4_LOCK_MASK DLL_STATUS_SR_FIC4_LOCK_NOW_MASK DLL_STATUS_SR_FIC4_LOCK_NOW_OFFSET DLL_STATUS_SR_FIC4_LOCK_OFFSET DLL_STATUS_SR_FIC4_UNLOCK_MASK DLL_STATUS_SR_FIC4_UNLOCK_OFFSET DLL_STATUS_SR_OFFSET DMA_CNTL_REG_DMA_BURST_MODE_MASK DMA_CNTL_REG_DMA_BURST_MODE_SHIFT DMA_CNTL_REG_DMA_BUS_ERR_MASK DMA_CNTL_REG_DMA_DIR_MASK DMA_CNTL_REG_DMA_DIR_SHIFT DMA_CNTL_REG_DMA_EP_NUM_MASK DMA_CNTL_REG_DMA_EP_NUM_SHIFT DMA_CNTL_REG_DMA_MODE_MASK DMA_CNTL_REG_DMA_MODE_SHIFT DMA_CNTL_REG_ENABLE_DMA_IRQ_MASK DMA_CNTL_REG_START_XFR_MASK DMA_DISABLE DMA_ENABLE DMA_XFR_ERROR DMI_DBI_MASK DPB_DISABLE DPB_ENABLE DPC_VRGEN_H_DDR3_WR_LVL_VAL DPC_VRGEN_H_LPDDR4_WR_LVL_VAL DQ_DQS_BIT DQ_DQS_NUM_TAPS DRAM_BASE E51_ECC_CORRECT_INT_OFFSET E51_ECC_ERROR_INT_OFFSET E51_ENVM_INT_OFFSET E51_F2M_32_INT_OFFSET E51_F2M_33_INT_OFFSET E51_F2M_34_INT_OFFSET E51_F2M_35_INT_OFFSET E51_F2M_36_INT_OFFSET E51_F2M_37_INT_OFFSET E51_F2M_38_INT_OFFSET E51_F2M_39_INT_OFFSET E51_F2M_40_INT_OFFSET E51_F2M_41_INT_OFFSET E51_F2M_42_INT_OFFSET E51_F2M_43_INT_OFFSET E51_F2M_44_INT_OFFSET E51_F2M_45_INT_OFFSET E51_F2M_46_INT_OFFSET E51_F2M_47_INT_OFFSET E51_F2M_48_INT_OFFSET E51_F2M_49_INT_OFFSET E51_F2M_50_INT_OFFSET E51_F2M_51_INT_OFFSET E51_F2M_52_INT_OFFSET E51_F2M_53_INT_OFFSET E51_F2M_54_INT_OFFSET E51_F2M_55_INT_OFFSET E51_F2M_56_INT_OFFSET E51_F2M_57_INT_OFFSET E51_F2M_58_INT_OFFSET E51_F2M_59_INT_OFFSET E51_F2M_60_INT_OFFSET E51_F2M_61_INT_OFFSET E51_F2M_62_INT_OFFSET E51_F2M_63_INT_OFFSET E51_G5C_DEVRST_INT_OFFSET E51_G5C_MESSAGE_INT_OFFSET E51_MAINTENANCE_INT_OFFSET E51_MMUART0_INT_OFFSET E51_USOC_SMB_INTERRUPT_INT_OFFSET E51_USOC_VC_INTERRUPT_INT_OFFSET E51_WDOG0_MVRP_INT_OFFSET E51_WDOG0_TOUT_INT_OFFSET E51_WDOG1_TOUT_INT_OFFSET E51_WDOG2_TOUT_INT_OFFSET E51_WDOG3_TOUT_INT_OFFSET E51_WDOG4_TOUT_INT_OFFSET E51_scb_INTERRUPT_INT_OFFSET EARLY_EYE_WIDTH_PART_PART_NOT_DETERMINED EARLY_EYE_WIDTH_PART_REVC_OR_LATER EARLY_EYE_WIDTH_PART_REVC_OR_LATER_PRE_TEST EARLY_EYE_WIDTH_SS_PART_REVB EARLY_TT_PART_REVB ECC_CORRECT_E51_INT ECC_ERROR_E51_INT EDAC_CNT_CAN0_COUNT_MASK EDAC_CNT_CAN0_COUNT_OFFSET EDAC_CNT_CAN0_OFFSET EDAC_CNT_CAN1_COUNT_MASK EDAC_CNT_CAN1_COUNT_OFFSET EDAC_CNT_CAN1_OFFSET EDAC_CNT_DDRC_COUNT_MASK EDAC_CNT_DDRC_COUNT_OFFSET EDAC_CNT_DDRC_OFFSET EDAC_CNT_MAC0_COUNT_MASK EDAC_CNT_MAC0_COUNT_OFFSET EDAC_CNT_MAC0_OFFSET EDAC_CNT_MAC1_COUNT_MASK EDAC_CNT_MAC1_COUNT_OFFSET EDAC_CNT_MAC1_OFFSET EDAC_CNT_MMC_COUNT_MASK EDAC_CNT_MMC_COUNT_OFFSET EDAC_CNT_MMC_OFFSET EDAC_CNT_USB_COUNT_MASK EDAC_CNT_USB_COUNT_OFFSET EDAC_CNT_USB_OFFSET EDAC_INJECT_CR_CAN0_1E_MASK EDAC_INJECT_CR_CAN0_1E_OFFSET EDAC_INJECT_CR_CAN0_2E_MASK EDAC_INJECT_CR_CAN0_2E_OFFSET EDAC_INJECT_CR_CAN1_1E_MASK EDAC_INJECT_CR_CAN1_1E_OFFSET EDAC_INJECT_CR_CAN1_2E_MASK EDAC_INJECT_CR_CAN1_2E_OFFSET EDAC_INJECT_CR_DDRC_1E_MASK EDAC_INJECT_CR_DDRC_1E_OFFSET EDAC_INJECT_CR_DDRC_2E_MASK EDAC_INJECT_CR_DDRC_2E_OFFSET EDAC_INJECT_CR_MAC0_1E_MASK EDAC_INJECT_CR_MAC0_1E_OFFSET EDAC_INJECT_CR_MAC0_2E_MASK EDAC_INJECT_CR_MAC0_2E_OFFSET EDAC_INJECT_CR_MAC1_1E_MASK EDAC_INJECT_CR_MAC1_1E_OFFSET EDAC_INJECT_CR_MAC1_2E_MASK EDAC_INJECT_CR_MAC1_2E_OFFSET EDAC_INJECT_CR_MMC_1E_MASK EDAC_INJECT_CR_MMC_1E_OFFSET EDAC_INJECT_CR_MMC_2E_MASK EDAC_INJECT_CR_MMC_2E_OFFSET EDAC_INJECT_CR_OFFSET EDAC_INJECT_CR_USB_1E_MASK EDAC_INJECT_CR_USB_1E_OFFSET EDAC_INJECT_CR_USB_2E_MASK EDAC_INJECT_CR_USB_2E_OFFSET EDAC_INTEN_CR_CAN0_1E_MASK EDAC_INTEN_CR_CAN0_1E_OFFSET EDAC_INTEN_CR_CAN0_2E_MASK EDAC_INTEN_CR_CAN0_2E_OFFSET EDAC_INTEN_CR_CAN1_1E_MASK EDAC_INTEN_CR_CAN1_1E_OFFSET EDAC_INTEN_CR_CAN1_2E_MASK EDAC_INTEN_CR_CAN1_2E_OFFSET EDAC_INTEN_CR_DDRC_1E_MASK EDAC_INTEN_CR_DDRC_1E_OFFSET EDAC_INTEN_CR_DDRC_2E_MASK EDAC_INTEN_CR_DDRC_2E_OFFSET EDAC_INTEN_CR_MAC0_1E_MASK EDAC_INTEN_CR_MAC0_1E_OFFSET EDAC_INTEN_CR_MAC0_2E_MASK EDAC_INTEN_CR_MAC0_2E_OFFSET EDAC_INTEN_CR_MAC1_1E_MASK EDAC_INTEN_CR_MAC1_1E_OFFSET EDAC_INTEN_CR_MAC1_2E_MASK EDAC_INTEN_CR_MAC1_2E_OFFSET EDAC_INTEN_CR_MMC_1E_MASK EDAC_INTEN_CR_MMC_1E_OFFSET EDAC_INTEN_CR_MMC_2E_MASK EDAC_INTEN_CR_MMC_2E_OFFSET EDAC_INTEN_CR_OFFSET EDAC_INTEN_CR_USB_1E_MASK EDAC_INTEN_CR_USB_1E_OFFSET EDAC_INTEN_CR_USB_2E_MASK EDAC_INTEN_CR_USB_2E_OFFSET EDAC_SR_CAN0_1E_MASK EDAC_SR_CAN0_1E_OFFSET EDAC_SR_CAN0_2E_MASK EDAC_SR_CAN0_2E_OFFSET EDAC_SR_CAN1_1E_MASK EDAC_SR_CAN1_1E_OFFSET EDAC_SR_CAN1_2E_MASK EDAC_SR_CAN1_2E_OFFSET EDAC_SR_DDRC_1E_MASK EDAC_SR_DDRC_1E_OFFSET EDAC_SR_DDRC_2E_MASK EDAC_SR_DDRC_2E_OFFSET EDAC_SR_MAC0_1E_MASK EDAC_SR_MAC0_1E_OFFSET EDAC_SR_MAC0_2E_MASK EDAC_SR_MAC0_2E_OFFSET EDAC_SR_MAC1_1E_MASK EDAC_SR_MAC1_1E_OFFSET EDAC_SR_MAC1_2E_MASK EDAC_SR_MAC1_2E_OFFSET EDAC_SR_MMC_1E_MASK EDAC_SR_MMC_1E_OFFSET EDAC_SR_MMC_2E_MASK EDAC_SR_MMC_2E_OFFSET EDAC_SR_OFFSET EDAC_SR_USB_1E_MASK EDAC_SR_USB_1E_OFFSET EDAC_SR_USB_2E_MASK EDAC_SR_USB_2E_OFFSET EMMC_CONFIGURED_MASK ENVM_CR_CLOCK_CONTINUOUS_MASK ENVM_CR_CLOCK_CONTINUOUS_OFFSET ENVM_CR_CLOCK_OKAY_MASK ENVM_CR_CLOCK_OKAY_OFFSET ENVM_CR_CLOCK_PERIOD_MASK ENVM_CR_CLOCK_PERIOD_OFFSET ENVM_CR_CLOCK_SUPPRESS_MASK ENVM_CR_CLOCK_SUPPRESS_OFFSET ENVM_CR_INTERRUPT_ENABLE_MASK ENVM_CR_INTERRUPT_ENABLE_OFFSET ENVM_CR_OFFSET ENVM_CR_READAHEAD_MASK ENVM_CR_READAHEAD_OFFSET ENVM_CR_SLOWREAD_MASK ENVM_CR_SLOWREAD_OFFSET ENVM_CR_TIMER_MASK ENVM_CR_TIMER_OFFSET ENVM_E51_INT EP_FIFO_ADDR_STEP ERROR ESTATUS_1000_TFULL ESTATUS_1000_THALF EXPANSION_ENABLENPAGE EXPANSION_LCWP EXPANSION_MFAULTS EXPANSION_NPCAPABLE EXPANSION_NWAY EXPANSION_RESV EXT_IO_BASE EXT_IRQ_DISABLE EXT_IRQ_KEEP_ENABLED FABRIC_F2H_32_E51_INT FABRIC_F2H_33_E51_INT FABRIC_F2H_34_E51_INT FABRIC_F2H_35_E51_INT FABRIC_F2H_36_E51_INT FABRIC_F2H_37_E51_INT FABRIC_F2H_38_E51_INT FABRIC_F2H_39_E51_INT FABRIC_F2H_40_E51_INT FABRIC_F2H_41_E51_INT FABRIC_F2H_42_E51_INT FABRIC_F2H_43_E51_INT FABRIC_F2H_44_E51_INT FABRIC_F2H_45_E51_INT FABRIC_F2H_46_E51_INT FABRIC_F2H_47_E51_INT FABRIC_F2H_48_E51_INT FABRIC_F2H_49_E51_INT FABRIC_F2H_50_E51_INT FABRIC_F2H_51_E51_INT FABRIC_F2H_52_E51_INT FABRIC_F2H_53_E51_INT FABRIC_F2H_54_E51_INT FABRIC_F2H_55_E51_INT FABRIC_F2H_56_E51_INT FABRIC_F2H_57_E51_INT FABRIC_F2H_58_E51_INT FABRIC_F2H_59_E51_INT FABRIC_F2H_60_E51_INT FABRIC_F2H_61_E51_INT FABRIC_F2H_62_E51_INT FABRIC_F2H_63_E51_INT FABRIC_RESET_CR_ENABLE_MASK FABRIC_RESET_CR_ENABLE_OFFSET FABRIC_RESET_CR_OFFSET FABRIC_SD_EMMC_DEMUX_SELECT_ADDRESS FABRIC_SD_EMMC_DEMUX_SELECT_PRESENT FAB_INTEN_MAC0_U54_1_EN_MASK FAB_INTEN_MAC0_U54_1_EN_OFFSET FAB_INTEN_MAC0_U54_2_EN_MASK FAB_INTEN_MAC0_U54_2_EN_OFFSET FAB_INTEN_MAC1_U54_3_EN_MASK FAB_INTEN_MAC1_U54_3_EN_OFFSET FAB_INTEN_MAC1_U54_4_EN_MASK FAB_INTEN_MAC1_U54_4_EN_OFFSET FAB_INTEN_MISC_MAC0_U54_1_MASK FAB_INTEN_MISC_MAC0_U54_1_OFFSET FAB_INTEN_MISC_MAC0_U54_2_MASK FAB_INTEN_MISC_MAC0_U54_2_OFFSET FAB_INTEN_MISC_MAC1_U54_3_MASK FAB_INTEN_MISC_MAC1_U54_3_OFFSET FAB_INTEN_MISC_MAC1_U54_4_MASK FAB_INTEN_MISC_MAC1_U54_4_OFFSET FAB_INTEN_MISC_OFFSET FAB_INTEN_U54_1_ENABLE_MASK FAB_INTEN_U54_1_ENABLE_OFFSET FAB_INTEN_U54_1_OFFSET FAB_INTEN_U54_2_ENABLE_MASK FAB_INTEN_U54_2_ENABLE_OFFSET FAB_INTEN_U54_2_OFFSET FAB_INTEN_U54_3_ENABLE_MASK FAB_INTEN_U54_3_ENABLE_OFFSET FAB_INTEN_U54_3_OFFSET FAB_INTEN_U54_4_ENABLE_MASK FAB_INTEN_U54_4_ENABLE_OFFSET FAB_INTEN_U54_4_OFFSET FRMS_CBYTES FRMS_CBYTES_MASK FRMS_FBYTE FRMS_FBYTE_MASK FRMS_FWORD FRMS_FWORD_MASK FRMS_IDLE FRMS_IDLE_MASK FRMS_QSPI FRMS_TBYTES FRMS_TBYTES_MASK FRMS_UBYTES_MASK FS_DEV_NOT_SUPPORTED G5C_DEVRST_E51_INT G5C_MESSAGE_E51_INT GEM_ACKNOWLEDGE GEM_ACKNOWLEDGE_2 GEM_ADD_CSR_PARITY GEM_ADD_DP_PARITY GEM_ADD_ECC_DPRAM GEM_ADD_FRAG_SIZE GEM_ADD_SUBTRACT GEM_ALIGNMENT_ERROR_COUNT GEM_ALT_NS_INC GEM_ALT_SGMII_MODE GEM_AMBA_BURST_LENGTH GEM_AMBA_ERROR GEM_AN_AV_FULL_DUPLEX GEM_AN_AV_HALF_DUPLEX GEM_AN_AV_NEXT_PAGE GEM_AN_AV_PAUSE GEM_AN_AV_REMOTE_FAULT GEM_AN_MESSAGE GEM_AR2R_MAX_PIPELINE GEM_ASS_ERR_COUNT GEM_ASS_OK_COUNT GEM_AUTO_FLUSHED_COUNT GEM_AUTO_NEG_ABILITY GEM_AUTO_NEG_COMPLETE GEM_AW2W_MAX_PIPELINE GEM_AXI GEM_AXI_ACCESS_PIPELINE_BITS GEM_AXI_CACHE_VALUE GEM_AXI_PROT_VALUE GEM_AXI_RX_DESCR_RD_BUFF_BITS GEM_AXI_RX_DESCR_WR_BUFF_BITS GEM_AXI_TX_DESCR_RD_BUFF_BITS GEM_AXI_TX_DESCR_WR_BUFF_BITS GEM_AXI_TX_FULL_ADJ_0 GEM_AXI_TX_FULL_ADJ_1 GEM_AXI_TX_FULL_ADJ_2 GEM_AXI_TX_FULL_ADJ_3 GEM_A_LO_BASE GEM_BACK_PRESSURE GEM_BASE_100_T4 GEM_BASE_100_T2_FULL_DUPLEX GEM_BASE_100_T2_HALF_DUPLEX GEM_BASE_100_X_FULL_DUPLEX GEM_BASE_100_X_HALF_DUPLEX GEM_BD_TS_MODE GEM_BD_TS_MODE_SHIFT GEM_BUFFER_NOT_AVAILABLE GEM_B_LO_BASE GEM_CBS_ENABLE_QUEUE_A GEM_CBS_ENABLE_QUEUE_B GEM_CLEAR_ALL_STATS_REGS GEM_CODEGROUP_BYPASS GEM_COLLISION_OCCURRED GEM_COLLISION_TEST GEM_COMMA_BYPASS GEM_COMPARE_A GEM_COMPARE_A_ENABLE GEM_COMPARE_A_SHIFT GEM_COMPARE_B GEM_COMPARE_B_ENABLE GEM_COMPARE_B_SHIFT GEM_COMPARE_C GEM_COMPARE_C_ENABLE GEM_COMPARE_C_SHIFT GEM_COMPARE_OFFSET GEM_COMPARE_OFFSET_SHIFT GEM_COMPARE_S_TAG GEM_COMPARE_VALUE GEM_COMPARE_VLAN_ID GEM_COPY_ALL_FRAMES GEM_CRC_ERROR_REPORT GEM_CRS_ERROR_COUNT GEM_DATA_BUS_WIDTH GEM_DATA_BUS_WIDTH_SHIFT GEM_DEFERRED_FRAMES_COUNT GEM_DISABLE_COPY_OF_PAUSE_FRAMES GEM_DISABLE_MASK GEM_DISCARD_NON_VLAN_FRAMES GEM_DMA_ADDR_BUS_WIDTH_1 GEM_DMA_ADDR_WIDTH_IS_64B GEM_DMA_BUS_WIDTH GEM_DMA_BUS_WIDTH_DEF GEM_DMA_CUTTHRU GEM_DMA_DBUF_ADDR_MASK_ENABLE GEM_DMA_DBUF_ADDR_MASK_VALUE GEM_DMA_EMAC_CUTTHRU_THRESHOLD GEM_DMA_PRIORITY_QUEUE1 GEM_DMA_PRIORITY_QUEUE2 GEM_DMA_PRIORITY_QUEUE3 GEM_DMA_PRIORITY_QUEUE4 GEM_DMA_PRIORITY_QUEUE5 GEM_DMA_PRIORITY_QUEUE6 GEM_DMA_PRIORITY_QUEUE7 GEM_DMA_PRIORITY_QUEUE8 GEM_DMA_PRIORITY_QUEUE9 GEM_DMA_PRIORITY_QUEUE10 GEM_DMA_PRIORITY_QUEUE11 GEM_DMA_PRIORITY_QUEUE12 GEM_DMA_PRIORITY_QUEUE13 GEM_DMA_PRIORITY_QUEUE14 GEM_DMA_PRIORITY_QUEUE15 GEM_DMA_RX_CUTTHRU_THRESHOLD GEM_DMA_RX_DIS_Q GEM_DMA_RX_Q_BUF_SIZE GEM_DMA_RX_Q_PTR GEM_DMA_TX_CUTTHRU_THRESHOLD GEM_DMA_TX_DIS_Q GEM_DMA_TX_Q_FILL_LEVEL_SELECT GEM_DMA_TX_Q_PTR GEM_DMA_TX_RX_FILL_LEVEL GEM_DMA_TX_RX_FILL_LEVEL_SELECT GEM_DROP_ON_MATCH GEM_DSTC_ENABLE GEM_DSTC_MATCH GEM_DSTC_MATCH_SHIFT GEM_DWRR_ETS_WEIGHT_Q0 GEM_DWRR_ETS_WEIGHT_Q1 GEM_DWRR_ETS_WEIGHT_Q2 GEM_DWRR_ETS_WEIGHT_Q3 GEM_EMAC_BUS_WIDTH GEM_EMAC_RX_PBUF_ADDR GEM_EMAC_TX_PBUF_ADDR GEM_ENABLE_AUTO_NEG GEM_ENABLE_COPY GEM_ENABLE_PROCESSING GEM_ENABLE_RECEIVE GEM_ENABLE_TRANSMIT GEM_ENDIAN_SWAP_DEF GEM_ENDIAN_SWAP_MANAGEMENT GEM_ENDIAN_SWAP_PACKET GEM_ENST_DISABLE_Q_0 GEM_ENST_DISABLE_Q_1 GEM_ENST_DISABLE_Q_2 GEM_ENST_DISABLE_Q_3 GEM_ENST_ENABLE_Q_0 GEM_ENST_ENABLE_Q_1 GEM_ENST_ENABLE_Q_2 GEM_ENST_ENABLE_Q_3 GEM_EN_HALF_DUPLEX_RX GEM_ETHERTYPE_ENABLE GEM_ETHERTYPE_REG_INDEX GEM_ETHERTYPE_REG_INDEX_SHIFT GEM_EXCLUDE_CBS GEM_EXCLUDE_QBV GEM_EXTENDED_CAPABILITIES GEM_EXTENDED_STATUS GEM_EXTERNAL_ADDRESS_MATCH_ENABLE GEM_EXTERNAL_INTERRUPT GEM_EXT_FIFO_INTERFACE GEM_EXT_RXQ_SEL_EN GEM_EXT_TSU_PORT_ENABLE GEM_EXT_TSU_TIMER GEM_FCS_ERROR_COUNT GEM_FCS_REMOVE GEM_FILTER_BYTE_MASK GEM_FILTER_TYPE GEM_FIX_NUMBER GEM_FLUSH_RX_PKT_PCLK GEM_FORCE_DISCARD_ON_ERR GEM_FORCE_MAX_AMBA_BURST_RX GEM_FORCE_MAX_AMBA_BURST_TX GEM_FRAG_COUNT GEM_FRAME_COUNT GEM_FRAME_RECEIVED GEM_FRER_COUNT_ERR GEM_FULL_DUPLEX GEM_FULL_DUPLEX_1000BASE_T GEM_FULL_DUPLEX_1000BASE_X GEM_GEM_CB_HISTORY_LEN GEM_GEM_HAS_802P3_BR GEM_GEM_HAS_CB GEM_GEM_NUM_CB_STREAMS GEM_GIGABIT_MODE_ENABLE GEM_HALF_DUPLEX_1000BASE_T GEM_HALF_DUPLEX_1000BASE_X GEM_HDR_DATA_SPLITTING_EN GEM_HOST_IF_SOFT_SEL GEM_HPROT_VALUE GEM_ID_CODE GEM_IFG_EATS_QAV_CREDIT GEM_IGNORE_IPG_RX_ER GEM_IGNORE_RX_FCS GEM_INC_ALL_STATS_REGS GEM_INFINITE_LAST_DBUF_SIZE_EN GEM_INT_FRER_COUNT_ERR GEM_INT_LOOPBACK GEM_INT_RCV_R_ERROR GEM_INT_RCV_V_ERROR GEM_INT_SMDC_ERROR GEM_INT_SMDS_ERROR GEM_INT_SMD_ERROR GEM_IPG_STRETCH GEM_IPG_STRETCH_DIV GEM_IPG_STRETCH_DIV_MASK GEM_IPG_STRETCH_DIV_SHIFT GEM_IPG_STRETCH_ENABLE GEM_IPG_STRETCH_MUL GEM_IPG_STRETCH_MUL_MASK GEM_IP_CHECKSUM_ERROR_COUNT GEM_IRQ_READ_CLEAR GEM_JABBER_COUNT GEM_JUMBO_FRAMES GEM_JUMBO_MAX_LENGTH GEM_LATE_COLLISION_COUNT GEM_LATE_COLLISION_OCCURRED GEM_LENGTH_ERROR_COUNT GEM_LENGTH_FIELD_ERROR_FRAME_DISCARD GEM_LINK_CHANGE GEM_LINK_PARTNER_ACKNOWLEDGE GEM_LINK_PARTNER_FULL_DUPLEX GEM_LINK_PARTNER_HALF_DUPLEX GEM_LINK_PARTNER_NEXT_PAGE_STATUS GEM_LINK_PARTNER_PAUSE GEM_LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE GEM_LINK_PARTNER_SPEED GEM_LINK_STATUS GEM_LOCKUP_DETECTED_INT_TYPE GEM_LOCKUP_RECOVERY_EN GEM_LOCKUP_TIME GEM_LOOPBACK GEM_LOOPBACK_LOCAL GEM_LOOPBACK_MODE GEM_LPI_COUNT GEM_LPI_INDICATE_PCLK GEM_LPI_TIME GEM_MAC_DUPLEX_STATE GEM_MAC_FULL_DUPLEX GEM_MAC_PAUSE_RX_EN GEM_MAC_PAUSE_TX_EN GEM_MANAGEMENT_FRAME_SENT GEM_MAN_DONE GEM_MAN_PORT_EN GEM_MBPS_10_FULL_DUPLEX GEM_MBPS_10_HALF_DUPLEX GEM_MDC_CLOCK_DIV GEM_MDC_CLOCK_DIVISOR GEM_MDC_CLOCK_DIVISOR_MASK GEM_MDC_CLOCK_DIVISOR_SHIFT GEM_MDIO_IN GEM_MESSAGE_PAGE_INDICATOR GEM_MMSL_DEBUG_MODE GEM_MODULE_IDENTIFICATION_NUMBER GEM_MODULE_REVISION GEM_MULTICAST_HASH_ENABLE GEM_NEXT_PAGE_CAPABILITY GEM_NEXT_PAGE_TO_RECEIVE GEM_NEXT_PAGE_TO_TRANSMIT GEM_NO_BROADCAST GEM_NO_PCS GEM_NO_SNAPSHOT GEM_NO_STATS GEM_NSEC_COMPARISON_VALUE GEM_NSP_CHANGE GEM_NS_INCREMENT GEM_NUM_INCS GEM_NUM_SCR2_COMPARE_REGS GEM_NUM_SCR2_ETHTYPE_REGS GEM_NUM_SPEC_ADD_FILTERS GEM_NUM_TYPE1_SCREENERS GEM_NUM_TYPE2_SCREENERS GEM_OFFSET_VALUE GEM_ONE_STEP_SYNC_MODE GEM_ON_OFF_TIME GEM_OPERATION GEM_OPERATION_SHIFT GEM_OSS_CORRECTION_FIELD GEM_OVERRUN_COUNT GEM_OVERSIZE_FRAME_COUNT GEM_PAGE_RECEIVED GEM_PAUSE_ENABLE GEM_PAUSE_FRAME_TRANSMITTED GEM_PAUSE_FRAME_WITH_NON_0_PAUSE_QUANTUM_RX GEM_PAUSE_TIME_ELAPSED GEM_PBUF_CUTTHRU GEM_PBUF_LSO GEM_PBUF_RSC GEM_PCS_AUTO_NEGOTIATION_COMPLETE GEM_PCS_INT_TYPE GEM_PCS_LINK_PARTNER_PAGE_RECEIVED GEM_PCS_LINK_STATE GEM_PCS_SELECT GEM_PCS_SOFTWARE_RESET GEM_PFC_CTRL GEM_PFC_ENABLE GEM_PFC_MULTI_QUANTUM GEM_PFC_NEGOTIATE_PCLK GEM_PHY_ADDRESS GEM_PHY_ADDRESS_SHIFT GEM_PHY_IDENT GEM_PHY_OP_CL22_READ GEM_PHY_OP_CL22_WRITE GEM_PHY_OP_CL45_ADDRESS GEM_PHY_OP_CL45_POST_READ_INC GEM_PHY_OP_CL45_READ GEM_PHY_OP_CL45_WRITE GEM_PHY_WRITE_READ_DATA GEM_PRE_ACTIVE GEM_PRE_ENABLE GEM_PROTECT_DESCR_ADDR GEM_PROTECT_TSU GEM_PTP_DELAY_REQ_FRAME_RECEIVED GEM_PTP_DELAY_REQ_FRAME_TRANSMITTED GEM_PTP_FRAME_RECEIVED_INT_TYPE GEM_PTP_PDELAY_REQ_FRAME_RECEIVED GEM_PTP_PDELAY_REQ_FRAME_TRANSMITTED GEM_PTP_PDELAY_RESP_FRAME_RECEIVED GEM_PTP_PDELAY_RESP_FRAME_TRANSMITTED GEM_PTP_SYNC_FRAME_RECEIVED GEM_PTP_SYNC_FRAME_TRANSMITTED GEM_PTP_UNICAST_ENA GEM_QUANTUM GEM_QUEUE_NUMBER GEM_RCV_R_ERROR GEM_RCV_V_ERROR GEM_RECEIVE_1536_BYTE_FRAMES GEM_RECEIVE_BUFFER_OFFSET GEM_RECEIVE_BUFFER_OFFSET_SHIFT GEM_RECEIVE_CHECKSUM_OFFLOAD_ENABLE GEM_RECEIVE_COMPLETE GEM_RECEIVE_LPI_INT_TYPE GEM_RECEIVE_OVERRUN GEM_RECEIVE_OVERRUN_INT GEM_REGISTER_ADDRESS GEM_REGISTER_ADDRESS_SHIFT GEM_REMOTE_FAULT GEM_RESOURCE_ERROR_COUNT GEM_RESPOND_STATUS GEM_RESP_NOT_OK_INT GEM_RESTART_AUTO_NEG GEM_RESTART_VER GEM_RETRY_LIMIT_EXCEEDED GEM_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION GEM_RETRY_TEST GEM_ROUTE_RX_TO_PMAC GEM_RUNT_FRAME_COUNT GEM_RX_BD_EXTENDED_MODE_EN GEM_RX_BD_REREAD_TIMER GEM_RX_BUFFER_LENGTH_DEF GEM_RX_BUF_SIZE GEM_RX_BUF_SIZE_SHIFT GEM_RX_DMA_LOCKUP_DETECTED GEM_RX_DMA_LOCKUP_MON_EN GEM_RX_FIFO_CNT_WIDTH GEM_RX_INT_MODERATION GEM_RX_LOCKUP_DETECTED GEM_RX_LPI_INDICATION_STATUS_BIT_CHANGE GEM_RX_MAC_LOCKUP_DETECTED GEM_RX_MAC_LOCKUP_MON_EN GEM_RX_PBUF_ADDR GEM_RX_PBUF_DATA GEM_RX_PBUF_SIZE GEM_RX_PBUF_SIZE_DEF GEM_RX_PBUF_SIZE_SHIFT GEM_RX_PKT_BUFFER GEM_RX_RESP_NOT_OK GEM_RX_USED_BIT_READ GEM_SEC_VALUE_UPPER GEM_SEGMENT_ALLOC_Q0 GEM_SEGMENT_ALLOC_Q1 GEM_SEGMENT_ALLOC_Q2 GEM_SEGMENT_ALLOC_Q3 GEM_SEL_MII_ON_RGMII GEM_SGMII_MODE_ENABLE GEM_SMDC_ERROR GEM_SMDS_ERROR GEM_SMD_ERROR GEM_SMD_ERR_COUNT GEM_SMD_ERR_COUNT_SHIFT GEM_SM_COLLISION_COUNT GEM_SPEC_ADDRESS GEM_SPEC_ADDR_MASK GEM_SPEC_ADDR_MATCH GEM_SPEED GEM_SPEED_SELECT_BIT_0 GEM_SPEED_SELECT_BIT_1 GEM_SPRAM GEM_START_TIME_NSEC GEM_START_TIME_SEC GEM_STATS_WRITE_EN GEM_STAT_AMBA_ERROR GEM_STAT_TRANSMIT_COMPLETE GEM_STAT_TRANSMIT_UNDER_RUN GEM_STORE_RX_TS GEM_STORE_UDP_OFFSET GEM_SUB_NS_INCR GEM_SUB_NS_INCR_LSB GEM_SYMBOL_ERROR_COUNT GEM_SYS_WAKE_TIME GEM_T2_DROP_ON_MATCH GEM_TOGGLE GEM_TRANSMIT_COMPLETE GEM_TRANSMIT_GO GEM_TRANSMIT_HALT GEM_TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME GEM_TRANSMIT_START GEM_TRANSMIT_UNDER_RUN GEM_TSU GEM_TSU_CLK GEM_TSU_CLK_SOURCE GEM_TSU_NANOSECONDS GEM_TSU_SECONDS_MSB GEM_TSU_SECONDS_REGISTER_INCREMENT GEM_TSU_SECONDS_REGISTER_INCREMENT_INT_TYPE GEM_TSU_TIMER_COMPARISON_INTERRUPT GEM_TSU_TIMER_COMPARISON_INTERRUPT_INT_TYPE GEM_TWO_PT_FIVE_GIG GEM_TX_ADD_FIFO_IF GEM_TX_BD_EXTENDED_MODE_EN GEM_TX_DMA_LOCKUP_DETECTED GEM_TX_DMA_LOCKUP_MON_EN GEM_TX_FIFO_CNT_WIDTH GEM_TX_INT_MODERATION GEM_TX_LOCKUP_DETECTED GEM_TX_LPI_EN GEM_TX_MAC_LOCKUP_DETECTED GEM_TX_MAC_LOCKUP_MON_EN GEM_TX_PAUSE_FRAME_REQ GEM_TX_PAUSE_FRAME_ZERO GEM_TX_PBUF_ADDR GEM_TX_PBUF_DATA GEM_TX_PBUF_NUM_SEGMENTS_Q0 GEM_TX_PBUF_NUM_SEGMENTS_Q1 GEM_TX_PBUF_NUM_SEGMENTS_Q2 GEM_TX_PBUF_NUM_SEGMENTS_Q3 GEM_TX_PBUF_NUM_SEGMENTS_Q4 GEM_TX_PBUF_NUM_SEGMENTS_Q5 GEM_TX_PBUF_NUM_SEGMENTS_Q6 GEM_TX_PBUF_NUM_SEGMENTS_Q7 GEM_TX_PBUF_NUM_SEGMENTS_Q8 GEM_TX_PBUF_NUM_SEGMENTS_Q9 GEM_TX_PBUF_NUM_SEGMENTS_Q10 GEM_TX_PBUF_NUM_SEGMENTS_Q11 GEM_TX_PBUF_NUM_SEGMENTS_Q12 GEM_TX_PBUF_NUM_SEGMENTS_Q13 GEM_TX_PBUF_NUM_SEGMENTS_Q14 GEM_TX_PBUF_NUM_SEGMENTS_Q15 GEM_TX_PBUF_QUEUE_SEGMENT_SIZE GEM_TX_PBUF_SIZE GEM_TX_PBUF_SIZE_DEF GEM_TX_PBUF_TCP_EN GEM_TX_PKT_BUFFER GEM_TX_RESP_NOT_OK GEM_TX_SCHED_Q0 GEM_TX_SCHED_Q1 GEM_TX_SCHED_Q2 GEM_TX_SCHED_Q3 GEM_TX_USED_BIT_READ GEM_UDP_PORT_MATCH GEM_UDP_PORT_MATCH_ENABLE GEM_UDP_PORT_MATCH_SHIFT GEM_UNDERRUN_COUNT GEM_UNICAST_HASH_ENABLE GEM_UNI_DIRECTION_ENABLE GEM_UPPER_BITS_OF_48 GEM_USED_BIT_READ GEM_USER_IN_WIDTH GEM_USER_IO GEM_USER_OUT_WIDTH GEM_USE_AW2B_FILL GEM_VECTOR GEM_VECTOR_ENABLE GEM_VERIFY_DISABLE GEM_VERIFY_DONE_FAIL GEM_VERIFY_DONE_OK GEM_VERIFY_IDLE GEM_VERIFY_INIT GEM_VERIFY_SEND GEM_VERIFY_STATUS GEM_VERIFY_STATUS_SHIFT GEM_VERIFY_WAIT GEM_VLAN_C_TAG GEM_VLAN_ENABLE GEM_VLAN_ETHERTYPE_MIN GEM_VLAN_MATCH GEM_VLAN_NO_STACK GEM_VLAN_PRIORITY GEM_VLAN_PRIORITY_SHIFT GEM_VLAN_S_TAG GEM_W0_COMPARE_VALUE GEM_W0_MASK_VALUE GEM_WOL_ADDRESS GEM_WOL_ARP_REQUEST GEM_WOL_INTERRUPT GEM_WOL_INTERRUPT_INT_TYPE GEM_WOL_MAGIC_PACKET GEM_WOL_MULTICAST_HASH GEM_WOL_SPEC_ADDRESS_1 GEM_WRITE0 GEM_WRITE1 GEM_WRITE10 GEM_WRITE10_SHIFT GMII GMII_SGMII GPIO0_HI GPIO0_LO GPIO1_HI GPIO1_LO GPIO2_HI GPIO2_LO GPIO_0_MASK GPIO_1_MASK GPIO_2_MASK GPIO_3_MASK GPIO_4_MASK GPIO_5_MASK GPIO_6_MASK GPIO_7_MASK GPIO_8_MASK GPIO_9_MASK GPIO_10_MASK GPIO_11_MASK GPIO_12_MASK GPIO_13_MASK GPIO_14_MASK GPIO_15_MASK GPIO_16_MASK GPIO_17_MASK GPIO_18_MASK GPIO_19_MASK GPIO_20_MASK GPIO_21_MASK GPIO_22_MASK GPIO_23_MASK GPIO_24_MASK GPIO_25_MASK GPIO_26_MASK GPIO_27_MASK GPIO_28_MASK GPIO_29_MASK GPIO_30_MASK GPIO_31_MASK GPIO_CR_GPIO0_DEFAULT_MASK GPIO_CR_GPIO0_DEFAULT_OFFSET GPIO_CR_GPIO0_SOFT_RESET_SELECT_MASK GPIO_CR_GPIO0_SOFT_RESET_SELECT_OFFSET GPIO_CR_GPIO1_DEFAULT_MASK GPIO_CR_GPIO1_DEFAULT_OFFSET GPIO_CR_GPIO1_SOFT_RESET_SELECT_MASK GPIO_CR_GPIO1_SOFT_RESET_SELECT_OFFSET GPIO_CR_GPIO2_DEFAULT_MASK GPIO_CR_GPIO2_DEFAULT_OFFSET GPIO_CR_GPIO2_SOFT_RESET_SELECT_MASK GPIO_CR_GPIO2_SOFT_RESET_SELECT_OFFSET GPIO_CR_OFFSET GPIO_INOUT_MODE GPIO_INPUT_MODE GPIO_INTERRUPT_FAB_CR_OFFSET GPIO_INTERRUPT_FAB_CR_SELECT_MASK GPIO_INTERRUPT_FAB_CR_SELECT_OFFSET GPIO_IRQ_EDGE_BOTH GPIO_IRQ_EDGE_NEGATIVE GPIO_IRQ_EDGE_POSITIVE GPIO_IRQ_LEVEL_HIGH GPIO_IRQ_LEVEL_LOW GPIO_OUTPUT_MODE H2_FABRIC_F2H_0_U54_INT H2_FABRIC_F2H_1_U54_INT H2_FABRIC_F2H_2_U54_INT H2_FABRIC_F2H_3_U54_INT H2_FABRIC_F2H_4_U54_INT H2_FABRIC_F2H_5_U54_INT H2_FABRIC_F2H_6_U54_INT H2_FABRIC_F2H_7_U54_INT H2_FABRIC_F2H_8_U54_INT H2_FABRIC_F2H_9_U54_INT H2_FABRIC_F2H_10_U54_INT H2_FABRIC_F2H_11_U54_INT H2_FABRIC_F2H_12_U54_INT H2_FABRIC_F2H_13_U54_INT H2_FABRIC_F2H_14_U54_INT H2_FABRIC_F2H_15_U54_INT H2_FABRIC_F2H_16_U54_INT H2_FABRIC_F2H_17_U54_INT H2_FABRIC_F2H_18_U54_INT H2_FABRIC_F2H_19_U54_INT H2_FABRIC_F2H_20_U54_INT H2_FABRIC_F2H_21_U54_INT H2_FABRIC_F2H_22_U54_INT H2_FABRIC_F2H_23_U54_INT H2_FABRIC_F2H_24_U54_INT H2_FABRIC_F2H_25_U54_INT H2_FABRIC_F2H_26_U54_INT H2_FABRIC_F2H_27_U54_INT H2_FABRIC_F2H_28_U54_INT H2_FABRIC_F2H_29_U54_INT H2_FABRIC_F2H_30_U54_INT H2_FABRIC_F2H_31_U54_INT HALF_GB_MTC HART0_TICK_RATE_MS HART1_TICK_RATE_MS HART2_TICK_RATE_MS HART3_TICK_RATE_MS HART4_TICK_RATE_MS HLS_DATA_IN_WFI HLS_DATA_PASSED_WFI HLS_DEBUG_AREA_SIZE HLS_SIZE HUB_CLASS_NOT_SUPPORTED IMAGE_LOADED_BY_BOOTLOADER INIT_MARKER INIT_SETTING_SEG0_0 INIT_SETTING_SEG0_1 INIT_SETTING_SEG0_2 INIT_SETTING_SEG0_3 INIT_SETTING_SEG0_4 INIT_SETTING_SEG0_5 INIT_SETTING_SEG0_6 INIT_SETTING_SEG0_7 INIT_SETTING_SEG1_0 INIT_SETTING_SEG1_1 INIT_SETTING_SEG1_2 INIT_SETTING_SEG1_3 INIT_SETTING_SEG1_4 INIT_SETTING_SEG1_5 INIT_SETTING_SEG1_6 INIT_SETTING_SEG1_7 INTEGER_CONTEXT_SIZE INTE_RAVLB INTE_RAVLB_MASK INTE_RDONE INTE_RDONE_MASK INTE_RFEMPTY INTE_RFEMPTY_MASK INTE_TAVLB INTE_TAVLB_MASK INTE_TDONE INTE_TDONE_MASK INTE_TFFULL INTE_TFFULL_MASK IOMUX0_CR_CAN0_FABRIC_MASK IOMUX0_CR_CAN0_FABRIC_OFFSET IOMUX0_CR_CAN1_FABRIC_MASK IOMUX0_CR_CAN1_FABRIC_OFFSET IOMUX0_CR_I2C0_FABRIC_MASK IOMUX0_CR_I2C0_FABRIC_OFFSET IOMUX0_CR_I2C1_FABRIC_MASK IOMUX0_CR_I2C1_FABRIC_OFFSET IOMUX0_CR_MDIO0_FABRIC_MASK IOMUX0_CR_MDIO0_FABRIC_OFFSET IOMUX0_CR_MDIO1_FABRIC_MASK IOMUX0_CR_MDIO1_FABRIC_OFFSET IOMUX0_CR_MMUART0_FABRIC_MASK IOMUX0_CR_MMUART0_FABRIC_OFFSET IOMUX0_CR_MMUART1_FABRIC_MASK IOMUX0_CR_MMUART1_FABRIC_OFFSET IOMUX0_CR_MMUART2_FABRIC_MASK IOMUX0_CR_MMUART2_FABRIC_OFFSET IOMUX0_CR_MMUART3_FABRIC_MASK IOMUX0_CR_MMUART3_FABRIC_OFFSET IOMUX0_CR_MMUART4_FABRIC_MASK IOMUX0_CR_MMUART4_FABRIC_OFFSET IOMUX0_CR_OFFSET IOMUX0_CR_QSPI_FABRIC_MASK IOMUX0_CR_QSPI_FABRIC_OFFSET IOMUX0_CR_SPI0_FABRIC_MASK IOMUX0_CR_SPI0_FABRIC_OFFSET IOMUX0_CR_SPI1_FABRIC_MASK IOMUX0_CR_SPI1_FABRIC_OFFSET IOMUX1_CR_OFFSET IOMUX1_CR_PAD0_MASK IOMUX1_CR_PAD0_OFFSET IOMUX1_CR_PAD1_MASK IOMUX1_CR_PAD1_OFFSET IOMUX1_CR_PAD2_MASK IOMUX1_CR_PAD2_OFFSET IOMUX1_CR_PAD3_MASK IOMUX1_CR_PAD3_OFFSET IOMUX1_CR_PAD4_MASK IOMUX1_CR_PAD4_OFFSET IOMUX1_CR_PAD5_MASK IOMUX1_CR_PAD5_OFFSET IOMUX1_CR_PAD6_MASK IOMUX1_CR_PAD6_OFFSET IOMUX1_CR_PAD7_MASK IOMUX1_CR_PAD7_OFFSET IOMUX2_CR_OFFSET IOMUX2_CR_PAD8_MASK IOMUX2_CR_PAD8_OFFSET IOMUX2_CR_PAD9_MASK IOMUX2_CR_PAD9_OFFSET IOMUX2_CR_PAD10_MASK IOMUX2_CR_PAD10_OFFSET IOMUX2_CR_PAD11_MASK IOMUX2_CR_PAD11_OFFSET IOMUX2_CR_PAD12_MASK IOMUX2_CR_PAD12_OFFSET IOMUX2_CR_PAD13_MASK IOMUX2_CR_PAD13_OFFSET IOMUX3_CR_OFFSET IOMUX3_CR_PAD14_MASK IOMUX3_CR_PAD14_OFFSET IOMUX3_CR_PAD15_MASK IOMUX3_CR_PAD15_OFFSET IOMUX3_CR_PAD16_MASK IOMUX3_CR_PAD16_OFFSET IOMUX3_CR_PAD17_MASK IOMUX3_CR_PAD17_OFFSET IOMUX3_CR_PAD18_MASK IOMUX3_CR_PAD18_OFFSET IOMUX3_CR_PAD19_MASK IOMUX3_CR_PAD19_OFFSET IOMUX3_CR_PAD20_MASK IOMUX3_CR_PAD20_OFFSET IOMUX3_CR_PAD21_MASK IOMUX3_CR_PAD21_OFFSET IOMUX4_CR_OFFSET IOMUX4_CR_PAD22_MASK IOMUX4_CR_PAD22_OFFSET IOMUX4_CR_PAD23_MASK IOMUX4_CR_PAD23_OFFSET IOMUX4_CR_PAD24_MASK IOMUX4_CR_PAD24_OFFSET IOMUX4_CR_PAD25_MASK IOMUX4_CR_PAD25_OFFSET IOMUX4_CR_PAD26_MASK IOMUX4_CR_PAD26_OFFSET IOMUX4_CR_PAD27_MASK IOMUX4_CR_PAD27_OFFSET IOMUX4_CR_PAD28_MASK IOMUX4_CR_PAD28_OFFSET IOMUX4_CR_PAD29_MASK IOMUX4_CR_PAD29_OFFSET IOMUX5_CR_OFFSET IOMUX5_CR_PAD30_MASK IOMUX5_CR_PAD30_OFFSET IOMUX5_CR_PAD31_MASK IOMUX5_CR_PAD31_OFFSET IOMUX5_CR_PAD32_MASK IOMUX5_CR_PAD32_OFFSET IOMUX5_CR_PAD33_MASK IOMUX5_CR_PAD33_OFFSET IOMUX5_CR_PAD34_MASK IOMUX5_CR_PAD34_OFFSET IOMUX5_CR_PAD35_MASK IOMUX5_CR_PAD35_OFFSET IOMUX5_CR_PAD36_MASK IOMUX5_CR_PAD36_OFFSET IOMUX5_CR_PAD37_MASK IOMUX5_CR_PAD37_OFFSET IOMUX6_CR_OFFSET IOMUX6_CR_SD_LED_MASK IOMUX6_CR_SD_LED_OFFSET IOMUX6_CR_SD_VOLT_0_MASK IOMUX6_CR_SD_VOLT_0_OFFSET IOMUX6_CR_SD_VOLT_1_MASK IOMUX6_CR_SD_VOLT_1_OFFSET IOMUX6_CR_SD_VOLT_2_MASK IOMUX6_CR_SD_VOLT_2_OFFSET IOMUX6_CR_VLT_CMD_DIR_MASK IOMUX6_CR_VLT_CMD_DIR_OFFSET IOMUX6_CR_VLT_DIR_0_MASK IOMUX6_CR_VLT_DIR_0_OFFSET IOMUX6_CR_VLT_DIR_1_3_MASK IOMUX6_CR_VLT_DIR_1_3_OFFSET IOMUX6_CR_VLT_EN_MASK IOMUX6_CR_VLT_EN_OFFSET IOMUX6_CR_VLT_SEL_MASK IOMUX6_CR_VLT_SEL_OFFSET IOSCBCFG_BASE IOSCB_BANKCONT_DDR_BASE IOSCB_BANK_CNTL_SGMII_BASE IOSCB_DLL_SGMII_BASE IOSCB_IO_CALIB_DDR_BASE IOSCB_IO_CALIB_SGMII_BASE IPI_FENCE_I IPI_SFENCE_VMA IPI_SOFT IRQ_COP IRQ_HOST IRQ_H_EXT IRQ_H_SOFT IRQ_H_TIMER IRQ_M_BEU IRQ_M_EXT IRQ_M_LOCAL_MAX IRQ_M_LOCAL_MIN IRQ_M_SOFT IRQ_M_TIMER IRQ_S_EXT IRQ_S_SOFT IRQ_S_TIMER KM_AUTH_CODE KM_DEFAULT_KEY KM_FACTORY_EC KM_FACTORY_EC_E KM_FACTORY_KEY KM_INIT_FACTORY KM_USER_EC KM_USER_EC_E KM_USER_KEY1 KM_USER_KEY2 KM_ZERO_RECOVERY L2_SHUTDOWN_CR_L2_RAMS_MASK L2_SHUTDOWN_CR_L2_RAMS_OFFSET L2_SHUTDOWN_CR_OFFSET LATE_EYE_WIDTH_PART_NOT_DETERMINED LATE_EYE_WIDTH_PART_REVC_OR_LATER LATE_EYE_WIDTH_PART_REVC_OR_LATER_PRE_TEST LATE_EYE_WIDTH_SS_PART_REVB LATE_TT_PART_REVB LIBERO_FAST_START LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_0_DEG_DDR3 LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_0_DEG_DDR4 LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_0_DEG_DDR3L LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_0_DEG_LPDDR3 LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_0_DEG_LPDDR4 LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_45_DEG_DDR3 LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_45_DEG_DDR4 LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_45_DEG_DDR3L LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_45_DEG_LPDDR3 LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_45_DEG_LPDDR4 LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_90_DEG_DDR3 LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_90_DEG_DDR4 LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_90_DEG_DDR3L LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_90_DEG_LPDDR3 LIBERO_SETTING_ADD_CMD_CLK_MOVE_ORDER_90_DEG_LPDDR4 LIBERO_SETTING_ALT_GPIO_INTERRUPT_FAB_CR LIBERO_SETTING_ALT_IOMUX0_CR LIBERO_SETTING_ALT_IOMUX1_CR LIBERO_SETTING_ALT_IOMUX2_CR LIBERO_SETTING_ALT_IOMUX3_CR LIBERO_SETTING_ALT_IOMUX4_CR LIBERO_SETTING_ALT_IOMUX5_CR LIBERO_SETTING_ALT_IOMUX6_CR LIBERO_SETTING_ALT_MSSIO_BANK2_CFG_CR LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_0_1_CR LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_2_3_CR LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_4_5_CR LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_6_7_CR LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_8_9_CR LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_10_11_CR LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_12_13_CR LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_14_15_CR LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_16_17_CR LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_18_19_CR LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_20_21_CR LIBERO_SETTING_ALT_MSSIO_BANK2_IO_CFG_22_23_CR LIBERO_SETTING_ALT_MSSIO_BANK4_CFG_CR LIBERO_SETTING_ALT_MSSIO_BANK4_IO_CFG_0_1_CR LIBERO_SETTING_ALT_MSSIO_BANK4_IO_CFG_2_3_CR LIBERO_SETTING_ALT_MSSIO_BANK4_IO_CFG_4_5_CR LIBERO_SETTING_ALT_MSSIO_BANK4_IO_CFG_6_7_CR LIBERO_SETTING_ALT_MSSIO_BANK4_IO_CFG_8_9_CR LIBERO_SETTING_ALT_MSSIO_BANK4_IO_CFG_10_11_CR LIBERO_SETTING_ALT_MSSIO_BANK4_IO_CFG_12_13_CR LIBERO_SETTING_ALT_MSSIO_VB2_CFG LIBERO_SETTING_ALT_MSSIO_VB4_CFG LIBERO_SETTING_APBBUS_CR LIBERO_SETTING_APB_SPLIT_VERSION LIBERO_SETTING_BEU_ENABLE_HART0 LIBERO_SETTING_BEU_ENABLE_HART1 LIBERO_SETTING_BEU_ENABLE_HART2 LIBERO_SETTING_BEU_ENABLE_HART3 LIBERO_SETTING_BEU_ENABLE_HART4 LIBERO_SETTING_BEU_LOCAL_ENABLE_HART0 LIBERO_SETTING_BEU_LOCAL_ENABLE_HART1 LIBERO_SETTING_BEU_LOCAL_ENABLE_HART2 LIBERO_SETTING_BEU_LOCAL_ENABLE_HART3 LIBERO_SETTING_BEU_LOCAL_ENABLE_HART4 LIBERO_SETTING_BEU_PLIC_ENABLE_HART0 LIBERO_SETTING_BEU_PLIC_ENABLE_HART1 LIBERO_SETTING_BEU_PLIC_ENABLE_HART2 LIBERO_SETTING_BEU_PLIC_ENABLE_HART3 LIBERO_SETTING_BEU_PLIC_ENABLE_HART4 LIBERO_SETTING_CA_BUS_RX_OFF_POST_TRAINING LIBERO_SETTING_CFG_ACTIVE_DQ_SEL LIBERO_SETTING_CFG_ADDR_MIRROR LIBERO_SETTING_CFG_ADVANCE_ACTIVATE_READY LIBERO_SETTING_CFG_AL_MODE LIBERO_SETTING_CFG_ASYNC_ODT LIBERO_SETTING_CFG_AUTO_REF_EN LIBERO_SETTING_CFG_AUTO_SR LIBERO_SETTING_CFG_AUTO_ZQ_CAL_EN LIBERO_SETTING_CFG_AXI_AUTO_PCH LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_0 LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI1_1 LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_0 LIBERO_SETTING_CFG_AXI_END_ADDRESS_AXI2_1 LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI1_0 LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI1_1 LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_0 LIBERO_SETTING_CFG_AXI_START_ADDRESS_AXI2_1 LIBERO_SETTING_CFG_BANKADDR_MAP_0 LIBERO_SETTING_CFG_BANKADDR_MAP_1 LIBERO_SETTING_CFG_BG_INTERLEAVE LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS0_0 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS0_1 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS1_0 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS1_1 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS2_0 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS2_1 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS3_0 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS3_1 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS4_0 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS4_1 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS5_0 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS5_1 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS6_0 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS6_1 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS7_0 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS7_1 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS8_0 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS8_1 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS9_0 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS9_1 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS10_0 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS10_1 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS11_0 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS11_1 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS12_0 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS12_1 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS13_0 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS13_1 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS14_0 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS14_1 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS15_0 LIBERO_SETTING_CFG_BIT_MAP_INDEX_CS15_1 LIBERO_SETTING_CFG_BL LIBERO_SETTING_CFG_BL_MODE LIBERO_SETTING_CFG_BT LIBERO_SETTING_CFG_BURST_RW_REFRESH_HOLDOFF LIBERO_SETTING_CFG_CAL_READ_PERIOD LIBERO_SETTING_CFG_CA_ODT LIBERO_SETTING_CFG_CA_PARITY_ERR_STATUS LIBERO_SETTING_CFG_CA_PARITY_LATENCY LIBERO_SETTING_CFG_CA_PARITY_PERSIST_ERR LIBERO_SETTING_CFG_CCD_L LIBERO_SETTING_CFG_CCD_S LIBERO_SETTING_CFG_CHIPADDR_MAP LIBERO_SETTING_CFG_CIDADDR_MAP LIBERO_SETTING_CFG_CKSRE LIBERO_SETTING_CFG_CKSRX LIBERO_SETTING_CFG_CL LIBERO_SETTING_CFG_COLADDR_MAP_0 LIBERO_SETTING_CFG_COLADDR_MAP_1 LIBERO_SETTING_CFG_COLADDR_MAP_2 LIBERO_SETTING_CFG_CRC_ERROR_CLEAR LIBERO_SETTING_CFG_CS_TO_CMDADDR_LATENCY LIBERO_SETTING_CFG_CTRLR_BUSY_ENABLE LIBERO_SETTING_CFG_CTRLR_BUSY_RESTART_HOLDOFF LIBERO_SETTING_CFG_CTRLR_BUSY_SEL LIBERO_SETTING_CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW LIBERO_SETTING_CFG_CTRLR_BUSY_TURN_OFF_DELAY LIBERO_SETTING_CFG_CTRLR_BUSY_VALUE LIBERO_SETTING_CFG_CTRLR_INIT_DISABLE LIBERO_SETTING_CFG_CTRLUPD_START_DELAY LIBERO_SETTING_CFG_CTRLUPD_TRIG LIBERO_SETTING_CFG_CWL LIBERO_SETTING_CFG_DATA_MASK LIBERO_SETTING_CFG_DATA_SEL LIBERO_SETTING_CFG_DATA_SEL_FIRST_ERROR LIBERO_SETTING_CFG_DBI_CL LIBERO_SETTING_CFG_DFI_DATA_BYTE_DISABLE LIBERO_SETTING_CFG_DFI_LVL_PATTERN LIBERO_SETTING_CFG_DFI_LVL_PERIODIC LIBERO_SETTING_CFG_DFI_LVL_SEL LIBERO_SETTING_CFG_DFI_PHYUPD_EN LIBERO_SETTING_CFG_DFI_T_CTRLUPD_MAX LIBERO_SETTING_CFG_DFI_T_CTRL_DELAY LIBERO_SETTING_CFG_DFI_T_DRAM_CLK_ENABLE LIBERO_SETTING_CFG_DFI_T_PHY_RDLAT LIBERO_SETTING_CFG_DFI_T_PHY_WRLAT LIBERO_SETTING_CFG_DFI_T_RDDATA_EN LIBERO_SETTING_CFG_DLL_DISABLE LIBERO_SETTING_CFG_DM_EN LIBERO_SETTING_CFG_DQ_ODT LIBERO_SETTING_CFG_DQ_WIDTH LIBERO_SETTING_CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH LIBERO_SETTING_CFG_DS LIBERO_SETTING_CFG_EARLY_RANK_TO_RD_START LIBERO_SETTING_CFG_EARLY_RANK_TO_WR_START LIBERO_SETTING_CFG_ECC_1BIT_INT_THRESH LIBERO_SETTING_CFG_ECC_BYPASS LIBERO_SETTING_CFG_ECC_CORRECTION_EN LIBERO_SETTING_CFG_EMR3 LIBERO_SETTING_CFG_ENABLE_BUS_HOLD_AXI1 LIBERO_SETTING_CFG_ENABLE_BUS_HOLD_AXI2 LIBERO_SETTING_CFG_EN_MASK LIBERO_SETTING_CFG_ERROR_GROUP_SEL LIBERO_SETTING_CFG_FAW LIBERO_SETTING_CFG_FAW_DLR LIBERO_SETTING_CFG_FINE_GRAN_REF_MODE LIBERO_SETTING_CFG_GEARDOWN_MODE LIBERO_SETTING_CFG_GENERATE_REFRESH_ON_SRX LIBERO_SETTING_CFG_IDLE_TIME_TO_POWER_DOWN LIBERO_SETTING_CFG_IDLE_TIME_TO_SELF_REFRESH LIBERO_SETTING_CFG_INIT_DURATION LIBERO_SETTING_CFG_INTRAPORT_REORDER_EN LIBERO_SETTING_CFG_INT_VREF_MON LIBERO_SETTING_CFG_LOOKAHEAD_ACT LIBERO_SETTING_CFG_LOOKAHEAD_PCH LIBERO_SETTING_CFG_LPDDR4_FSP_OP LIBERO_SETTING_CFG_LP_ASR LIBERO_SETTING_CFG_LRDIMM LIBERO_SETTING_CFG_MAINTAIN_COHERENCY LIBERO_SETTING_CFG_MANUAL_ADDRESS_MAP LIBERO_SETTING_CFG_MAX_PWR_DOWN_MODE LIBERO_SETTING_CFG_MB_AUTOPCH_COL_BIT_POS_HIGH LIBERO_SETTING_CFG_MB_AUTOPCH_COL_BIT_POS_LOW LIBERO_SETTING_CFG_MEMORY_TYPE LIBERO_SETTING_CFG_MEM_BANKBITS LIBERO_SETTING_CFG_MEM_COLBITS LIBERO_SETTING_CFG_MEM_ROWBITS LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_0 LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI1_1 LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI2_0 LIBERO_SETTING_CFG_MEM_START_ADDRESS_AXI2_1 LIBERO_SETTING_CFG_MIN_READ_IDLE LIBERO_SETTING_CFG_MIRROR_X16_BG0_BG1 LIBERO_SETTING_CFG_MOD LIBERO_SETTING_CFG_MPR_READ_FORMAT LIBERO_SETTING_CFG_MRD LIBERO_SETTING_CFG_MRR LIBERO_SETTING_CFG_MRRI LIBERO_SETTING_CFG_MRW LIBERO_SETTING_CFG_NIBBLE_DEVICES LIBERO_SETTING_CFG_NON_DBI_CL LIBERO_SETTING_CFG_NUM_CAL_READS LIBERO_SETTING_CFG_NUM_LOGICAL_RANKS_PER_3DS LIBERO_SETTING_CFG_NUM_RANKS LIBERO_SETTING_CFG_ODTD_CA LIBERO_SETTING_CFG_ODTE_CK LIBERO_SETTING_CFG_ODTE_CS LIBERO_SETTING_CFG_ODT_INBUF_4_PD LIBERO_SETTING_CFG_ODT_POWERDOWN LIBERO_SETTING_CFG_ODT_RD_MAP_CS0 LIBERO_SETTING_CFG_ODT_RD_MAP_CS1 LIBERO_SETTING_CFG_ODT_RD_MAP_CS2 LIBERO_SETTING_CFG_ODT_RD_MAP_CS3 LIBERO_SETTING_CFG_ODT_RD_MAP_CS4 LIBERO_SETTING_CFG_ODT_RD_MAP_CS5 LIBERO_SETTING_CFG_ODT_RD_MAP_CS6 LIBERO_SETTING_CFG_ODT_RD_MAP_CS7 LIBERO_SETTING_CFG_ODT_RD_TURN_OFF LIBERO_SETTING_CFG_ODT_RD_TURN_ON LIBERO_SETTING_CFG_ODT_WR_MAP_CS0 LIBERO_SETTING_CFG_ODT_WR_MAP_CS1 LIBERO_SETTING_CFG_ODT_WR_MAP_CS2 LIBERO_SETTING_CFG_ODT_WR_MAP_CS3 LIBERO_SETTING_CFG_ODT_WR_MAP_CS4 LIBERO_SETTING_CFG_ODT_WR_MAP_CS5 LIBERO_SETTING_CFG_ODT_WR_MAP_CS6 LIBERO_SETTING_CFG_ODT_WR_MAP_CS7 LIBERO_SETTING_CFG_ODT_WR_TURN_OFF LIBERO_SETTING_CFG_ODT_WR_TURN_ON LIBERO_SETTING_CFG_ONLY_SRANK_CMDS LIBERO_SETTING_CFG_PARITY_RDIMM_DELAY LIBERO_SETTING_CFG_PASR LIBERO_SETTING_CFG_PASR_BANK LIBERO_SETTING_CFG_PASR_SEG LIBERO_SETTING_CFG_PER_DRAM_ADDR_EN LIBERO_SETTING_CFG_PHYUPD_ACK_DELAY LIBERO_SETTING_CFG_POST_TRIG_CYCS LIBERO_SETTING_CFG_PRE_TRIG_CYCS LIBERO_SETTING_CFG_PU_CAL LIBERO_SETTING_CFG_QOFF LIBERO_SETTING_CFG_QUAD_RANK LIBERO_SETTING_CFG_Q_AGE_LIMIT LIBERO_SETTING_CFG_RAS LIBERO_SETTING_CFG_RC LIBERO_SETTING_CFG_RCD LIBERO_SETTING_CFG_RCD_STAB LIBERO_SETTING_CFG_RDIMM_BSIDE_INVERT LIBERO_SETTING_CFG_RDIMM_LAT LIBERO_SETTING_CFG_RD_POSTAMBLE LIBERO_SETTING_CFG_RD_PREAMBLE LIBERO_SETTING_CFG_RD_PREAMB_TOGGLE LIBERO_SETTING_CFG_RD_PREAMB_TRN_MODE LIBERO_SETTING_CFG_READ_DBI LIBERO_SETTING_CFG_READ_TO_READ LIBERO_SETTING_CFG_READ_TO_READ_ODT LIBERO_SETTING_CFG_READ_TO_WRITE LIBERO_SETTING_CFG_READ_TO_WRITE_ODT LIBERO_SETTING_CFG_REFRESH_DURING_PHY_TRAINING LIBERO_SETTING_CFG_REF_PER LIBERO_SETTING_CFG_REGDIMM LIBERO_SETTING_CFG_REORDER_EN LIBERO_SETTING_CFG_REORDER_QUEUE_EN LIBERO_SETTING_CFG_REORDER_RW_ONLY LIBERO_SETTING_CFG_RFC LIBERO_SETTING_CFG_RFC1 LIBERO_SETTING_CFG_RFC2 LIBERO_SETTING_CFG_RFC4 LIBERO_SETTING_CFG_RFC_DLR1 LIBERO_SETTING_CFG_RFC_DLR2 LIBERO_SETTING_CFG_RFC_DLR4 LIBERO_SETTING_CFG_RL LIBERO_SETTING_CFG_RMW_EN LIBERO_SETTING_CFG_ROWADDR_MAP_0 LIBERO_SETTING_CFG_ROWADDR_MAP_1 LIBERO_SETTING_CFG_ROWADDR_MAP_2 LIBERO_SETTING_CFG_ROWADDR_MAP_3 LIBERO_SETTING_CFG_RO_CLOSED_PAGE_POLICY LIBERO_SETTING_CFG_RO_PRIORITY_EN LIBERO_SETTING_CFG_RP LIBERO_SETTING_CFG_RRD LIBERO_SETTING_CFG_RRD_DLR LIBERO_SETTING_CFG_RRD_L LIBERO_SETTING_CFG_RRD_S LIBERO_SETTING_CFG_RTP LIBERO_SETTING_CFG_RTT LIBERO_SETTING_CFG_RTT_PARK LIBERO_SETTING_CFG_RTT_WR LIBERO_SETTING_CFG_SOC_ODT LIBERO_SETTING_CFG_SRT LIBERO_SETTING_CFG_SR_ABORT LIBERO_SETTING_CFG_STARTUP_DELAY LIBERO_SETTING_CFG_STARVE_TIMEOUT_P0 LIBERO_SETTING_CFG_STARVE_TIMEOUT_P1 LIBERO_SETTING_CFG_STARVE_TIMEOUT_P2 LIBERO_SETTING_CFG_STARVE_TIMEOUT_P3 LIBERO_SETTING_CFG_STARVE_TIMEOUT_P4 LIBERO_SETTING_CFG_STARVE_TIMEOUT_P5 LIBERO_SETTING_CFG_STARVE_TIMEOUT_P6 LIBERO_SETTING_CFG_STARVE_TIMEOUT_P7 LIBERO_SETTING_CFG_TDQS LIBERO_SETTING_CFG_TEMP_CTRL_REF_MODE LIBERO_SETTING_CFG_TEMP_CTRL_REF_RANGE LIBERO_SETTING_CFG_TEMP_SENSOR_READOUT LIBERO_SETTING_CFG_THERMAL_OFFSET LIBERO_SETTING_CFG_TRIG_ERR_MASK_0 LIBERO_SETTING_CFG_TRIG_ERR_MASK_1 LIBERO_SETTING_CFG_TRIG_ERR_MASK_2 LIBERO_SETTING_CFG_TRIG_ERR_MASK_3 LIBERO_SETTING_CFG_TRIG_ERR_MASK_4 LIBERO_SETTING_CFG_TRIG_MASK LIBERO_SETTING_CFG_TRIG_MODE LIBERO_SETTING_CFG_TRIG_MT_ADDR_0 LIBERO_SETTING_CFG_TRIG_MT_ADDR_1 LIBERO_SETTING_CFG_TWO_T LIBERO_SETTING_CFG_TWO_T_SEL_CYCLE LIBERO_SETTING_CFG_VRCG_DISABLE LIBERO_SETTING_CFG_VRCG_ENABLE LIBERO_SETTING_CFG_VREFDQ_TRN_ENABLE LIBERO_SETTING_CFG_VREFDQ_TRN_RANGE LIBERO_SETTING_CFG_VREFDQ_TRN_VALUE LIBERO_SETTING_CFG_WL LIBERO_SETTING_CFG_WR LIBERO_SETTING_CFG_WRITE_CRC LIBERO_SETTING_CFG_WRITE_DBI LIBERO_SETTING_CFG_WRITE_LATENCY_SET LIBERO_SETTING_CFG_WRITE_TO_READ LIBERO_SETTING_CFG_WRITE_TO_READ_ODT LIBERO_SETTING_CFG_WRITE_TO_WRITE LIBERO_SETTING_CFG_WRITE_TO_WRITE_ODT LIBERO_SETTING_CFG_WR_CMD_LAT_CRC_DM LIBERO_SETTING_CFG_WR_CRC_DM LIBERO_SETTING_CFG_WR_POSTAMBLE LIBERO_SETTING_CFG_WR_PREAMBLE LIBERO_SETTING_CFG_WTR LIBERO_SETTING_CFG_WTR_L LIBERO_SETTING_CFG_WTR_L_CRC_DM LIBERO_SETTING_CFG_WTR_S LIBERO_SETTING_CFG_WTR_S_CRC_DM LIBERO_SETTING_CFG_XP LIBERO_SETTING_CFG_XPR LIBERO_SETTING_CFG_XS LIBERO_SETTING_CFG_XSDLL LIBERO_SETTING_CFG_XSR LIBERO_SETTING_CFG_ZQINIT_CAL_DURATION LIBERO_SETTING_CFG_ZQLATCH_DURATION LIBERO_SETTING_CFG_ZQ_CAL_DURATION LIBERO_SETTING_CFG_ZQ_CAL_L_DURATION LIBERO_SETTING_CFG_ZQ_CAL_PER LIBERO_SETTING_CFG_ZQ_CAL_R_DURATION LIBERO_SETTING_CFG_ZQ_CAL_S_DURATION LIBERO_SETTING_CFG_ZQ_CAL_TYPE LIBERO_SETTING_CH0_CNTL LIBERO_SETTING_CH1_CNTL LIBERO_SETTING_CLK_CNTL LIBERO_SETTING_CONFIGURED_PERIPHERALS LIBERO_SETTING_CONTEXT_A_EN LIBERO_SETTING_CONTEXT_A_EN_FIC LIBERO_SETTING_CONTEXT_A_HART_EN LIBERO_SETTING_CONTEXT_B_EN LIBERO_SETTING_CONTEXT_B_EN_FIC LIBERO_SETTING_CONTEXT_B_HART_EN LIBERO_SETTING_CRYPTO_CR_INFO LIBERO_SETTING_CRYPTO_MPU_CFG_PMP0 LIBERO_SETTING_CRYPTO_MPU_CFG_PMP1 LIBERO_SETTING_CRYPTO_MPU_CFG_PMP2 LIBERO_SETTING_CRYPTO_MPU_CFG_PMP3 LIBERO_SETTING_CTRLR_INIT LIBERO_SETTING_CTRLR_SOFT_RESET_N LIBERO_SETTING_DATA_LANES_USED LIBERO_SETTING_DDRPHY_MODE LIBERO_SETTING_DDRPHY_MODE_OFF LIBERO_SETTING_DDR_32_CACHE LIBERO_SETTING_DDR_32_CACHE_SIZE LIBERO_SETTING_DDR_32_NON_CACHE LIBERO_SETTING_DDR_32_NON_CACHE_SIZE LIBERO_SETTING_DDR_32_WCB LIBERO_SETTING_DDR_32_WCB_SIZE LIBERO_SETTING_DDR_64_CACHE LIBERO_SETTING_DDR_64_CACHE_SIZE LIBERO_SETTING_DDR_64_NON_CACHE LIBERO_SETTING_DDR_64_NON_CACHE_SIZE LIBERO_SETTING_DDR_64_WCB LIBERO_SETTING_DDR_64_WCB_SIZE LIBERO_SETTING_DDR_CLK LIBERO_SETTING_DDR_IOC_REG0 LIBERO_SETTING_DDR_PLL_CAL LIBERO_SETTING_DDR_PLL_CTRL LIBERO_SETTING_DDR_PLL_CTRL2 LIBERO_SETTING_DDR_PLL_DIV_0_1 LIBERO_SETTING_DDR_PLL_DIV_2_3 LIBERO_SETTING_DDR_PLL_FRACN LIBERO_SETTING_DDR_PLL_PHADJ LIBERO_SETTING_DDR_PLL_REF_FB LIBERO_SETTING_DDR_SOFT_RESET LIBERO_SETTING_DDR_SSCG_REG_0 LIBERO_SETTING_DDR_SSCG_REG_1 LIBERO_SETTING_DDR_SSCG_REG_2 LIBERO_SETTING_DDR_SSCG_REG_3 LIBERO_SETTING_DESIGN_NAME LIBERO_SETTING_DPC_BITS LIBERO_SETTING_DPC_BITS_OFF_MODE LIBERO_SETTING_DYN_CNTL LIBERO_SETTING_ENVM_MSS_END_PAGE LIBERO_SETTING_ENVM_MSS_START_PAGE LIBERO_SETTING_FIC0_MPU_CFG_PMP0 LIBERO_SETTING_FIC0_MPU_CFG_PMP1 LIBERO_SETTING_FIC0_MPU_CFG_PMP2 LIBERO_SETTING_FIC0_MPU_CFG_PMP3 LIBERO_SETTING_FIC0_MPU_CFG_PMP4 LIBERO_SETTING_FIC0_MPU_CFG_PMP5 LIBERO_SETTING_FIC0_MPU_CFG_PMP6 LIBERO_SETTING_FIC0_MPU_CFG_PMP7 LIBERO_SETTING_FIC0_MPU_CFG_PMP8 LIBERO_SETTING_FIC0_MPU_CFG_PMP9 LIBERO_SETTING_FIC0_MPU_CFG_PMP10 LIBERO_SETTING_FIC0_MPU_CFG_PMP11 LIBERO_SETTING_FIC0_MPU_CFG_PMP12 LIBERO_SETTING_FIC0_MPU_CFG_PMP13 LIBERO_SETTING_FIC0_MPU_CFG_PMP14 LIBERO_SETTING_FIC0_MPU_CFG_PMP15 LIBERO_SETTING_FIC1_MPU_CFG_PMP0 LIBERO_SETTING_FIC1_MPU_CFG_PMP1 LIBERO_SETTING_FIC1_MPU_CFG_PMP2 LIBERO_SETTING_FIC1_MPU_CFG_PMP3 LIBERO_SETTING_FIC1_MPU_CFG_PMP4 LIBERO_SETTING_FIC1_MPU_CFG_PMP5 LIBERO_SETTING_FIC1_MPU_CFG_PMP6 LIBERO_SETTING_FIC1_MPU_CFG_PMP7 LIBERO_SETTING_FIC1_MPU_CFG_PMP8 LIBERO_SETTING_FIC1_MPU_CFG_PMP9 LIBERO_SETTING_FIC1_MPU_CFG_PMP10 LIBERO_SETTING_FIC1_MPU_CFG_PMP11 LIBERO_SETTING_FIC1_MPU_CFG_PMP12 LIBERO_SETTING_FIC1_MPU_CFG_PMP13 LIBERO_SETTING_FIC1_MPU_CFG_PMP14 LIBERO_SETTING_FIC1_MPU_CFG_PMP15 LIBERO_SETTING_FIC2_MPU_CFG_PMP0 LIBERO_SETTING_FIC2_MPU_CFG_PMP1 LIBERO_SETTING_FIC2_MPU_CFG_PMP2 LIBERO_SETTING_FIC2_MPU_CFG_PMP3 LIBERO_SETTING_FIC2_MPU_CFG_PMP4 LIBERO_SETTING_FIC2_MPU_CFG_PMP5 LIBERO_SETTING_FIC2_MPU_CFG_PMP6 LIBERO_SETTING_FIC2_MPU_CFG_PMP7 LIBERO_SETTING_GEM0_MPU_CFG_PMP0 LIBERO_SETTING_GEM0_MPU_CFG_PMP1 LIBERO_SETTING_GEM0_MPU_CFG_PMP2 LIBERO_SETTING_GEM0_MPU_CFG_PMP3 LIBERO_SETTING_GEM0_MPU_CFG_PMP4 LIBERO_SETTING_GEM0_MPU_CFG_PMP5 LIBERO_SETTING_GEM0_MPU_CFG_PMP6 LIBERO_SETTING_GEM0_MPU_CFG_PMP7 LIBERO_SETTING_GEM1_MPU_CFG_PMP0 LIBERO_SETTING_GEM1_MPU_CFG_PMP1 LIBERO_SETTING_GEM1_MPU_CFG_PMP2 LIBERO_SETTING_GEM1_MPU_CFG_PMP3 LIBERO_SETTING_GEM1_MPU_CFG_PMP4 LIBERO_SETTING_GEM1_MPU_CFG_PMP5 LIBERO_SETTING_GEM1_MPU_CFG_PMP6 LIBERO_SETTING_GEM1_MPU_CFG_PMP7 LIBERO_SETTING_GENERATION_DATE LIBERO_SETTING_GPIO_CR LIBERO_SETTING_GPIO_INTERRUPT_FAB_CR LIBERO_SETTING_HART0_CSR_PMPADDR0 LIBERO_SETTING_HART0_CSR_PMPADDR1 LIBERO_SETTING_HART0_CSR_PMPADDR2 LIBERO_SETTING_HART0_CSR_PMPADDR3 LIBERO_SETTING_HART0_CSR_PMPADDR4 LIBERO_SETTING_HART0_CSR_PMPADDR5 LIBERO_SETTING_HART0_CSR_PMPADDR6 LIBERO_SETTING_HART0_CSR_PMPADDR7 LIBERO_SETTING_HART0_CSR_PMPADDR8 LIBERO_SETTING_HART0_CSR_PMPADDR9 LIBERO_SETTING_HART0_CSR_PMPADDR10 LIBERO_SETTING_HART0_CSR_PMPADDR11 LIBERO_SETTING_HART0_CSR_PMPADDR12 LIBERO_SETTING_HART0_CSR_PMPADDR13 LIBERO_SETTING_HART0_CSR_PMPADDR14 LIBERO_SETTING_HART0_CSR_PMPADDR15 LIBERO_SETTING_HART0_CSR_PMPCFG0 LIBERO_SETTING_HART0_CSR_PMPCFG2 LIBERO_SETTING_HART1_CSR_PMPADDR0 LIBERO_SETTING_HART1_CSR_PMPADDR1 LIBERO_SETTING_HART1_CSR_PMPADDR2 LIBERO_SETTING_HART1_CSR_PMPADDR3 LIBERO_SETTING_HART1_CSR_PMPADDR4 LIBERO_SETTING_HART1_CSR_PMPADDR5 LIBERO_SETTING_HART1_CSR_PMPADDR6 LIBERO_SETTING_HART1_CSR_PMPADDR7 LIBERO_SETTING_HART1_CSR_PMPADDR8 LIBERO_SETTING_HART1_CSR_PMPADDR9 LIBERO_SETTING_HART1_CSR_PMPADDR10 LIBERO_SETTING_HART1_CSR_PMPADDR11 LIBERO_SETTING_HART1_CSR_PMPADDR12 LIBERO_SETTING_HART1_CSR_PMPADDR13 LIBERO_SETTING_HART1_CSR_PMPADDR14 LIBERO_SETTING_HART1_CSR_PMPADDR15 LIBERO_SETTING_HART1_CSR_PMPCFG0 LIBERO_SETTING_HART1_CSR_PMPCFG2 LIBERO_SETTING_HART2_CSR_PMPADDR0 LIBERO_SETTING_HART2_CSR_PMPADDR1 LIBERO_SETTING_HART2_CSR_PMPADDR2 LIBERO_SETTING_HART2_CSR_PMPADDR3 LIBERO_SETTING_HART2_CSR_PMPADDR4 LIBERO_SETTING_HART2_CSR_PMPADDR5 LIBERO_SETTING_HART2_CSR_PMPADDR6 LIBERO_SETTING_HART2_CSR_PMPADDR7 LIBERO_SETTING_HART2_CSR_PMPADDR8 LIBERO_SETTING_HART2_CSR_PMPADDR9 LIBERO_SETTING_HART2_CSR_PMPADDR10 LIBERO_SETTING_HART2_CSR_PMPADDR11 LIBERO_SETTING_HART2_CSR_PMPADDR12 LIBERO_SETTING_HART2_CSR_PMPADDR13 LIBERO_SETTING_HART2_CSR_PMPADDR14 LIBERO_SETTING_HART2_CSR_PMPADDR15 LIBERO_SETTING_HART2_CSR_PMPCFG0 LIBERO_SETTING_HART2_CSR_PMPCFG2 LIBERO_SETTING_HART3_CSR_PMPADDR0 LIBERO_SETTING_HART3_CSR_PMPADDR1 LIBERO_SETTING_HART3_CSR_PMPADDR2 LIBERO_SETTING_HART3_CSR_PMPADDR3 LIBERO_SETTING_HART3_CSR_PMPADDR4 LIBERO_SETTING_HART3_CSR_PMPADDR5 LIBERO_SETTING_HART3_CSR_PMPADDR6 LIBERO_SETTING_HART3_CSR_PMPADDR7 LIBERO_SETTING_HART3_CSR_PMPADDR8 LIBERO_SETTING_HART3_CSR_PMPADDR9 LIBERO_SETTING_HART3_CSR_PMPADDR10 LIBERO_SETTING_HART3_CSR_PMPADDR11 LIBERO_SETTING_HART3_CSR_PMPADDR12 LIBERO_SETTING_HART3_CSR_PMPADDR13 LIBERO_SETTING_HART3_CSR_PMPADDR14 LIBERO_SETTING_HART3_CSR_PMPADDR15 LIBERO_SETTING_HART3_CSR_PMPCFG0 LIBERO_SETTING_HART3_CSR_PMPCFG2 LIBERO_SETTING_HART4_CSR_PMPADDR0 LIBERO_SETTING_HART4_CSR_PMPADDR1 LIBERO_SETTING_HART4_CSR_PMPADDR2 LIBERO_SETTING_HART4_CSR_PMPADDR3 LIBERO_SETTING_HART4_CSR_PMPADDR4 LIBERO_SETTING_HART4_CSR_PMPADDR5 LIBERO_SETTING_HART4_CSR_PMPADDR6 LIBERO_SETTING_HART4_CSR_PMPADDR7 LIBERO_SETTING_HART4_CSR_PMPADDR8 LIBERO_SETTING_HART4_CSR_PMPADDR9 LIBERO_SETTING_HART4_CSR_PMPADDR10 LIBERO_SETTING_HART4_CSR_PMPADDR11 LIBERO_SETTING_HART4_CSR_PMPADDR12 LIBERO_SETTING_HART4_CSR_PMPADDR13 LIBERO_SETTING_HART4_CSR_PMPADDR14 LIBERO_SETTING_HART4_CSR_PMPADDR15 LIBERO_SETTING_HART4_CSR_PMPCFG0 LIBERO_SETTING_HART4_CSR_PMPCFG2 LIBERO_SETTING_HEADER_GENERATOR_VERSION LIBERO_SETTING_HEADER_GENERATOR_VERSION_MAJOR LIBERO_SETTING_HEADER_GENERATOR_VERSION_MINOR LIBERO_SETTING_HEADER_GENERATOR_VERSION_PATCH LIBERO_SETTING_INIT_AUTOINIT_DISABLE LIBERO_SETTING_INIT_CAL_L_ADDR_0 LIBERO_SETTING_INIT_CAL_L_ADDR_1 LIBERO_SETTING_INIT_CAL_L_B_SIZE LIBERO_SETTING_INIT_CAL_L_R_REQ LIBERO_SETTING_INIT_CAL_SELECT LIBERO_SETTING_INIT_CA_PARITY_ERROR_GEN_CMD LIBERO_SETTING_INIT_CA_PARITY_ERROR_GEN_REQ LIBERO_SETTING_INIT_CS LIBERO_SETTING_INIT_DFI_DRAM_CLK_DISABLE LIBERO_SETTING_INIT_DFI_LP_CTRL_REQ LIBERO_SETTING_INIT_DFI_LP_DATA_REQ LIBERO_SETTING_INIT_DFI_LP_WAKEUP LIBERO_SETTING_INIT_DISABLE_CKE LIBERO_SETTING_INIT_FORCE_RESET LIBERO_SETTING_INIT_FORCE_WRITE LIBERO_SETTING_INIT_FORCE_WRITE_CS LIBERO_SETTING_INIT_FORCE_WRITE_DATA_0 LIBERO_SETTING_INIT_GEARDOWN_EN LIBERO_SETTING_INIT_MEMORY_RESET_MASK LIBERO_SETTING_INIT_MRR_MODE LIBERO_SETTING_INIT_MR_ADDR LIBERO_SETTING_INIT_MR_WR_DATA LIBERO_SETTING_INIT_MR_WR_MASK LIBERO_SETTING_INIT_MR_W_REQ LIBERO_SETTING_INIT_NOP LIBERO_SETTING_INIT_ODT_FORCE_EN LIBERO_SETTING_INIT_ODT_FORCE_RANK LIBERO_SETTING_INIT_PDA_MR_W_REQ LIBERO_SETTING_INIT_PDA_NIBBLE_SELECT LIBERO_SETTING_INIT_POWER_DOWN LIBERO_SETTING_INIT_PRECHARGE_ALL LIBERO_SETTING_INIT_RDIMM_COMPLETE LIBERO_SETTING_INIT_RD_DQCAL LIBERO_SETTING_INIT_READ_CAPTURE_ADDR LIBERO_SETTING_INIT_REFRESH LIBERO_SETTING_INIT_RWFIFO LIBERO_SETTING_INIT_SELF_REFRESH LIBERO_SETTING_INIT_START_DQSOSC LIBERO_SETTING_INIT_STOP_DQSOSC LIBERO_SETTING_INIT_WRITE_DATA_1B_ECC_ERROR_GEN LIBERO_SETTING_INIT_WRITE_DATA_2B_ECC_ERROR_GEN LIBERO_SETTING_INIT_ZQ_CAL_REQ LIBERO_SETTING_INIT_ZQ_CAL_START LIBERO_SETTING_IOMUX0_CR LIBERO_SETTING_IOMUX1_CR LIBERO_SETTING_IOMUX2_CR LIBERO_SETTING_IOMUX3_CR LIBERO_SETTING_IOMUX4_CR LIBERO_SETTING_IOMUX5_CR LIBERO_SETTING_IOMUX6_CR LIBERO_SETTING_L2_SHUTDOWN_CR LIBERO_SETTING_MANUAL_REF_CLK_PHASE_OFFSET LIBERO_SETTING_MAX_MANUAL_REF_CLK_PHASE_OFFSET LIBERO_SETTING_MAX_RPC_156_VALUE LIBERO_SETTING_MEM_CONFIGS_ENABLED LIBERO_SETTING_MIN_MANUAL_REF_CLK_PHASE_OFFSET LIBERO_SETTING_MIN_RPC_156_VALUE LIBERO_SETTING_MMC_MPU_CFG_PMP0 LIBERO_SETTING_MMC_MPU_CFG_PMP1 LIBERO_SETTING_MMC_MPU_CFG_PMP2 LIBERO_SETTING_MMC_MPU_CFG_PMP3 LIBERO_SETTING_MPFS_PART LIBERO_SETTING_MSSIO_BANK2_CFG_CR LIBERO_SETTING_MSSIO_BANK2_IO_CFG_0_1_CR LIBERO_SETTING_MSSIO_BANK2_IO_CFG_2_3_CR LIBERO_SETTING_MSSIO_BANK2_IO_CFG_4_5_CR LIBERO_SETTING_MSSIO_BANK2_IO_CFG_6_7_CR LIBERO_SETTING_MSSIO_BANK2_IO_CFG_8_9_CR LIBERO_SETTING_MSSIO_BANK2_IO_CFG_10_11_CR LIBERO_SETTING_MSSIO_BANK2_IO_CFG_12_13_CR LIBERO_SETTING_MSSIO_BANK2_IO_CFG_14_15_CR LIBERO_SETTING_MSSIO_BANK2_IO_CFG_16_17_CR LIBERO_SETTING_MSSIO_BANK2_IO_CFG_18_19_CR LIBERO_SETTING_MSSIO_BANK2_IO_CFG_20_21_CR LIBERO_SETTING_MSSIO_BANK2_IO_CFG_22_23_CR LIBERO_SETTING_MSSIO_BANK4_CFG_CR LIBERO_SETTING_MSSIO_BANK4_IO_CFG_0_1_CR LIBERO_SETTING_MSSIO_BANK4_IO_CFG_2_3_CR LIBERO_SETTING_MSSIO_BANK4_IO_CFG_4_5_CR LIBERO_SETTING_MSSIO_BANK4_IO_CFG_6_7_CR LIBERO_SETTING_MSSIO_BANK4_IO_CFG_8_9_CR LIBERO_SETTING_MSSIO_BANK4_IO_CFG_10_11_CR LIBERO_SETTING_MSSIO_BANK4_IO_CFG_12_13_CR LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS LIBERO_SETTING_MSSIO_VB2_CFG LIBERO_SETTING_MSSIO_VB4_CFG LIBERO_SETTING_MSS_APB_AHB_CLK LIBERO_SETTING_MSS_AXI_CLK LIBERO_SETTING_MSS_BCLKMUX LIBERO_SETTING_MSS_CLKS_VERSION LIBERO_SETTING_MSS_CLOCK_CONFIG_CR LIBERO_SETTING_MSS_CLOCK_CONFIG_CR_LOW LIBERO_SETTING_MSS_CLOCK_CONFIG_CR_MED LIBERO_SETTING_MSS_CONFIGURATOR_VERSION LIBERO_SETTING_MSS_COREPLEX_CPU_CLK LIBERO_SETTING_MSS_ENVM_CR LIBERO_SETTING_MSS_EXT_SGMII_REF_CLK LIBERO_SETTING_MSS_FMETER_ADDR LIBERO_SETTING_MSS_FMETER_DATAR LIBERO_SETTING_MSS_FMETER_DATAW LIBERO_SETTING_MSS_IMIRROR_TRIM LIBERO_SETTING_MSS_MSSCLKMUX LIBERO_SETTING_MSS_PLL_CAL LIBERO_SETTING_MSS_PLL_CKMUX LIBERO_SETTING_MSS_PLL_CTRL LIBERO_SETTING_MSS_PLL_CTRL2 LIBERO_SETTING_MSS_PLL_DIV_0_1 LIBERO_SETTING_MSS_PLL_DIV_2_3 LIBERO_SETTING_MSS_PLL_FRACN LIBERO_SETTING_MSS_PLL_PHADJ LIBERO_SETTING_MSS_PLL_REF_FB LIBERO_SETTING_MSS_RTC_CLOCK_CR LIBERO_SETTING_MSS_RTC_TOGGLE_CLK LIBERO_SETTING_MSS_SPARE0 LIBERO_SETTING_MSS_SSCG_REG_0 LIBERO_SETTING_MSS_SSCG_REG_1 LIBERO_SETTING_MSS_SSCG_REG_2 LIBERO_SETTING_MSS_SSCG_REG_3 LIBERO_SETTING_MSS_SYSREG_CLKS_VERSION LIBERO_SETTING_MSS_SYSTEM_CLK LIBERO_SETTING_MSS_TEST_CTRL LIBERO_SETTING_MTC_ACQ_ADDR LIBERO_SETTING_MTC_ACQ_WR_DATA_0 LIBERO_SETTING_MTC_ACQ_WR_DATA_1 LIBERO_SETTING_MTC_ACQ_WR_DATA_2 LIBERO_SETTING_NUM_SCRATCH_PAD_WAYS LIBERO_SETTING_PHY_CLR_DFI_LVL_PERIODIC LIBERO_SETTING_PHY_DFI_INIT_START LIBERO_SETTING_PHY_ENCODED_QUAD_CS LIBERO_SETTING_PHY_EYE_PAT LIBERO_SETTING_PHY_EYE_TRAIN_DELAY LIBERO_SETTING_PHY_GATE_TRAIN_DELAY LIBERO_SETTING_PHY_HALF_CLK_DLY_ENABLE LIBERO_SETTING_PHY_INDPNDT_TRAINING LIBERO_SETTING_PHY_LPDDR_DQ_CAL_PAT LIBERO_SETTING_PHY_PC_RANK LIBERO_SETTING_PHY_RANKS_TO_TRAIN LIBERO_SETTING_PHY_READ_REQUEST LIBERO_SETTING_PHY_RESET_CONTROL LIBERO_SETTING_PHY_START_RECAL LIBERO_SETTING_PHY_TRAIN_STEP_ENABLE LIBERO_SETTING_PHY_WRITE_LEVEL_DELAY LIBERO_SETTING_PHY_WRITE_REQUEST LIBERO_SETTING_PLL_CNTL LIBERO_SETTING_PVT_STAT LIBERO_SETTING_RECAL_CNTL LIBERO_SETTING_REFCLK_DDR3L_1067_NUM_OFFSETS LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_0 LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_1 LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_2 LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_3 LIBERO_SETTING_REFCLK_DDR3L_1333_NUM_OFFSETS LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_0 LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_1 LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_2 LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_3 LIBERO_SETTING_REFCLK_DDR3_1067_NUM_OFFSETS LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_0 LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_1 LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_2 LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_3 LIBERO_SETTING_REFCLK_DDR3_1333_NUM_OFFSETS LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_0 LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_1 LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_2 LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_3 LIBERO_SETTING_REFCLK_DDR4_1333_NUM_OFFSETS LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_0 LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_1 LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_2 LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_3 LIBERO_SETTING_REFCLK_DDR4_1600_NUM_OFFSETS LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_0 LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_1 LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_2 LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_3 LIBERO_SETTING_REFCLK_LPDDR3_1333_NUM_OFFSETS LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_0 LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_1 LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_2 LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_3 LIBERO_SETTING_REFCLK_LPDDR3_1600_NUM_OFFSETS LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_0 LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_1 LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_2 LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_3 LIBERO_SETTING_REFCLK_LPDDR4_1333_NUM_OFFSETS LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_0 LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_1 LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_2 LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_3 LIBERO_SETTING_REFCLK_LPDDR4_1600_NUM_OFFSETS LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_0 LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_1 LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_2 LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_3 LIBERO_SETTING_RESERVED_ENVM LIBERO_SETTING_RESERVED_ENVM_SIZE LIBERO_SETTING_RESERVED_SNVM LIBERO_SETTING_RESERVED_SNVM_SIZE LIBERO_SETTING_RESET_VECTOR_HART0 LIBERO_SETTING_RESET_VECTOR_HART0_SIZE LIBERO_SETTING_RESET_VECTOR_HART1 LIBERO_SETTING_RESET_VECTOR_HART2 LIBERO_SETTING_RESET_VECTOR_HART3 LIBERO_SETTING_RESET_VECTOR_HART4 LIBERO_SETTING_RESET_VECTOR_HART1_SIZE LIBERO_SETTING_RESET_VECTOR_HART2_SIZE LIBERO_SETTING_RESET_VECTOR_HART3_SIZE LIBERO_SETTING_RESET_VECTOR_HART4_SIZE LIBERO_SETTING_RPC235_WPD_ADD_CMD0 LIBERO_SETTING_RPC236_WPD_ADD_CMD1 LIBERO_SETTING_RPC237_WPD_ADD_CMD2 LIBERO_SETTING_RPC238_WPD_DATA0 LIBERO_SETTING_RPC239_WPD_DATA1 LIBERO_SETTING_RPC240_WPD_DATA2 LIBERO_SETTING_RPC241_WPD_DATA3 LIBERO_SETTING_RPC242_WPD_ECC LIBERO_SETTING_RPC243_WPU_ADD_CMD0 LIBERO_SETTING_RPC244_WPU_ADD_CMD1 LIBERO_SETTING_RPC245_WPU_ADD_CMD2 LIBERO_SETTING_RPC246_WPU_DATA0 LIBERO_SETTING_RPC247_WPU_DATA1 LIBERO_SETTING_RPC248_WPU_DATA2 LIBERO_SETTING_RPC249_WPU_DATA3 LIBERO_SETTING_RPC250_WPU_ECC LIBERO_SETTING_RPC_156_VALUE LIBERO_SETTING_RPC_EN_ADDCMD0_OVRT9 LIBERO_SETTING_RPC_EN_ADDCMD1_OVRT10 LIBERO_SETTING_RPC_EN_ADDCMD2_OVRT11 LIBERO_SETTING_RPC_EN_DATA0_OVRT12 LIBERO_SETTING_RPC_EN_DATA1_OVRT13 LIBERO_SETTING_RPC_EN_DATA2_OVRT14 LIBERO_SETTING_RPC_EN_DATA3_OVRT15 LIBERO_SETTING_RPC_EN_ECC_OVRT16 LIBERO_SETTING_RPC_IBUFMD_ADDCMD LIBERO_SETTING_RPC_IBUFMD_CLK LIBERO_SETTING_RPC_IBUFMD_DQ LIBERO_SETTING_RPC_IBUFMD_DQS LIBERO_SETTING_RPC_ODT_ADDCMD LIBERO_SETTING_RPC_ODT_CLK LIBERO_SETTING_RPC_ODT_DQ LIBERO_SETTING_RPC_ODT_DQS LIBERO_SETTING_RPC_ODT_STATIC_ADDCMD LIBERO_SETTING_RPC_ODT_STATIC_CLKN LIBERO_SETTING_RPC_ODT_STATIC_CLKP LIBERO_SETTING_RPC_ODT_STATIC_DQ LIBERO_SETTING_RPC_ODT_STATIC_DQS LIBERO_SETTING_RPC_SPARE0_DQ LIBERO_SETTING_SCB_MPU_CFG_PMP0 LIBERO_SETTING_SCB_MPU_CFG_PMP1 LIBERO_SETTING_SCB_MPU_CFG_PMP2 LIBERO_SETTING_SCB_MPU_CFG_PMP3 LIBERO_SETTING_SCB_MPU_CFG_PMP4 LIBERO_SETTING_SCB_MPU_CFG_PMP5 LIBERO_SETTING_SCB_MPU_CFG_PMP6 LIBERO_SETTING_SCB_MPU_CFG_PMP7 LIBERO_SETTING_SEG0_0 LIBERO_SETTING_SEG0_1 LIBERO_SETTING_SEG0_2 LIBERO_SETTING_SEG0_3 LIBERO_SETTING_SEG0_4 LIBERO_SETTING_SEG0_5 LIBERO_SETTING_SEG0_6 LIBERO_SETTING_SEG0_7 LIBERO_SETTING_SEG1_0 LIBERO_SETTING_SEG1_1 LIBERO_SETTING_SEG1_2 LIBERO_SETTING_SEG1_3 LIBERO_SETTING_SEG1_4 LIBERO_SETTING_SEG1_5 LIBERO_SETTING_SEG1_6 LIBERO_SETTING_SEG1_7 LIBERO_SETTING_SGMII_CLK_XCVR LIBERO_SETTING_SGMII_IOC_REG0 LIBERO_SETTING_SGMII_MODE LIBERO_SETTING_SGMII_PLL_CAL LIBERO_SETTING_SGMII_PLL_CTRL LIBERO_SETTING_SGMII_PLL_CTRL2 LIBERO_SETTING_SGMII_PLL_DIV_0_1 LIBERO_SETTING_SGMII_PLL_DIV_2_3 LIBERO_SETTING_SGMII_PLL_FRACN LIBERO_SETTING_SGMII_PLL_PHADJ LIBERO_SETTING_SGMII_PLL_REF_FB LIBERO_SETTING_SGMII_REFCLKMUX LIBERO_SETTING_SGMII_SGMII_CLKMUX LIBERO_SETTING_SGMII_SOFT_RESET LIBERO_SETTING_SGMII_SPARE0 LIBERO_SETTING_SGMII_SSCG_REG_0 LIBERO_SETTING_SGMII_SSCG_REG_1 LIBERO_SETTING_SGMII_SSCG_REG_2 LIBERO_SETTING_SGMII_SSCG_REG_3 LIBERO_SETTING_SGMII_TEST_CTRL LIBERO_SETTING_SNVM_MSS_END_PAGE LIBERO_SETTING_SNVM_MSS_START_PAGE LIBERO_SETTING_SPARE_CNTL LIBERO_SETTING_SPARE_STAT LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_DDR3 LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_DDR4 LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_DDR3L LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_LPDDR3 LIBERO_SETTING_SW_TRAING_BCLK_SCLK_OFFSET_LPDDR4 LIBERO_SETTING_TIP_CFG_PARAMS LIBERO_SETTING_TIP_CONFIG_PARAMS_BCLK_VCOPHS_OFFSET LIBERO_SETTING_TRACE_MPU_CFG_PMP0 LIBERO_SETTING_TRACE_MPU_CFG_PMP1 LIBERO_SETTING_TRAINING_SKIP_SETTING LIBERO_SETTING_TRIM_OPTIONS LIBERO_SETTING_TURN_ON_FPU LIBERO_SETTING_USB_MPU_CFG_PMP0 LIBERO_SETTING_USB_MPU_CFG_PMP1 LIBERO_SETTING_USB_MPU_CFG_PMP2 LIBERO_SETTING_USB_MPU_CFG_PMP3 LIBERO_SETTING_USER_INPUT_PHY_RANKS_TO_TRAIN LIBERO_SETTING_USE_CK_PUSH_DDR4_LPDDR3 LIBERO_SETTING_WAY_ENABLE LIBERO_SETTING_WAY_MASK_AXI4_PORT_0 LIBERO_SETTING_WAY_MASK_AXI4_PORT_1 LIBERO_SETTING_WAY_MASK_AXI4_PORT_2 LIBERO_SETTING_WAY_MASK_AXI4_PORT_3 LIBERO_SETTING_WAY_MASK_DMA LIBERO_SETTING_WAY_MASK_E51_DCACHE LIBERO_SETTING_WAY_MASK_E51_ICACHE LIBERO_SETTING_WAY_MASK_U54_1_DCACHE LIBERO_SETTING_WAY_MASK_U54_1_ICACHE LIBERO_SETTING_WAY_MASK_U54_2_DCACHE LIBERO_SETTING_WAY_MASK_U54_2_ICACHE LIBERO_SETTING_WAY_MASK_U54_3_DCACHE LIBERO_SETTING_WAY_MASK_U54_3_ICACHE LIBERO_SETTING_WAY_MASK_U54_4_DCACHE LIBERO_SETTING_WAY_MASK_U54_4_ICACHE LIBERO_SETTING_XML_VERSION LIBERO_SETTING_XML_VERSION_MAJOR LIBERO_SETTING_XML_VERSION_MINOR LIBERO_SETTING_XML_VERSION_PATCH LOCAL_INT_F2M_OFFSET LOCAL_INT_MAX LOCAL_INT_OFFSET_IN_MIE LOCAL_INT_UNUSED LOG_REGBYTES LPA_10FULL LPA_10HALF LPA_100 LPA_100BASE4 LPA_100FULL LPA_100HALF LPA_1000FULL LPA_1000HALF LPA_1000LOCALRXOK LPA_1000REMRXOK LPA_1000XFULL LPA_1000XHALF LPA_1000XPAUSE LPA_1000XPAUSE_ASYM LPA_DUPLEX LPA_LPACK LPA_NPAGE LPA_PAUSE_ASYM LPA_PAUSE_CAP LPA_RESV LPA_RFAULT LPA_SLCT LS_DEV_NOT_SUPPORTED M2F_BASE_ADDRESS MAC0_CR_OFFSET MAC0_CR_SPEED_MODE_MASK MAC0_CR_SPEED_MODE_OFFSET MAC0_EMAC_U54_INT MAC0_INT_U54_INT MAC0_MMSL_U54_INT MAC0_QUEUE1_U54_INT MAC0_QUEUE2_U54_INT MAC0_QUEUE3_U54_INT MAC1_CR_OFFSET MAC1_CR_SPEED_MODE_MASK MAC1_CR_SPEED_MODE_OFFSET MAC1_EMAC_U54_INT MAC1_INT_U54_INT MAC1_MMSL_U54_INT MAC1_QUEUE1_U54_INT MAC1_QUEUE2_U54_INT MAC1_QUEUE3_U54_INT MACHINE_STACK_SIZE MAINTENANCE_E51_INT MAINTENANCE_INTEN_CR_DECODE_MASK MAINTENANCE_INTEN_CR_DECODE_OFFSET MAINTENANCE_INTEN_CR_DLL_MASK MAINTENANCE_INTEN_CR_DLL_OFFSET MAINTENANCE_INTEN_CR_FF_END_MASK MAINTENANCE_INTEN_CR_FF_END_OFFSET MAINTENANCE_INTEN_CR_FF_START_MASK MAINTENANCE_INTEN_CR_FF_START_OFFSET MAINTENANCE_INTEN_CR_FPGA_OFF_MASK MAINTENANCE_INTEN_CR_FPGA_OFF_OFFSET MAINTENANCE_INTEN_CR_FPGA_ON_MASK MAINTENANCE_INTEN_CR_FPGA_ON_OFFSET MAINTENANCE_INTEN_CR_IO_BANK_B2_OFF_MASK MAINTENANCE_INTEN_CR_IO_BANK_B2_OFF_OFFSET MAINTENANCE_INTEN_CR_IO_BANK_B2_ON_MASK MAINTENANCE_INTEN_CR_IO_BANK_B2_ON_OFFSET MAINTENANCE_INTEN_CR_IO_BANK_B4_OFF_MASK MAINTENANCE_INTEN_CR_IO_BANK_B4_OFF_OFFSET MAINTENANCE_INTEN_CR_IO_BANK_B4_ON_MASK MAINTENANCE_INTEN_CR_IO_BANK_B4_ON_OFFSET MAINTENANCE_INTEN_CR_IO_BANK_B5_OFF_MASK MAINTENANCE_INTEN_CR_IO_BANK_B5_OFF_OFFSET MAINTENANCE_INTEN_CR_IO_BANK_B5_ON_MASK MAINTENANCE_INTEN_CR_IO_BANK_B5_ON_OFFSET MAINTENANCE_INTEN_CR_IO_BANK_B6_OFF_MASK MAINTENANCE_INTEN_CR_IO_BANK_B6_OFF_OFFSET MAINTENANCE_INTEN_CR_IO_BANK_B6_ON_MASK MAINTENANCE_INTEN_CR_IO_BANK_B6_ON_OFFSET MAINTENANCE_INTEN_CR_LP_STATE_ENTER_MASK MAINTENANCE_INTEN_CR_LP_STATE_ENTER_OFFSET MAINTENANCE_INTEN_CR_LP_STATE_EXIT_MASK MAINTENANCE_INTEN_CR_LP_STATE_EXIT_OFFSET MAINTENANCE_INTEN_CR_MESH_ERROR_MASK MAINTENANCE_INTEN_CR_MESH_ERROR_OFFSET MAINTENANCE_INTEN_CR_MPU_MASK MAINTENANCE_INTEN_CR_MPU_OFFSET MAINTENANCE_INTEN_CR_OFFSET MAINTENANCE_INTEN_CR_PLL_MASK MAINTENANCE_INTEN_CR_PLL_OFFSET MAINTENANCE_INTEN_CR_SCB_ERROR_MASK MAINTENANCE_INTEN_CR_SCB_ERROR_OFFSET MAINTENANCE_INTEN_CR_SCB_FAULT_MASK MAINTENANCE_INTEN_CR_SCB_FAULT_OFFSET MAINTENANCE_INT_SR_DECODE_MASK MAINTENANCE_INT_SR_DECODE_OFFSET MAINTENANCE_INT_SR_DLL_MASK MAINTENANCE_INT_SR_DLL_OFFSET MAINTENANCE_INT_SR_FF_END_MASK MAINTENANCE_INT_SR_FF_END_OFFSET MAINTENANCE_INT_SR_FF_START_MASK MAINTENANCE_INT_SR_FF_START_OFFSET MAINTENANCE_INT_SR_FPGA_OFF_MASK MAINTENANCE_INT_SR_FPGA_OFF_OFFSET MAINTENANCE_INT_SR_FPGA_ON_MASK MAINTENANCE_INT_SR_FPGA_ON_OFFSET MAINTENANCE_INT_SR_IO_BANK_B2_OFF_MASK MAINTENANCE_INT_SR_IO_BANK_B2_OFF_OFFSET MAINTENANCE_INT_SR_IO_BANK_B2_ON_MASK MAINTENANCE_INT_SR_IO_BANK_B2_ON_OFFSET MAINTENANCE_INT_SR_IO_BANK_B4_OFF_MASK MAINTENANCE_INT_SR_IO_BANK_B4_OFF_OFFSET MAINTENANCE_INT_SR_IO_BANK_B4_ON_MASK MAINTENANCE_INT_SR_IO_BANK_B4_ON_OFFSET MAINTENANCE_INT_SR_IO_BANK_B5_OFF_MASK MAINTENANCE_INT_SR_IO_BANK_B5_OFF_OFFSET MAINTENANCE_INT_SR_IO_BANK_B5_ON_MASK MAINTENANCE_INT_SR_IO_BANK_B5_ON_OFFSET MAINTENANCE_INT_SR_IO_BANK_B6_OFF_MASK MAINTENANCE_INT_SR_IO_BANK_B6_OFF_OFFSET MAINTENANCE_INT_SR_IO_BANK_B6_ON_MASK MAINTENANCE_INT_SR_IO_BANK_B6_ON_OFFSET MAINTENANCE_INT_SR_LP_STATE_ENTER_MASK MAINTENANCE_INT_SR_LP_STATE_ENTER_OFFSET MAINTENANCE_INT_SR_LP_STATE_EXIT_MASK MAINTENANCE_INT_SR_LP_STATE_EXIT_OFFSET MAINTENANCE_INT_SR_MESH_ERROR_MASK MAINTENANCE_INT_SR_MESH_ERROR_OFFSET MAINTENANCE_INT_SR_MPU_MASK MAINTENANCE_INT_SR_MPU_OFFSET MAINTENANCE_INT_SR_OFFSET MAINTENANCE_INT_SR_PLL_MASK MAINTENANCE_INT_SR_PLL_OFFSET MAINTENANCE_INT_SR_SCB_ERROR_MASK MAINTENANCE_INT_SR_SCB_ERROR_OFFSET MAINTENANCE_INT_SR_SCB_FAULT_MASK MAINTENANCE_INT_SR_SCB_FAULT_OFFSET MASK_ADD MASK_ADDI MASK_ADDIW MASK_ADDW MASK_AMOADD_D MASK_AMOADD_W MASK_AMOAND_D MASK_AMOAND_W MASK_AMOMAXU_D MASK_AMOMAXU_W MASK_AMOMAX_D MASK_AMOMAX_W MASK_AMOMINU_D MASK_AMOMINU_W MASK_AMOMIN_D MASK_AMOMIN_W MASK_AMOOR_D MASK_AMOOR_W MASK_AMOSWAP_D MASK_AMOSWAP_W MASK_AMOXOR_D MASK_AMOXOR_W MASK_AND MASK_ANDI MASK_AUIPC MASK_BEQ MASK_BGE MASK_BGEU MASK_BLT MASK_BLTU MASK_BNE MASK_CSRRC MASK_CSRRCI MASK_CSRRS MASK_CSRRSI MASK_CSRRW MASK_CSRRWI MASK_CUSTOM0 MASK_CUSTOM0_RD MASK_CUSTOM0_RD_RS1 MASK_CUSTOM0_RD_RS1_RS2 MASK_CUSTOM0_RS1 MASK_CUSTOM0_RS1_RS2 MASK_CUSTOM1 MASK_CUSTOM2 MASK_CUSTOM3 MASK_CUSTOM1_RD MASK_CUSTOM1_RD_RS1 MASK_CUSTOM1_RD_RS1_RS2 MASK_CUSTOM1_RS1 MASK_CUSTOM1_RS1_RS2 MASK_CUSTOM2_RD MASK_CUSTOM2_RD_RS1 MASK_CUSTOM2_RD_RS1_RS2 MASK_CUSTOM2_RS1 MASK_CUSTOM2_RS1_RS2 MASK_CUSTOM3_RD MASK_CUSTOM3_RD_RS1 MASK_CUSTOM3_RD_RS1_RS2 MASK_CUSTOM3_RS1 MASK_CUSTOM3_RS1_RS2 MASK_C_ADD MASK_C_ADDI MASK_C_ADDI4SPN MASK_C_ADDI16SP MASK_C_ADDIW MASK_C_ADDW MASK_C_AND MASK_C_ANDI MASK_C_BEQZ MASK_C_BNEZ MASK_C_EBREAK MASK_C_FLD MASK_C_FLDSP MASK_C_FLW MASK_C_FLWSP MASK_C_FSD MASK_C_FSDSP MASK_C_FSW MASK_C_FSWSP MASK_C_J MASK_C_JAL MASK_C_JALR MASK_C_JR MASK_C_LD MASK_C_LDSP MASK_C_LI MASK_C_LUI MASK_C_LW MASK_C_LWSP MASK_C_MV MASK_C_NOP MASK_C_OR MASK_C_SD MASK_C_SDSP MASK_C_SLLI MASK_C_SRAI MASK_C_SRLI MASK_C_SUB MASK_C_SUBW MASK_C_SW MASK_C_SWSP MASK_C_XOR MASK_DIV MASK_DIVU MASK_DIVUW MASK_DIVW MASK_DRET MASK_EBREAK MASK_ECALL MASK_FADD_D MASK_FADD_Q MASK_FADD_S MASK_FCLASS_D MASK_FCLASS_Q MASK_FCLASS_S MASK_FCVT_D_L MASK_FCVT_D_LU MASK_FCVT_D_Q MASK_FCVT_D_S MASK_FCVT_D_W MASK_FCVT_D_WU MASK_FCVT_LU_D MASK_FCVT_LU_Q MASK_FCVT_LU_S MASK_FCVT_L_D MASK_FCVT_L_Q MASK_FCVT_L_S MASK_FCVT_Q_D MASK_FCVT_Q_L MASK_FCVT_Q_LU MASK_FCVT_Q_S MASK_FCVT_Q_W MASK_FCVT_Q_WU MASK_FCVT_S_D MASK_FCVT_S_L MASK_FCVT_S_LU MASK_FCVT_S_Q MASK_FCVT_S_W MASK_FCVT_S_WU MASK_FCVT_WU_D MASK_FCVT_WU_Q MASK_FCVT_WU_S MASK_FCVT_W_D MASK_FCVT_W_Q MASK_FCVT_W_S MASK_FDIV_D MASK_FDIV_Q MASK_FDIV_S MASK_FENCE MASK_FENCE_I MASK_FEQ_D MASK_FEQ_Q MASK_FEQ_S MASK_FLD MASK_FLE_D MASK_FLE_Q MASK_FLE_S MASK_FLQ MASK_FLT_D MASK_FLT_Q MASK_FLT_S MASK_FLW MASK_FMADD_D MASK_FMADD_Q MASK_FMADD_S MASK_FMAX_D MASK_FMAX_Q MASK_FMAX_S MASK_FMIN_D MASK_FMIN_Q MASK_FMIN_S MASK_FMSUB_D MASK_FMSUB_Q MASK_FMSUB_S MASK_FMUL_D MASK_FMUL_Q MASK_FMUL_S MASK_FMV_D_X MASK_FMV_Q_X MASK_FMV_S_X MASK_FMV_X_D MASK_FMV_X_Q MASK_FMV_X_S MASK_FNMADD_D MASK_FNMADD_Q MASK_FNMADD_S MASK_FNMSUB_D MASK_FNMSUB_Q MASK_FNMSUB_S MASK_FSD MASK_FSGNJN_D MASK_FSGNJN_Q MASK_FSGNJN_S MASK_FSGNJX_D MASK_FSGNJX_Q MASK_FSGNJX_S MASK_FSGNJ_D MASK_FSGNJ_Q MASK_FSGNJ_S MASK_FSQ MASK_FSQRT_D MASK_FSQRT_Q MASK_FSQRT_S MASK_FSUB_D MASK_FSUB_Q MASK_FSUB_S MASK_FSW MASK_HRET MASK_JAL MASK_JALR MASK_LB MASK_LBU MASK_LD MASK_LH MASK_LHU MASK_LR_D MASK_LR_W MASK_LUI MASK_LW MASK_LWU MASK_MRET MASK_MUL MASK_MULH MASK_MULHSU MASK_MULHU MASK_MULW MASK_OR MASK_ORI MASK_REM MASK_REMU MASK_REMUW MASK_REMW MASK_SB MASK_SC_D MASK_SC_W MASK_SD MASK_SFENCE_VMA MASK_SH MASK_SLL MASK_SLLI MASK_SLLIW MASK_SLLW MASK_SLT MASK_SLTI MASK_SLTIU MASK_SLTU MASK_SRA MASK_SRAI MASK_SRAIW MASK_SRAW MASK_SRET MASK_SRL MASK_SRLI MASK_SRLIW MASK_SRLW MASK_SUB MASK_SUBW MASK_SW MASK_URET MASK_WFI MASK_XOR MASK_XORI MATCH_ADD MATCH_ADDI MATCH_ADDIW MATCH_ADDW MATCH_AMOADD_D MATCH_AMOADD_W MATCH_AMOAND_D MATCH_AMOAND_W MATCH_AMOMAXU_D MATCH_AMOMAXU_W MATCH_AMOMAX_D MATCH_AMOMAX_W MATCH_AMOMINU_D MATCH_AMOMINU_W MATCH_AMOMIN_D MATCH_AMOMIN_W MATCH_AMOOR_D MATCH_AMOOR_W MATCH_AMOSWAP_D MATCH_AMOSWAP_W MATCH_AMOXOR_D MATCH_AMOXOR_W MATCH_AND MATCH_ANDI MATCH_AUIPC MATCH_BEQ MATCH_BGE MATCH_BGEU MATCH_BLT MATCH_BLTU MATCH_BNE MATCH_CSRRC MATCH_CSRRCI MATCH_CSRRS MATCH_CSRRSI MATCH_CSRRW MATCH_CSRRWI MATCH_CUSTOM0 MATCH_CUSTOM0_RD MATCH_CUSTOM0_RD_RS1 MATCH_CUSTOM0_RD_RS1_RS2 MATCH_CUSTOM0_RS1 MATCH_CUSTOM0_RS1_RS2 MATCH_CUSTOM1 MATCH_CUSTOM2 MATCH_CUSTOM3 MATCH_CUSTOM1_RD MATCH_CUSTOM1_RD_RS1 MATCH_CUSTOM1_RD_RS1_RS2 MATCH_CUSTOM1_RS1 MATCH_CUSTOM1_RS1_RS2 MATCH_CUSTOM2_RD MATCH_CUSTOM2_RD_RS1 MATCH_CUSTOM2_RD_RS1_RS2 MATCH_CUSTOM2_RS1 MATCH_CUSTOM2_RS1_RS2 MATCH_CUSTOM3_RD MATCH_CUSTOM3_RD_RS1 MATCH_CUSTOM3_RD_RS1_RS2 MATCH_CUSTOM3_RS1 MATCH_CUSTOM3_RS1_RS2 MATCH_C_ADD MATCH_C_ADDI MATCH_C_ADDI4SPN MATCH_C_ADDI16SP MATCH_C_ADDIW MATCH_C_ADDW MATCH_C_AND MATCH_C_ANDI MATCH_C_BEQZ MATCH_C_BNEZ MATCH_C_EBREAK MATCH_C_FLD MATCH_C_FLDSP MATCH_C_FLW MATCH_C_FLWSP MATCH_C_FSD MATCH_C_FSDSP MATCH_C_FSW MATCH_C_FSWSP MATCH_C_J MATCH_C_JAL MATCH_C_JALR MATCH_C_JR MATCH_C_LD MATCH_C_LDSP MATCH_C_LI MATCH_C_LUI MATCH_C_LW MATCH_C_LWSP MATCH_C_MV MATCH_C_NOP MATCH_C_OR MATCH_C_SD MATCH_C_SDSP MATCH_C_SLLI MATCH_C_SRAI MATCH_C_SRLI MATCH_C_SUB MATCH_C_SUBW MATCH_C_SW MATCH_C_SWSP MATCH_C_XOR MATCH_DIV MATCH_DIVU MATCH_DIVUW MATCH_DIVW MATCH_DRET MATCH_EBREAK MATCH_ECALL MATCH_FADD_D MATCH_FADD_Q MATCH_FADD_S MATCH_FCLASS_D MATCH_FCLASS_Q MATCH_FCLASS_S MATCH_FCVT_D_L MATCH_FCVT_D_LU MATCH_FCVT_D_Q MATCH_FCVT_D_S MATCH_FCVT_D_W MATCH_FCVT_D_WU MATCH_FCVT_LU_D MATCH_FCVT_LU_Q MATCH_FCVT_LU_S MATCH_FCVT_L_D MATCH_FCVT_L_Q MATCH_FCVT_L_S MATCH_FCVT_Q_D MATCH_FCVT_Q_L MATCH_FCVT_Q_LU MATCH_FCVT_Q_S MATCH_FCVT_Q_W MATCH_FCVT_Q_WU MATCH_FCVT_S_D MATCH_FCVT_S_L MATCH_FCVT_S_LU MATCH_FCVT_S_Q MATCH_FCVT_S_W MATCH_FCVT_S_WU MATCH_FCVT_WU_D MATCH_FCVT_WU_Q MATCH_FCVT_WU_S MATCH_FCVT_W_D MATCH_FCVT_W_Q MATCH_FCVT_W_S MATCH_FDIV_D MATCH_FDIV_Q MATCH_FDIV_S MATCH_FENCE MATCH_FENCE_I MATCH_FEQ_D MATCH_FEQ_Q MATCH_FEQ_S MATCH_FLD MATCH_FLE_D MATCH_FLE_Q MATCH_FLE_S MATCH_FLQ MATCH_FLT_D MATCH_FLT_Q MATCH_FLT_S MATCH_FLW MATCH_FMADD_D MATCH_FMADD_Q MATCH_FMADD_S MATCH_FMAX_D MATCH_FMAX_Q MATCH_FMAX_S MATCH_FMIN_D MATCH_FMIN_Q MATCH_FMIN_S MATCH_FMSUB_D MATCH_FMSUB_Q MATCH_FMSUB_S MATCH_FMUL_D MATCH_FMUL_Q MATCH_FMUL_S MATCH_FMV_D_X MATCH_FMV_Q_X MATCH_FMV_S_X MATCH_FMV_X_D MATCH_FMV_X_Q MATCH_FMV_X_S MATCH_FNMADD_D MATCH_FNMADD_Q MATCH_FNMADD_S MATCH_FNMSUB_D MATCH_FNMSUB_Q MATCH_FNMSUB_S MATCH_FSD MATCH_FSGNJN_D MATCH_FSGNJN_Q MATCH_FSGNJN_S MATCH_FSGNJX_D MATCH_FSGNJX_Q MATCH_FSGNJX_S MATCH_FSGNJ_D MATCH_FSGNJ_Q MATCH_FSGNJ_S MATCH_FSQ MATCH_FSQRT_D MATCH_FSQRT_Q MATCH_FSQRT_S MATCH_FSUB_D MATCH_FSUB_Q MATCH_FSUB_S MATCH_FSW MATCH_HRET MATCH_JAL MATCH_JALR MATCH_LB MATCH_LBU MATCH_LD MATCH_LH MATCH_LHU MATCH_LR_D MATCH_LR_W MATCH_LUI MATCH_LW MATCH_LWU MATCH_MRET MATCH_MUL MATCH_MULH MATCH_MULHSU MATCH_MULHU MATCH_MULW MATCH_OR MATCH_ORI MATCH_REM MATCH_REMU MATCH_REMUW MATCH_REMW MATCH_SB MATCH_SC_D MATCH_SC_W MATCH_SD MATCH_SFENCE_VMA MATCH_SH MATCH_SLL MATCH_SLLI MATCH_SLLIW MATCH_SLLW MATCH_SLT MATCH_SLTI MATCH_SLTIU MATCH_SLTU MATCH_SRA MATCH_SRAI MATCH_SRAIW MATCH_SRAW MATCH_SRET MATCH_SRL MATCH_SRLI MATCH_SRLIW MATCH_SRLW MATCH_SUB MATCH_SUBW MATCH_SW MATCH_URET MATCH_WFI MATCH_XOR MATCH_XORI MAX_LANES MAX_NO_PATTERNS MAX_POSSIBLE_TIP_TRAININGS MAX_RPC_166_VALUE MAX_WAY_ENABLE MCAUSE32_CAUSE MCAUSE32_INT MCAUSE64_CAUSE MCAUSE64_INT MCAUSE_CAUSE MCAUSE_INT MCONTROL_ACTION MCONTROL_ACTION_DEBUG_EXCEPTION MCONTROL_ACTION_DEBUG_MODE MCONTROL_ACTION_TRACE_EMIT MCONTROL_ACTION_TRACE_START MCONTROL_ACTION_TRACE_STOP MCONTROL_CHAIN MCONTROL_EXECUTE MCONTROL_H MCONTROL_LOAD MCONTROL_M MCONTROL_MATCH MCONTROL_MATCH_EQUAL MCONTROL_MATCH_GE MCONTROL_MATCH_LT MCONTROL_MATCH_MASK_HIGH MCONTROL_MATCH_MASK_LOW MCONTROL_MATCH_NAPOT MCONTROL_S MCONTROL_SELECT MCONTROL_STORE MCONTROL_TIMING MCONTROL_TYPE_MATCH MCONTROL_TYPE_NONE MCONTROL_U MESH_CR_HOLD_MASK MESH_CR_HOLD_OFFSET MESH_CR_INJECT_ERROR_MASK MESH_CR_INJECT_ERROR_OFFSET MESH_CR_MESH_ERROR_MASK MESH_CR_MESH_ERROR_OFFSET MESH_CR_OFFSET MESH_CR_OKAY_MASK MESH_CR_OKAY_OFFSET MESH_CR_START_MASK MESH_CR_START_OFFSET MESH_SEED_CR_CLKRATE_MASK MESH_SEED_CR_CLKRATE_OFFSET MESH_SEED_CR_OFFSET MESH_SEED_CR_SEED_MASK MESH_SEED_CR_SEED_OFFSET MII_ADDAR MII_ADVERTISE MII_BMCR MII_BMSR MII_CTRL1000 MII_DCOUNTER MII_ESTATUS MII_EXPANSION MII_EXTEND MII_FCSCOUNTER MII_LBRERROR MII_LMCS MII_LPA MII_LPNPA MII_NCONFIG MII_NPAR MII_PHYADDR MII_PHYCTRL1 MII_PHYCTRL2 MII_PHYSID1 MII_PHYSID2 MII_REGCR MII_RERRCOUNTER MII_RESV1 MII_RESV2 MII_SREVISION MII_STAT1000 MII_TI_ADDAR MII_TI_CTRL MII_TI_PHYCR MII_TI_REGCR MII_TI_SGMIICTL1 MII_TPISTATUS MIN_DLL_90_CODE_VALUE_INDICATING_TT_PART_REVB MIN_EP_FIFO_SZ MIN_RPC_166_VALUE MIP_HEIP MIP_HSIP MIP_HTIP MIP_MEIP MIP_MSIP MIP_MTIP MIP_SEIP MIP_SSIP MIP_STIP MISC_SR_CONT_SPI_INTERRUPT_MASK MISC_SR_CONT_SPI_INTERRUPT_OFFSET MISC_SR_OFFSET MISC_SR_VOLT_TEMP_ALARM_MASK MISC_SR_VOLT_TEMP_ALARM_OFFSET MMUART0_E51_INT MMUARTx_U54_INT MPFS_HAL_CLEAR_MEMORY MPFS_HAL_FIRST_HART MPFS_HAL_LAST_HART MPU_ENABLED_MASK MPU_MODE_EXEC_ACCESS MPU_MODE_READ_ACCESS MPU_MODE_WRITE_ACCESS MPU_VIOLATION_INTEN_CR_ATHENA_MASK MPU_VIOLATION_INTEN_CR_ATHENA_OFFSET MPU_VIOLATION_INTEN_CR_FIC0_MASK MPU_VIOLATION_INTEN_CR_FIC0_OFFSET MPU_VIOLATION_INTEN_CR_FIC1_MASK MPU_VIOLATION_INTEN_CR_FIC1_OFFSET MPU_VIOLATION_INTEN_CR_FIC2_MASK MPU_VIOLATION_INTEN_CR_FIC2_OFFSET MPU_VIOLATION_INTEN_CR_GEM0_MASK MPU_VIOLATION_INTEN_CR_GEM0_OFFSET MPU_VIOLATION_INTEN_CR_GEM1_MASK MPU_VIOLATION_INTEN_CR_GEM1_OFFSET MPU_VIOLATION_INTEN_CR_MMC_MASK MPU_VIOLATION_INTEN_CR_MMC_OFFSET MPU_VIOLATION_INTEN_CR_OFFSET MPU_VIOLATION_INTEN_CR_SCB_MASK MPU_VIOLATION_INTEN_CR_SCB_OFFSET MPU_VIOLATION_INTEN_CR_TRACE_MASK MPU_VIOLATION_INTEN_CR_TRACE_OFFSET MPU_VIOLATION_INTEN_CR_USB_MASK MPU_VIOLATION_INTEN_CR_USB_OFFSET MPU_VIOLATION_SR_ATHENA_MASK MPU_VIOLATION_SR_ATHENA_OFFSET MPU_VIOLATION_SR_FIC0_MASK MPU_VIOLATION_SR_FIC0_OFFSET MPU_VIOLATION_SR_FIC1_MASK MPU_VIOLATION_SR_FIC1_OFFSET MPU_VIOLATION_SR_FIC2_MASK MPU_VIOLATION_SR_FIC2_OFFSET MPU_VIOLATION_SR_GEM0_MASK MPU_VIOLATION_SR_GEM0_OFFSET MPU_VIOLATION_SR_GEM1_MASK MPU_VIOLATION_SR_GEM1_OFFSET MPU_VIOLATION_SR_MMC_MASK MPU_VIOLATION_SR_MMC_OFFSET MPU_VIOLATION_SR_OFFSET MPU_VIOLATION_SR_SCB_MASK MPU_VIOLATION_SR_SCB_OFFSET MPU_VIOLATION_SR_TRACE_MASK MPU_VIOLATION_SR_TRACE_OFFSET MPU_VIOLATION_SR_USB_MASK MPU_VIOLATION_SR_USB_OFFSET MSSIO_BANK2_CFG_CR_BANK_NCODE_MASK MSSIO_BANK2_CFG_CR_BANK_NCODE_OFFSET MSSIO_BANK2_CFG_CR_BANK_PCODE_MASK MSSIO_BANK2_CFG_CR_BANK_PCODE_OFFSET MSSIO_BANK2_CFG_CR_OFFSET MSSIO_BANK2_CFG_CR_VS_MASK MSSIO_BANK2_CFG_CR_VS_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_ATP_EN_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_CLAMP_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_0_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_1_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_2_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_3_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_ENHYST_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_WPD_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_WPD_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_WPU_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_WPU_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_ATP_EN_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_CLAMP_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_0_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_1_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_2_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_3_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_ENHYST_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_WPD_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_WPD_OFFSET MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_WPU_MASK MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_WPU_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_ATP_EN_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_CLAMP_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_0_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_1_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_2_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_3_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_ENHYST_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_WPD_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_WPD_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_WPU_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_WPU_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_ATP_EN_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_CLAMP_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_0_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_1_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_2_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_3_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_ENHYST_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_WPD_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_WPD_OFFSET MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_WPU_MASK MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_WPU_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_ATP_EN_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_CLAMP_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_0_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_1_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_2_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_3_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_ENHYST_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_WPD_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_WPD_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_WPU_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_WPU_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_ATP_EN_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_CLAMP_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_0_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_1_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_2_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_3_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_ENHYST_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_WPD_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_WPD_OFFSET MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_WPU_MASK MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_WPU_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_ATP_EN_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_CLAMP_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_0_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_1_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_2_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_3_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_ENHYST_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_WPD_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_WPD_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_WPU_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_WPU_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_ATP_EN_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_CLAMP_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_0_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_1_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_2_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_3_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_ENHYST_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_WPD_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_WPD_OFFSET MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_WPU_MASK MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_WPU_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_ATP_EN_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_CLAMP_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_0_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_1_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_2_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_3_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_ENHYST_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_WPD_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_WPD_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_WPU_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_WPU_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_ATP_EN_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_CLAMP_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_0_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_1_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_2_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_3_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_ENHYST_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_WPD_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_WPD_OFFSET MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_WPU_MASK MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_WPU_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_ATP_EN_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_CLAMP_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_0_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_1_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_2_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_3_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_ENHYST_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_WPD_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_WPD_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_WPU_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_WPU_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_ATP_EN_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_CLAMP_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_0_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_1_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_2_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_3_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_ENHYST_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_WPD_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_WPD_OFFSET MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_WPU_MASK MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_WPU_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_ATP_EN_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_CLAMP_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_0_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_1_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_2_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_3_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_ENHYST_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_WPD_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_WPD_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_WPU_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_WPU_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_ATP_EN_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_CLAMP_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_0_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_1_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_2_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_3_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_ENHYST_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_WPD_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_WPD_OFFSET MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_WPU_MASK MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_WPU_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_ATP_EN_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_CLAMP_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_DRV_0_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_DRV_1_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_DRV_2_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_DRV_3_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_ENHYST_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_WPD_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_WPD_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_WPU_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_WPU_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_ATP_EN_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_CLAMP_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_DRV_0_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_DRV_1_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_DRV_2_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_DRV_3_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_ENHYST_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_WPD_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_WPD_OFFSET MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_WPU_MASK MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_WPU_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_ATP_EN_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_CLAMP_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_DRV_0_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_DRV_1_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_DRV_2_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_DRV_3_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_ENHYST_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_WPD_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_WPD_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_WPU_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_WPU_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_ATP_EN_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_CLAMP_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_DRV_0_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_DRV_1_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_DRV_2_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_DRV_3_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_ENHYST_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_WPD_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_WPD_OFFSET MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_WPU_MASK MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_WPU_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_ATP_EN_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_CLAMP_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_DRV_0_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_DRV_1_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_DRV_2_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_DRV_3_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_ENHYST_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_WPD_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_WPD_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_WPU_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_WPU_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_ATP_EN_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_CLAMP_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_DRV_0_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_DRV_1_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_DRV_2_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_DRV_3_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_ENHYST_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_WPD_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_WPD_OFFSET MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_WPU_MASK MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_WPU_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_ATP_EN_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_CLAMP_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_DRV_0_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_DRV_1_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_DRV_2_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_DRV_3_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_ENHYST_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_WPD_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_WPD_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_WPU_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_WPU_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_ATP_EN_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_CLAMP_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_DRV_0_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_DRV_1_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_DRV_2_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_DRV_3_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_ENHYST_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_WPD_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_WPD_OFFSET MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_WPU_MASK MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_WPU_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_ATP_EN_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_CLAMP_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_DRV_0_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_DRV_1_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_DRV_2_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_DRV_3_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_ENHYST_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_WPD_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_WPD_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_WPU_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_WPU_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_ATP_EN_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_ATP_EN_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_CLAMP_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_CLAMP_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_DRV_0_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_DRV_0_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_DRV_1_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_DRV_1_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_DRV_2_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_DRV_2_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_DRV_3_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_DRV_3_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_ENHYST_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_ENHYST_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_IBUFMD_0_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_IBUFMD_0_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_IBUFMD_1_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_IBUFMD_1_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_IBUFMD_2_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_IBUFMD_2_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_LOCKDN_EN_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_LOCKDN_EN_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_LP_BYPASS_EN_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_LP_BYPASS_EN_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_LP_PERSIST_EN_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_LP_PERSIST_EN_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_WPD_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_WPD_OFFSET MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_WPU_MASK MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_WPU_OFFSET MSSIO_BANK4_CFG_CR_BANK_NCODE_MASK MSSIO_BANK4_CFG_CR_BANK_NCODE_OFFSET MSSIO_BANK4_CFG_CR_BANK_PCODE_MASK MSSIO_BANK4_CFG_CR_BANK_PCODE_OFFSET MSSIO_BANK4_CFG_CR_OFFSET MSSIO_BANK4_CFG_CR_VS_MASK MSSIO_BANK4_CFG_CR_VS_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_ATP_EN_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_ATP_EN_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_CLAMP_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_CLAMP_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_0_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_0_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_1_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_1_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_2_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_2_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_3_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_3_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_ENHYST_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_ENHYST_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_0_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_0_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_1_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_1_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_2_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_2_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_LOCKDN_EN_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_LOCKDN_EN_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_LP_BYPASS_EN_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_LP_BYPASS_EN_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_LP_PERSIST_EN_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_LP_PERSIST_EN_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_WPD_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_WPD_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_WPU_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_WPU_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_ATP_EN_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_ATP_EN_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_CLAMP_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_CLAMP_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_0_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_0_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_1_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_1_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_2_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_2_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_3_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_3_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_ENHYST_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_ENHYST_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_0_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_0_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_1_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_1_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_2_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_2_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_LOCKDN_EN_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_LOCKDN_EN_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_LP_BYPASS_EN_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_LP_BYPASS_EN_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_LP_PERSIST_EN_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_LP_PERSIST_EN_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_WPD_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_WPD_OFFSET MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_WPU_MASK MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_WPU_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_ATP_EN_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_ATP_EN_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_CLAMP_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_CLAMP_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_0_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_0_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_1_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_1_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_2_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_2_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_3_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_3_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_ENHYST_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_ENHYST_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_0_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_0_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_1_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_1_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_2_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_2_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_LOCKDN_EN_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_LOCKDN_EN_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_LP_BYPASS_EN_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_LP_BYPASS_EN_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_LP_PERSIST_EN_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_LP_PERSIST_EN_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_WPD_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_WPD_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_WPU_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_WPU_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_ATP_EN_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_ATP_EN_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_CLAMP_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_CLAMP_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_0_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_0_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_1_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_1_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_2_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_2_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_3_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_3_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_ENHYST_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_ENHYST_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_0_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_0_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_1_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_1_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_2_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_2_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_LOCKDN_EN_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_LOCKDN_EN_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_LP_BYPASS_EN_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_LP_BYPASS_EN_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_LP_PERSIST_EN_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_LP_PERSIST_EN_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_WPD_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_WPD_OFFSET MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_WPU_MASK MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_WPU_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_ATP_EN_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_ATP_EN_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_CLAMP_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_CLAMP_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_0_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_0_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_1_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_1_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_2_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_2_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_3_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_3_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_ENHYST_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_ENHYST_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_0_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_0_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_1_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_1_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_2_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_2_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_LOCKDN_EN_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_LOCKDN_EN_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_LP_BYPASS_EN_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_LP_BYPASS_EN_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_LP_PERSIST_EN_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_LP_PERSIST_EN_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_WPD_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_WPD_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_WPU_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_WPU_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_ATP_EN_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_ATP_EN_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_CLAMP_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_CLAMP_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_0_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_0_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_1_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_1_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_2_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_2_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_3_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_3_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_ENHYST_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_ENHYST_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_0_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_0_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_1_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_1_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_2_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_2_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_LOCKDN_EN_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_LOCKDN_EN_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_LP_BYPASS_EN_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_LP_BYPASS_EN_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_LP_PERSIST_EN_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_LP_PERSIST_EN_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_WPD_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_WPD_OFFSET MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_WPU_MASK MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_WPU_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_ATP_EN_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_ATP_EN_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_CLAMP_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_CLAMP_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_0_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_0_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_1_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_1_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_2_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_2_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_3_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_3_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_ENHYST_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_ENHYST_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_0_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_0_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_1_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_1_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_2_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_2_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_LOCKDN_EN_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_LOCKDN_EN_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_LP_BYPASS_EN_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_LP_BYPASS_EN_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_LP_PERSIST_EN_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_LP_PERSIST_EN_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_WPD_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_WPD_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_WPU_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_WPU_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_ATP_EN_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_ATP_EN_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_CLAMP_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_CLAMP_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_0_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_0_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_1_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_1_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_2_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_2_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_3_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_3_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_ENHYST_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_ENHYST_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_0_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_0_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_1_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_1_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_2_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_2_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_LOCKDN_EN_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_LOCKDN_EN_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_LP_BYPASS_EN_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_LP_BYPASS_EN_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_LP_PERSIST_EN_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_LP_PERSIST_EN_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_WPD_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_WPD_OFFSET MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_WPU_MASK MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_WPU_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_ATP_EN_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_ATP_EN_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_CLAMP_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_CLAMP_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_0_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_0_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_1_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_1_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_2_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_2_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_3_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_3_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_ENHYST_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_ENHYST_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_0_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_0_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_1_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_1_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_2_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_2_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_LOCKDN_EN_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_LOCKDN_EN_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_LP_BYPASS_EN_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_LP_BYPASS_EN_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_LP_PERSIST_EN_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_LP_PERSIST_EN_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_WPD_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_WPD_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_WPU_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_WPU_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_ATP_EN_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_ATP_EN_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_CLAMP_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_CLAMP_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_0_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_0_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_1_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_1_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_2_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_2_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_3_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_3_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_ENHYST_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_ENHYST_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_0_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_0_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_1_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_1_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_2_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_2_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_LOCKDN_EN_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_LOCKDN_EN_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_LP_BYPASS_EN_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_LP_BYPASS_EN_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_LP_PERSIST_EN_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_LP_PERSIST_EN_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_WPD_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_WPD_OFFSET MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_WPU_MASK MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_WPU_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_ATP_EN_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_ATP_EN_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_CLAMP_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_CLAMP_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_0_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_0_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_1_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_1_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_2_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_2_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_3_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_3_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_ENHYST_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_ENHYST_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_0_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_0_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_1_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_1_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_2_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_2_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_LOCKDN_EN_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_LOCKDN_EN_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_LP_BYPASS_EN_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_LP_BYPASS_EN_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_LP_PERSIST_EN_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_LP_PERSIST_EN_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_WPD_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_WPD_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_WPU_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_WPU_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_ATP_EN_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_ATP_EN_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_CLAMP_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_CLAMP_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_0_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_0_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_1_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_1_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_2_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_2_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_3_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_3_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_ENHYST_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_ENHYST_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_0_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_0_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_1_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_1_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_2_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_2_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_LOCKDN_EN_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_LOCKDN_EN_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_LP_BYPASS_EN_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_LP_BYPASS_EN_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_LP_PERSIST_EN_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_LP_PERSIST_EN_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_WPD_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_WPD_OFFSET MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_WPU_MASK MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_WPU_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_ATP_EN_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_ATP_EN_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_CLAMP_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_CLAMP_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_0_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_0_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_1_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_1_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_2_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_2_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_3_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_3_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_ENHYST_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_ENHYST_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_0_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_0_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_1_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_1_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_2_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_2_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_LOCKDN_EN_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_LOCKDN_EN_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_LP_BYPASS_EN_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_LP_BYPASS_EN_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_LP_PERSIST_EN_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_LP_PERSIST_EN_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_WPD_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_WPD_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_WPU_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_WPU_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_ATP_EN_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_ATP_EN_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_CLAMP_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_CLAMP_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_0_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_0_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_1_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_1_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_2_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_2_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_3_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_3_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_ENHYST_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_ENHYST_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_0_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_0_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_1_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_1_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_2_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_2_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_LOCKDN_EN_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_LOCKDN_EN_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_LP_BYPASS_EN_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_LP_BYPASS_EN_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_LP_PERSIST_EN_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_LP_PERSIST_EN_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_WPD_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_WPD_OFFSET MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_WPU_MASK MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_WPU_OFFSET MSSIO_CONFIG_OPTION__ALT_MSSIO_CONFIGURATION < 1 alternate config MSSIO_CONFIG_OPTION__DEFAULT_MSSIO_CONFIGURATION < 0 default behavior MSS_BUILD_OFFSET MSS_BUILD_REVISION_MASK MSS_BUILD_REVISION_OFFSET MSS_BUS_ERROR_UNIT_H0 MSS_BUS_ERROR_UNIT_H1 MSS_BUS_ERROR_UNIT_H2 MSS_BUS_ERROR_UNIT_H3 MSS_BUS_ERROR_UNIT_H4 MSS_FREQ_SCALING_OPTION__MSS_CLK_SCALING_LOW < 1 MSS PLL clock source MSS_FREQ_SCALING_OPTION__MSS_CLK_SCALING_MEDIUM < 1 MSS PLL clock source MSS_FREQ_SCALING_OPTION__MSS_CLK_SCALING_NORMAL < 0 SCB clock source MSS_GPIO_0_MASK MSS_GPIO_1_MASK MSS_GPIO_2_MASK MSS_GPIO_3_MASK MSS_GPIO_4_MASK MSS_GPIO_5_MASK MSS_GPIO_6_MASK MSS_GPIO_7_MASK MSS_GPIO_8_MASK MSS_GPIO_9_MASK MSS_GPIO_10_MASK MSS_GPIO_11_MASK MSS_GPIO_12_MASK MSS_GPIO_13_MASK MSS_GPIO_14_MASK MSS_GPIO_15_MASK MSS_GPIO_16_MASK MSS_GPIO_17_MASK MSS_GPIO_18_MASK MSS_GPIO_19_MASK MSS_GPIO_20_MASK MSS_GPIO_21_MASK MSS_GPIO_22_MASK MSS_GPIO_23_MASK MSS_GPIO_24_MASK MSS_GPIO_25_MASK MSS_GPIO_26_MASK MSS_GPIO_27_MASK MSS_GPIO_28_MASK MSS_GPIO_29_MASK MSS_GPIO_30_MASK MSS_GPIO_31_MASK MSS_GPIO_INOUT_MODE MSS_GPIO_INPUT_MODE MSS_GPIO_IRQ_EDGE_BOTH MSS_GPIO_IRQ_EDGE_NEGATIVE MSS_GPIO_IRQ_EDGE_POSITIVE MSS_GPIO_IRQ_LEVEL_HIGH MSS_GPIO_IRQ_LEVEL_LOW MSS_GPIO_OUTPUT_MODE MSS_I2C_HOLD_BUS MSS_I2C_NO_TIMEOUT MSS_I2C_RELEASE_BUS MSS_I2C_SMBALERT_IRQ MSS_I2C_SMBSUS_IRQ MSS_IO_OPTIONS__EMMC_MSSIO_CONFIGURATION < 1 eMMC config MSS_IO_OPTIONS__NOT_SETUP_MSSIO_CONFIGURATION < 0 none configured MSS_IO_OPTIONS__NO_SUPPORT_MSSIO_CONFIGURATION < 0 MSS Configurator version too early MSS_IO_OPTIONS__SD_MSSIO_CONFIGURATION < 0 SD config MSS_MAC_64_BIT_ADDRESS_MODE MSS_MAC_AMBA_BURST_1 MSS_MAC_AMBA_BURST_4 MSS_MAC_AMBA_BURST_8 MSS_MAC_AMBA_BURST_16 MSS_MAC_AMBA_BURST_256 MSS_MAC_AMBA_BURST_MASK MSS_MAC_ANEG_10M_FD MSS_MAC_ANEG_10M_HD MSS_MAC_ANEG_100M_FD MSS_MAC_ANEG_100M_HD MSS_MAC_ANEG_1000M_FD MSS_MAC_ANEG_1000M_HD MSS_MAC_ANEG_ALL_SPEEDS MSS_MAC_AVAILABLE MSS_MAC_BY8_PHY_CLK MSS_MAC_BY16_PHY_CLK MSS_MAC_BY32_PHY_CLK MSS_MAC_BY48_PHY_CLK MSS_MAC_BY64_PHY_CLK MSS_MAC_BY96_PHY_CLK MSS_MAC_BY128_PHY_CLK MSS_MAC_BY224_PHY_CLK MSS_MAC_CRC_DISABLE MSS_MAC_CRC_ENABLE MSS_MAC_DEF_PHY_CLK MSS_MAC_DESIGN_ALOE MSS_MAC_DESIGN_BEAGLEV_FIRE_GEM0 MSS_MAC_DESIGN_EMUL_DUAL_EXTERNAL MSS_MAC_DESIGN_EMUL_DUAL_EX_TI MSS_MAC_DESIGN_EMUL_DUAL_EX_VTS MSS_MAC_DESIGN_EMUL_DUAL_INTERNAL MSS_MAC_DESIGN_EMUL_GMII MSS_MAC_DESIGN_EMUL_GMII_GEM1 MSS_MAC_DESIGN_EMUL_GMII_LOCAL MSS_MAC_DESIGN_EMUL_TBI MSS_MAC_DESIGN_EMUL_TBI_GEM1 MSS_MAC_DESIGN_EMUL_TBI_GEM1_TI MSS_MAC_DESIGN_EMUL_TBI_TI MSS_MAC_DESIGN_EMUL_TI_GMII MSS_MAC_DESIGN_ICICLE_SGMII_GEM0 MSS_MAC_DESIGN_ICICLE_SGMII_GEM1 MSS_MAC_DESIGN_ICICLE_SGMII_GEMS MSS_MAC_DESIGN_ICICLE_STD_GEM0 MSS_MAC_DESIGN_ICICLE_STD_GEM0_LOCAL MSS_MAC_DESIGN_ICICLE_STD_GEM1 MSS_MAC_DESIGN_ICICLE_STD_GEMS MSS_MAC_DESIGN_RENODE MSS_MAC_DESIGN_SVG_DUAL_GEM MSS_MAC_DESIGN_SVG_GMII_GEM0 MSS_MAC_DESIGN_SVG_GMII_GEM0_SGMII_GEM1 MSS_MAC_DESIGN_SVG_GMII_GEM1 MSS_MAC_DESIGN_SVG_SGMII_GEM0 MSS_MAC_DESIGN_SVG_SGMII_GEM1 MSS_MAC_DEV_PHY_DP83867 MSS_MAC_DEV_PHY_NULL MSS_MAC_DEV_PHY_RTL8211 MSS_MAC_DEV_PHY_VSC8541 MSS_MAC_DEV_PHY_VSC8575 MSS_MAC_DEV_PHY_VSC8662 MSS_MAC_DEV_PHY_VSC8575_LITE MSS_MAC_DISABLE MSS_MAC_EMAC_TYPE_2_COMPARERS MSS_MAC_EMAC_TYPE_2_SCREENERS MSS_MAC_ENABLE MSS_MAC_ERR_DET_CORR_DISABLE MSS_MAC_ERR_DET_CORR_ENABLE MSS_MAC_ERR_NOT_DONE MSS_MAC_ERR_OK MSS_MAC_ERR_TX_FAIL MSS_MAC_ERR_TX_NOT_OK MSS_MAC_ERR_TX_TIMEOUT MSS_MAC_FAILED MSS_MAC_FULLDUPLEX_DISABLE MSS_MAC_FULLDUPLEX_ENABLE MSS_MAC_FULL_DUPLEX MSS_MAC_HALF_DUPLEX MSS_MAC_HW_PLATFORM MSS_MAC_IPG_DEFVAL MSS_MAC_JUMBO_FRAME_DISABLE MSS_MAC_JUMBO_FRAME_ENABLE MSS_MAC_JUMBO_MAX MSS_MAC_LENGTH_FIELD_CHECK_DISABLE MSS_MAC_LENGTH_FIELD_CHECK_ENABLE MSS_MAC_LINK_DOWN MSS_MAC_LINK_UP MSS_MAC_LOOPBACK_DISABLE MSS_MAC_LOOPBACK_ENABLE MSS_MAC_MAC_LEN MSS_MAC_MAXFRAMELEN_DEFVAL MSS_MAC_MAXFRAMELEN_MAXVAL MSS_MAC_MAX_PACKET_SIZE MSS_MAC_MAX_RX_BUF_SIZE MSS_MAC_MAX_TX_BUF_SIZE MSS_MAC_MEM_CRYPTO MSS_MAC_MEM_DDR MSS_MAC_MEM_FIC0 MSS_MAC_MEM_FIC1 MSS_MAC_PHYS MSS_MAC_QUEUE_COUNT MSS_MAC_QUEUE_DISABLE MSS_MAC_QUEUE_ENABLE MSS_MAC_RX_BUF_VALUE MSS_MAC_RX_FLOW_CTRL_DISABLE MSS_MAC_RX_FLOW_CTRL_ENABLE MSS_MAC_RX_RING_SIZE MSS_MAC_SA_FILTER_BYTE0 MSS_MAC_SA_FILTER_BYTE1 MSS_MAC_SA_FILTER_BYTE2 MSS_MAC_SA_FILTER_BYTE3 MSS_MAC_SA_FILTER_BYTE4 MSS_MAC_SA_FILTER_BYTE5 MSS_MAC_SA_FILTER_DISABLE MSS_MAC_SA_FILTER_SOURCE MSS_MAC_SUCCESS MSS_MAC_T2_OFFSET_ETHERTYPE MSS_MAC_T2_OFFSET_FRAME MSS_MAC_T2_OFFSET_IP MSS_MAC_T2_OFFSET_TCP_UDP MSS_MAC_TIME_STAMPED_MODE MSS_MAC_TX_FLOW_CTRL_DISABLE MSS_MAC_TX_FLOW_CTRL_ENABLE MSS_MAC_TX_RING_SIZE MSS_MAC_TYPE_1_SCREENERS MSS_MAC_TYPE_2_COMPARERS MSS_MAC_TYPE_2_ETHERTYPES MSS_MAC_TYPE_2_SCREENERS MSS_MMC_1_8V_BUS_VOLTAGE MSS_MMC_3_3V_BUS_VOLTAGE MSS_MMC_CARD_TYPE_COMBO MSS_MMC_CARD_TYPE_MMC MSS_MMC_CARD_TYPE_NONE MSS_MMC_CARD_TYPE_SD MSS_MMC_CARD_TYPE_SDIO MSS_MMC_CLOCK_12_5MHZ MSS_MMC_CLOCK_25MHZ MSS_MMC_CLOCK_26MHZ MSS_MMC_CLOCK_50MHZ MSS_MMC_CLOCK_100MHZ MSS_MMC_CLOCK_200MHZ MSS_MMC_CLOCK_400KHZ MSS_MMC_DATA_WIDTH_1BIT MSS_MMC_DATA_WIDTH_4BIT MSS_MMC_DATA_WIDTH_8BIT MSS_MMC_MODE_DDR MSS_MMC_MODE_HS200 MSS_MMC_MODE_HS400 MSS_MMC_MODE_HS400_ES MSS_MMC_MODE_LEGACY MSS_MMC_MODE_MASK MSS_MMC_MODE_SDCARD MSS_MMC_MODE_SDR MSS_QSPI_DISABLE MSS_QSPI_ENABLE MSS_QSPI_H_ MSS_QSPI_SAMPLE_ACTIVE_SPICLK MSS_QSPI_SAMPLE_NEGAGE_SPICLK MSS_QSPI_SAMPLE_POSAGE_SPICLK MSS_SCB_DDR_PLL_BASE MSS_SCB_MSS_MUX_BASE MSS_SCB_MSS_PLL_BASE MSS_SCB_SGMII_MUX_BASE MSS_SCB_SGMII_PLL_BASE MSS_SDCARD_MODE_DDR50 MSS_SDCARD_MODE_DEFAULT_SPEED MSS_SDCARD_MODE_HIGH_SPEED MSS_SDCARD_MODE_SDR12 MSS_SDCARD_MODE_SDR25 MSS_SDCARD_MODE_SDR50 MSS_SDCARD_MODE_SDR104 MSS_SDIO_FUNCTION_NUMBER_0 MSS_SDIO_FUNCTION_NUMBER_1 MSS_SDIO_FUNCTION_NUMBER_2 MSS_SDIO_FUNCTION_NUMBER_3 MSS_SDIO_FUNCTION_NUMBER_4 MSS_SDIO_FUNCTION_NUMBER_5 MSS_SDIO_FUNCTION_NUMBER_6 MSS_SDIO_FUNCTION_NUMBER_7 MSS_SPARE0_CR_DATA_MASK MSS_SPARE0_CR_DATA_OFFSET MSS_SPARE0_CR_OFFSET MSS_SPARE0_SR_DATA_MASK MSS_SPARE0_SR_DATA_OFFSET MSS_SPARE0_SR_OFFSET MSS_SPARE1_CR_DATA_MASK MSS_SPARE1_CR_DATA_OFFSET MSS_SPARE1_CR_OFFSET MSS_SPARE1_SR_DATA_MASK MSS_SPARE1_SR_DATA_OFFSET MSS_SPARE1_SR_OFFSET MSS_SPARE2_SR_DATA_MASK MSS_SPARE2_SR_DATA_OFFSET MSS_SPARE2_SR_OFFSET MSS_SPARE3_SR_DATA_MASK MSS_SPARE3_SR_DATA_OFFSET MSS_SPARE3_SR_OFFSET MSS_SPARE4_SR_DATA_MASK MSS_SPARE4_SR_DATA_OFFSET MSS_SPARE4_SR_OFFSET MSS_SPARE5_SR_DATA_MASK MSS_SPARE5_SR_DATA_OFFSET MSS_SPARE5_SR_OFFSET MSS_SYS_APB_READ_DEBUG_CMD MSS_SYS_APB_SECERR MSS_SYS_APB_SERVICE_DATA_LEN MSS_SYS_APB_SLVERR MSS_SYS_APB_TIMEOUT MSS_SYS_APB_WRITE_DEBUG_CMD MSS_SYS_AUTHENTICATED_TEXT_DATA_LEN MSS_SYS_BITSTREAM_AUTHENTICATE_CMD MSS_SYS_BITSTREAM_AUTHENTICATE_DATA_LEN MSS_SYS_BSTREAM_AUTH_ABORT_ERR MSS_SYS_BSTREAM_AUTH_AUTOIAP_NO_VALID_IMAGE_ERR MSS_SYS_BSTREAM_AUTH_BACK_LEVEL_NOT_SATISFIED_ERR MSS_SYS_BSTREAM_AUTH_BADCOMPONENT MSS_SYS_BSTREAM_AUTH_CHAINING_MISMATCH_ERR MSS_SYS_BSTREAM_AUTH_DNS_BINDING_MISMATCH_ERR MSS_SYS_BSTREAM_AUTH_HVPROGERR MSS_SYS_BSTREAM_AUTH_HVSTATE MSS_SYS_BSTREAM_AUTH_ILLEGAL_BITSTREAM_MODE_ERR MSS_SYS_BSTREAM_AUTH_ILLEGAL_COMPONENT_SEQUENCE_ERR MSS_SYS_BSTREAM_AUTH_IMAGE_PROGRAM_FAILED_ERR MSS_SYS_BSTREAM_AUTH_INCORRECT_DEVICEID_ERR MSS_SYS_BSTREAM_AUTH_INDEXIAP_NO_VALID_IMAGE_ERR MSS_SYS_BSTREAM_AUTH_INSUFF_DEVICE_CAPAB_ERR MSS_SYS_BSTREAM_AUTH_INVALID_DEV_CERT_ERR MSS_SYS_BSTREAM_AUTH_INVALID_DIB_ERR MSS_SYS_BSTREAM_AUTH_INVALID_ENCRY_KEY_ERR MSS_SYS_BSTREAM_AUTH_INVALID_HEADER_ERR MSS_SYS_BSTREAM_AUTH_INVALID_IMAGE_ERR MSS_SYS_BSTREAM_AUTH_NEWER_DESIGN_VERSION_ERR MSS_SYS_BSTREAM_AUTH_NOTENA MSS_SYS_BSTREAM_AUTH_NVMVERIFY_ERR MSS_SYS_BSTREAM_AUTH_PNVMVERIFY MSS_SYS_BSTREAM_AUTH_PROTECTED_ERR MSS_SYS_BSTREAM_AUTH_PROTOCOL_VERSION_ERR MSS_SYS_BSTREAM_AUTH_SPI_NOT_MASTER_ERR MSS_SYS_BSTREAM_AUTH_SYSTEM MSS_SYS_BSTREAM_AUTH_UNEXPECTED_DATA_ERR MSS_SYS_BSTREAM_AUTH_VERIFY_ERR MSS_SYS_BUSY MSS_SYS_DCF_DEVICE_MISMATCH MSS_SYS_DCF_INVALID_SIGNATURE MSS_SYS_DCF_SYSTEM_ERROR MSS_SYS_DEBUG_SNAPSHOT_BUSERR MSS_SYS_DEBUG_SNAPSHOT_CMD MSS_SYS_DEBUG_SNAPSHOT_DATA_LEN MSS_SYS_DEBUG_SNAPSHOT_SECERR MSS_SYS_DESIGN_INFO_REQUEST_CMD MSS_SYS_DESIGN_INFO_RESP_LEN MSS_SYS_DEVICE_CERTIFICATE_REQUEST_CMD MSS_SYS_DEVICE_CERTIFICATE_RESP_LEN MSS_SYS_DIGEST_CHECK_CC MSS_SYS_DIGEST_CHECK_CMD MSS_SYS_DIGEST_CHECK_DATA_LEN MSS_SYS_DIGEST_CHECK_DIGESTERR MSS_SYS_DIGEST_CHECK_ENVM MSS_SYS_DIGEST_CHECK_FABRIC MSS_SYS_DIGEST_CHECK_SERVICE_RESP_LEN MSS_SYS_DIGEST_CHECK_SNVM MSS_SYS_DIGEST_CHECK_SYS MSS_SYS_DIGEST_CHECK_UKDIGEST0 MSS_SYS_DIGEST_CHECK_UKDIGEST1 MSS_SYS_DIGEST_CHECK_UKDIGEST2 MSS_SYS_DIGEST_CHECK_UKDIGEST3 MSS_SYS_DIGEST_CHECK_UKDIGEST4 MSS_SYS_DIGEST_CHECK_UKDIGEST5 MSS_SYS_DIGEST_CHECK_UKDIGEST6 MSS_SYS_DIGEST_CHECK_UKDIGEST7 MSS_SYS_DIGEST_CHECK_UKDIGEST8 MSS_SYS_DIGEST_CHECK_UKDIGEST9 MSS_SYS_DIGEST_CHECK_UKDIGEST10 MSS_SYS_DIGEST_CHECK_UL MSS_SYS_DIGEST_CHECK_UPERM MSS_SYS_DIGITAL_SIGNATURE_DER_FORMAT_REQUEST_CMD MSS_SYS_DIGITAL_SIGNATURE_DER_FORMAT_RESP_SIZE MSS_SYS_DIGITAL_SIGNATURE_DRBG_ERROR MSS_SYS_DIGITAL_SIGNATURE_ECDSA_ERROR MSS_SYS_DIGITAL_SIGNATURE_FEK_FAILURE_ERROR MSS_SYS_DIGITAL_SIGNATURE_HASH_DATA_LEN MSS_SYS_DIGITAL_SIGNATURE_RAW_FORMAT_REQUEST_CMD MSS_SYS_DIGITAL_SIGNATURE_RAW_FORMAT_RESP_SIZE MSS_SYS_ENVM_DIGEST_ERROR MSS_SYS_GENERATE_OTP_CMD MSS_SYS_GENERATE_OTP_DATA_LEN MSS_SYS_GENERATE_OTP_PROTOCOLERR MSS_SYS_GENERATE_OTP_RESP_LEN MSS_SYS_GENERATE_OTP_SECERR MSS_SYS_IAP_AUTOUPDATE_CMD MSS_SYS_IAP_BITSTREAM_AUTHENTICATE_CMD MSS_SYS_IAP_PROGRAM_BY_SPIADDR_CMD MSS_SYS_IAP_PROGRAM_BY_SPIIDX_CMD MSS_SYS_IAP_SERVICE_DATA_LEN MSS_SYS_IAP_VERIFY_BY_SPIADDR_CMD MSS_SYS_IAP_VERIFY_BY_SPIIDX_CMD MSS_SYS_KM_FACTORY_KEY MSS_SYS_KM_USER_KEY1 MSS_SYS_KM_USER_KEY2 MSS_SYS_LIVE_PROBE_A_DEBUG_CMD MSS_SYS_LIVE_PROBE_B_DEBUG_CMD MSS_SYS_LIVE_PROBE_DEBUG_SERVICE_DATA_LEN MSS_SYS_MATCH_OTP_CMD MSS_SYS_MATCH_OTP_DATA_LEN MSS_SYS_MATCH_OTP_MISMATCHERR MSS_SYS_MATCH_OTP_PROTOCOLERR MSS_SYS_MBOX_ECC_NO_ERROR_MASK MSS_SYS_MBOX_ONEBIT_ERROR_CORRECTED_MASK MSS_SYS_MBOX_TWOBIT_ERROR_MASK MSS_SYS_MEM_LOCKERR MSS_SYS_MEM_READ_DEBUG_CMD MSS_SYS_MEM_READ_WRITE_DATA_LEN MSS_SYS_MEM_SECERR MSS_SYS_MEM_SELECT_DATA_LEN MSS_SYS_MEM_SELECT_DEBUG_CMD MSS_SYS_MEM_TIMEOUTERR MSS_SYS_MEM_WRITE_DEBUG_CMD MSS_SYS_NONCE_PUK_FETCH_ERROR MSS_SYS_NONCE_SEED_GEN_ERROR MSS_SYS_NONCE_SERVICE_REQUEST_CMD MSS_SYS_NONCE_SERVICE_RESP_LEN MSS_SYS_NON_AUTHENTICATED_TEXT_DATA_LEN MSS_SYS_NO_RESPONSE_LEN MSS_SYS_ONE_WAY_PASSCODE_CMD MSS_SYS_ONE_WAY_PASSCODE_DATA_LEN MSS_SYS_OWP_OWPERR MSS_SYS_PARAM_ERR MSS_SYS_PROBE_READ_DEBUG_CMD MSS_SYS_PROBE_READ_SERVICE_DATA_LEN MSS_SYS_PROBE_READ_SERVICE_RESP_LEN MSS_SYS_PROBE_SECERR MSS_SYS_PROBE_WRITE_DEBUG_CMD MSS_SYS_PROBE_WRITE_SERVICE_DATA_LEN MSS_SYS_PUF_EMULATION_SERVICE_CMD_LEN MSS_SYS_PUF_EMULATION_SERVICE_REQUEST_CMD MSS_SYS_PUF_EMULATION_SERVICE_RESP_LEN MSS_SYS_PUF_EMU_INTERNAL_ERR MSS_SYS_QUERY_SECURITY_REQUEST_CMD MSS_SYS_QUERY_SECURITY_RESP_LEN MSS_SYS_READ_DEBUG_INFO_REQUEST_CMD MSS_SYS_READ_DEBUG_INFO_RESP_LEN MSS_SYS_READ_DIGEST_REQUEST_CMD MSS_SYS_READ_DIGEST_RESP_LEN MSS_SYS_READ_ENVM_PARAM_REQUEST_CMD MSS_SYS_READ_ENVM_PARAM_RESP_LEN MSS_SYS_SECURE_NVM_READ_DATA_LEN MSS_SYS_SERIAL_NUMBER_REQUEST_CMD MSS_SYS_SERIAL_NUMBER_RESP_LEN MSS_SYS_SERVICE_INTERRUPT_MODE MSS_SYS_SERVICE_POLLING_MODE MSS_SYS_SNVM_AUTHEN_CIPHERTEXT_REQUEST_CMD MSS_SYS_SNVM_AUTHEN_TEXT_REQUEST_CMD MSS_SYS_SNVM_NON_AUTHEN_TEXT_REQUEST_CMD MSS_SYS_SNVM_READ_AUTHENTICATION_FAILURE MSS_SYS_SNVM_READ_INVALID_SNVMADDR MSS_SYS_SNVM_READ_REQUEST_CMD MSS_SYS_SNVM_READ_SYSTEM_ERROR MSS_SYS_SNVM_WRITE_FAILURE MSS_SYS_SNVM_WRITE_INVALID_SNVMADDR MSS_SYS_SNVM_WRITE_NOT_PERMITTED MSS_SYS_SNVM_WRITE_SYSTEM_ERROR MSS_SYS_SPI_AXI_ERR MSS_SYS_SPI_COPY_CMD MSS_SYS_SPI_COPY_MAILBOX_DATA_LEN MSS_SYS_SPI_MASTER_MODE_ERR MSS_SYS_SUCCESS MSS_SYS_TERMINATE_DEBUG_CMD MSS_SYS_UNLOCK_DEBUG_PASSCODE MSS_SYS_UNLOCK_DEBUG_PASSCODE_DATA_LEN MSS_SYS_UNLOCK_DEBUG_PASSCODE_ERR MSS_SYS_UNLOCK_DEBUG_PASSCODE_SECERR MSS_SYS_USERCODE_REQUEST_CMD MSS_SYS_USERCODE_RESP_LEN MSS_SYS_USER_SECRET_KEY_LEN MSS_SYS_WITHOUT_CMD_DATA MSS_UART_110_BAUD MSS_UART_300_BAUD MSS_UART_600_BAUD MSS_UART_1200_BAUD MSS_UART_2400_BAUD MSS_UART_4800_BAUD MSS_UART_9600_BAUD MSS_UART_19200_BAUD MSS_UART_38400_BAUD MSS_UART_57600_BAUD MSS_UART_115200_BAUD MSS_UART_230400_BAUD MSS_UART_460800_BAUD MSS_UART_921600_BAUD MSS_UART_BREAK_ERROR MSS_UART_CTS MSS_UART_DATA_5_BITS Data Bits Length MSS_UART_DATA_6_BITS MSS_UART_DATA_7_BITS MSS_UART_DATA_8_BITS MSS_UART_DCD MSS_UART_DCTS Modem Status MSS_UART_DDCD MSS_UART_DDSR MSS_UART_DSR MSS_UART_EVEN_PARITY MSS_UART_FIFO_ERROR MSS_UART_FRAMING_ERROR MSS_UART_INVALID_PARAM Receiver Error Status MSS_UART_LINB_IRQ MSS_UART_LINS_IRQ MSS_UART_LS_IRQ MSS_UART_MS_IRQ MSS_UART_NACK_IRQ MSS_UART_NO_ERROR MSS_UART_NO_PARITY Parity MSS_UART_ODD_PARITY MSS_UART_ONEHALF_STOP_BIT MSS_UART_ONE_STOP_BIT Number of Stop Bits MSS_UART_OVERUN_ERROR MSS_UART_PARITY_ERROR MSS_UART_PIDPE_IRQ MSS_UART_RBF_IRQ MSS_UART_RI MSS_UART_RTO_IRQ MSS_UART_STICK_PARITY_0 MSS_UART_STICK_PARITY_1 MSS_UART_TBE_IRQ MSS_UART_TEMT MSS_UART_TERI MSS_UART_THRE MSS_UART_TWO_STOP_BITS MSS_UART_TX_BUSY Transmitter Status MSS_USB_BOOLEAN_FALSE MSS_USB_BOOLEAN_TRUE MSS_USB_BYTE_BIT_0_MASK MSS_USB_WORD_BIT_0_MASK MSS_WDOG_ACTIVE_SLEEP MSS_WDOG_ACTIVE_SLEEP_MASK MSS_WDOG_DEVRST MSS_WDOG_DEVRST_MASK MSS_WDOG_DISABLE MSS_WDOG_ENABLE MSS_WDOG_ENA_FORBIDDEN MSS_WDOG_ENA_FORBIDDEN_MASK MSS_WDOG_FORBIDDEN MSS_WDOG_FORBIDDEN_MASK MSS_WDOG_INTEN_MVRP MSS_WDOG_INTEN_MVRP_MASK MSS_WDOG_INTEN_SLEEP MSS_WDOG_INTEN_SLEEP_MASK MSS_WDOG_INTEN_TRIG MSS_WDOG_INTEN_TRIG_MASK MSS_WDOG_LOCKED MSS_WDOG_LOCKED_MASK MSS_WDOG_MVRP_TRIPPED MSS_WDOG_MVRP_TRIPPED_MASK MSS_WDOG_TIMER_MAX MSS_WDOG_TRIGGERED MSS_WDOG_TRIGGERED_MASK MSS_WDOG_TRIGGER_MAX MSS_WDOG_WDOG_TRIPPED MSS_WDOG_WDOG_TRIPPED_MASK MSTATUS32_SD MSTATUS64_SD MSTATUS_FS MSTATUS_HIE MSTATUS_HPIE MSTATUS_HPP MSTATUS_MIE MSTATUS_MPIE MSTATUS_MPP MSTATUS_MPRV MSTATUS_MXR MSTATUS_SD MSTATUS_SIE MSTATUS_SPIE MSTATUS_SPP MSTATUS_SUM MSTATUS_TSR MSTATUS_TVM MSTATUS_TW MSTATUS_UIE MSTATUS_UPIE MSTATUS_XS MTC_ADD_PATTERN__MTC_ADD_RANDOM < MTC_ADD_PATTERN__MTC_ADD_SEQUENTIAL < MTC_PATTERN__MTC_ALT_5_A < MTC_PATTERN__MTC_ALT_ONES_ZEROS < MTC_PATTERN__MTC_COUNTING_PATTERN < MTC_PATTERN__MTC_NO_REPEATING_PSEUDO_RANDOM < MTC_PATTERN__MTC_PSEUDO_RANDOM < MTC_PATTERN__MTC_PSEUDO_RANDOM_8BIT < MTC_PATTERN__MTC_PSEUDO_RANDOM_16BIT < MTC_PATTERN__MTC_USER < MTC_PATTERN__MTC_WALKING_ONE < MTC_TIMEOUT_ERROR NAKLIMIT0_REG_MASK NB_BANKS NB_SETS NO_ZLP_TO_XFR NULL_PHY NUM_CLAIM_REGS NUM_RPC_166_VALUES NWAYTEST_LOOPBACK NWAYTEST_RESV1 NWAYTEST_RESV2 N_EYE_MASK OFFSET_TO_MSS_GLOBAL_INTS ONE_GB_MTC ONE_MB_MTC PART_TYPE__PART_NOT_DETERMINED < 0 default setting PART_TYPE__PART_REVC_OR_LATER < 1 rev c or later PART_TYPE__PART_TYPE_ARRAY_SIZE < 4 array size PART_TYPE__SS_PART_REVB < 2 SS part rev. B PART_TYPE__TT_PART_REVB < 3 TT part rev. B PATTERN_0x55555555 PATTERN_0xCCCCCCCC PATTERN_INCREMENTAL PATTERN_RANDOM PATTERN_TEST_MAX_OFFSET PATTERN_TEST_MIN_OFFSET PATTERN_TEST_NUM_OFFSET_INCS PATTERN_TEST_NUM_PATTERN_IN_CACHE_READS PATTERN_TEST_SIZE PATTERN_TEST_START_OFFSET PATTERN_WALKING_ONE PATTERN_WALKING_ZERO PATTERN_ZEROS PCIE0_BRIDGE_PHY_ADDR_OFFSET PCIE0_CRTL_PHY_ADDR_OFFSET PCIE1_BRIDGE_PHY_ADDR_OFFSET PCIE1_CRTL_PHY_ADDR_OFFSET PCIESS_MAIN_PHY_ADDR_OFFSET PCIESS_PCS_CMN_PHY_ADDR_OFFSET PCIESS_PCS_LANE0_PHY_ADDR_OFFSET PCIESS_PCS_LANE1_PHY_ADDR_OFFSET PCIESS_PCS_LANE2_PHY_ADDR_OFFSET PCIESS_PCS_LANE3_PHY_ADDR_OFFSET PCIESS_PMA_LANE0_PHY_ADDR_OFFSET PCIESS_PMA_LANE1_PHY_ADDR_OFFSET PCIESS_PMA_LANE2_PHY_ADDR_OFFSET PCIESS_PMA_LANE3_PHY_ADDR_OFFSET PCIESS_TXPLL0_PHY_ADDR_OFFSET PCIESS_TXPLL1_PHY_ADDR_OFFSET PCIESS_TXPLL_SSC_PHY_ADDR_OFFSET PDMA_CH0_DONE_INT PDMA_CH0_ERROR_INT PDMA_CH1_DONE_INT PDMA_CH1_ERROR_INT PDMA_CH2_DONE_INT PDMA_CH2_ERROR_INT PDMA_CH3_DONE_INT PDMA_CH3_ERROR_INT PERIPH_RESET_STATE__PERIPHERAL_OFF < 1 RST and clk OFF PERIPH_RESET_STATE__PERIPHERAL_ON < 0 RST and clk ON PF_PCIE_ATR_TABLE_DISABLE PF_PCIE_ATR_TABLE_ENABLE PF_PCIE_ATR_TABLE_INIT_FAILURE PF_PCIE_ATR_TABLE_INIT_SUCCESS PF_PCIE_CTRL_0 PF_PCIE_CTRL_1 PHYCR_DEEP_POWER_DOWN_EN PHYCR_DISABLE_CLK_125 PHYCR_DISABLE_JABBER PHYCR_FORCE_LINK_GOOD PHYCR_LINE_DRIVER_INV_EN PHYCR_MDI_CROSSOVER PHYCR_POWER_SAVE_MODE PHYCR_RX_FIFO_DEPTH PHYCR_SGMII_EN PHYCR_STANDBY_MODE PHYCR_TX_FIFO_DEPTH PHY_DP83867_MDIO_ADDR PHY_NULL_MDIO_ADDR PHY_RTL8211_MDIO_ADDR PHY_VSC8541_MDIO_ADDR PHY_VSC8575_MDIO_ADDR PHY_VSC8662_0_MDIO_ADDR PHY_VSC8662_1_MDIO_ADDR PLIC_BASE_ADDR PLIC_IRQn_Type_ATHENA_ALARM_INT_OFFSET PLIC_IRQn_Type_ATHENA_BUS_ERROR_INT_OFFSET PLIC_IRQn_Type_ATHENA_COMPLETE_INT_OFFSET PLIC_IRQn_Type_E51_0_MAINTENACE_INT_OFFSET PLIC_IRQn_Type_G5C_DEVRST_INT_OFFSET PLIC_IRQn_Type_G5C_MSS_SPI_INT_OFFSET PLIC_IRQn_Type_PLIC_CAN0_INT_OFFSET PLIC_IRQn_Type_PLIC_CAN1_INT_OFFSET PLIC_IRQn_Type_PLIC_DDRC_TRAIN_INT_OFFSET PLIC_IRQn_Type_PLIC_DMA_CH0_DONE_INT_OFFSET PLIC_IRQn_Type_PLIC_DMA_CH0_ERR_INT_OFFSET PLIC_IRQn_Type_PLIC_DMA_CH1_DONE_INT_OFFSET PLIC_IRQn_Type_PLIC_DMA_CH1_ERR_INT_OFFSET PLIC_IRQn_Type_PLIC_DMA_CH2_DONE_INT_OFFSET PLIC_IRQn_Type_PLIC_DMA_CH2_ERR_INT_OFFSET PLIC_IRQn_Type_PLIC_DMA_CH3_DONE_INT_OFFSET PLIC_IRQn_Type_PLIC_DMA_CH3_ERR_INT_OFFSET PLIC_IRQn_Type_PLIC_E51_BUS_ERROR_UNIT_OFFSET PLIC_IRQn_Type_PLIC_ECC_CORRECT_INT_OFFSET PLIC_IRQn_Type_PLIC_ECC_ERROR_INT_OFFSET PLIC_IRQn_Type_PLIC_ENVM_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_0_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_1_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_2_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_3_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_4_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_5_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_6_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_7_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_8_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_9_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_10_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_11_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_12_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_13_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_14_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_15_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_16_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_17_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_18_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_19_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_20_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_21_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_22_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_23_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_24_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_25_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_26_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_27_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_28_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_29_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_30_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_31_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_32_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_33_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_34_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_35_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_36_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_37_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_38_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_39_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_40_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_41_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_42_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_43_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_44_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_45_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_46_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_47_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_48_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_49_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_50_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_51_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_52_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_53_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_54_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_55_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_56_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_57_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_58_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_59_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_60_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_61_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_62_INT_OFFSET PLIC_IRQn_Type_PLIC_F2M_63_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO0_BIT0_or_GPIO2_BIT0_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO0_BIT1_or_GPIO2_BIT1_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO0_BIT2_or_GPIO2_BIT2_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO0_BIT3_or_GPIO2_BIT3_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO0_BIT4_or_GPIO2_BIT4_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO0_BIT5_or_GPIO2_BIT5_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO0_BIT6_or_GPIO2_BIT6_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO0_BIT7_or_GPIO2_BIT7_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO0_BIT8_or_GPIO2_BIT8_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO0_BIT9_or_GPIO2_BIT9_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO0_BIT10_or_GPIO2_BIT10_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO0_BIT11_or_GPIO2_BIT11_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO0_BIT12_or_GPIO2_BIT12_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO0_BIT13_or_GPIO2_BIT13_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO0_NON_DIRECT_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT0_or_GPIO2_BIT14_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT1_or_GPIO2_BIT15_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT2_or_GPIO2_BIT16_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT3_or_GPIO2_BIT17_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT4_or_GPIO2_BIT18_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT5_or_GPIO2_BIT19_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT6_or_GPIO2_BIT20_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT7_or_GPIO2_BIT21_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT8_or_GPIO2_BIT22_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT9_or_GPIO2_BIT23_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT10_or_GPIO2_BIT24_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT11_or_GPIO2_BIT25_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT12_or_GPIO2_BIT26_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT13_or_GPIO2_BIT27_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT14_or_GPIO2_BIT28_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT15_or_GPIO2_BIT29_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT16_or_GPIO2_BIT30_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT17_or_GPIO2_BIT31_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT18_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT19_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT20_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT21_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT22_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_BIT23_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO1_NON_DIRECT_INT_OFFSET PLIC_IRQn_Type_PLIC_GPIO2_NON_DIRECT_INT_OFFSET PLIC_IRQn_Type_PLIC_I2C0_ALERT_INT_OFFSET PLIC_IRQn_Type_PLIC_I2C0_MAIN_INT_OFFSET PLIC_IRQn_Type_PLIC_I2C0_SUS_INT_OFFSET PLIC_IRQn_Type_PLIC_I2C1_ALERT_INT_OFFSET PLIC_IRQn_Type_PLIC_I2C1_MAIN_INT_OFFSET PLIC_IRQn_Type_PLIC_I2C1_SUS_INT_OFFSET PLIC_IRQn_Type_PLIC_INVALID_INT_OFFSET PLIC_IRQn_Type_PLIC_L2_DATA_CORR_INT_OFFSET PLIC_IRQn_Type_PLIC_L2_DATA_UNCORR_INT_OFFSET PLIC_IRQn_Type_PLIC_L2_METADATA_CORR_INT_OFFSET PLIC_IRQn_Type_PLIC_L2_METADAT_UNCORR_INT_OFFSET PLIC_IRQn_Type_PLIC_MAC0_EMAC_INT_OFFSET PLIC_IRQn_Type_PLIC_MAC0_INT_INT_OFFSET PLIC_IRQn_Type_PLIC_MAC0_MMSL_INT_OFFSET PLIC_IRQn_Type_PLIC_MAC0_QUEUE1_INT_OFFSET PLIC_IRQn_Type_PLIC_MAC0_QUEUE2_INT_OFFSET PLIC_IRQn_Type_PLIC_MAC0_QUEUE3_INT_OFFSET PLIC_IRQn_Type_PLIC_MAC1_EMAC_INT_OFFSET PLIC_IRQn_Type_PLIC_MAC1_INT_INT_OFFSET PLIC_IRQn_Type_PLIC_MAC1_MMSL_INT_OFFSET PLIC_IRQn_Type_PLIC_MAC1_QUEUE1_INT_OFFSET PLIC_IRQn_Type_PLIC_MAC1_QUEUE2_INT_OFFSET PLIC_IRQn_Type_PLIC_MAC1_QUEUE3_INT_OFFSET PLIC_IRQn_Type_PLIC_MMC_main_INT_OFFSET PLIC_IRQn_Type_PLIC_MMC_wakeup_INT_OFFSET PLIC_IRQn_Type_PLIC_MMUART0_INT_OFFSET PLIC_IRQn_Type_PLIC_MMUART1_INT_OFFSET PLIC_IRQn_Type_PLIC_MMUART2_INT_OFFSET PLIC_IRQn_Type_PLIC_MMUART3_INT_OFFSET PLIC_IRQn_Type_PLIC_MMUART4_INT_OFFSET PLIC_IRQn_Type_PLIC_QSPI_INT_OFFSET PLIC_IRQn_Type_PLIC_RTC_MATCH_INT_OFFSET PLIC_IRQn_Type_PLIC_RTC_WAKEUP_INT_OFFSET PLIC_IRQn_Type_PLIC_SCB_INTERRUPT_INT_OFFSET PLIC_IRQn_Type_PLIC_SPI0_INT_OFFSET PLIC_IRQn_Type_PLIC_SPI1_INT_OFFSET PLIC_IRQn_Type_PLIC_TIMER1_INT_OFFSET PLIC_IRQn_Type_PLIC_TIMER2_INT_OFFSET PLIC_IRQn_Type_PLIC_U54_1_BUS_ERROR_UNIT_OFFSET PLIC_IRQn_Type_PLIC_U54_2_BUS_ERROR_UNIT_OFFSET PLIC_IRQn_Type_PLIC_U54_3_BUS_ERROR_UNIT_OFFSET PLIC_IRQn_Type_PLIC_U54_4_BUS_ERROR_UNIT_OFFSET PLIC_IRQn_Type_PLIC_USB_DMA_INT_OFFSET PLIC_IRQn_Type_PLIC_USB_MC_INT_OFFSET PLIC_IRQn_Type_PLIC_WDOG0_MRVP_INT_OFFSET PLIC_IRQn_Type_PLIC_WDOG0_TOUT_INT_OFFSET PLIC_IRQn_Type_PLIC_WDOG1_MRVP_INT_OFFSET PLIC_IRQn_Type_PLIC_WDOG1_TOUT_INT_OFFSET PLIC_IRQn_Type_PLIC_WDOG2_MRVP_INT_OFFSET PLIC_IRQn_Type_PLIC_WDOG2_TOUT_INT_OFFSET PLIC_IRQn_Type_PLIC_WDOG3_MRVP_INT_OFFSET PLIC_IRQn_Type_PLIC_WDOG3_TOUT_INT_OFFSET PLIC_IRQn_Type_PLIC_WDOG4_MRVP_INT_OFFSET PLIC_IRQn_Type_PLIC_WDOG4_TOUT_INT_OFFSET PLIC_IRQn_Type_USOC_AXIC_DS_INT_OFFSET PLIC_IRQn_Type_USOC_AXIC_US_INT_OFFSET PLIC_IRQn_Type_USOC_SMB_INTERRUPT_INT_OFFSET PLIC_IRQn_Type_USOC_VC_INTERRUPT_INT_OFFSET PLIC_IRQn_Type_VOLT_TEMP_ALARM_INT_OFFSET PLIC_IRQn_Type_g5c_MESSAGE_INT_OFFSET PLIC_NUM_PRIORITIES PLIC_NUM_SOURCES PLIC_SET_UP_REGISTERS PLL_CTRL_LOCK_BIT PLL_CTRL_REG_POWERDOWN_B_MASK PLL_INIT_AND_OUT_OF_RESET PLL_STATUS_INTEN_CR_CPU_LOCK_MASK PLL_STATUS_INTEN_CR_CPU_LOCK_OFFSET PLL_STATUS_INTEN_CR_CPU_UNLOCK_MASK PLL_STATUS_INTEN_CR_CPU_UNLOCK_OFFSET PLL_STATUS_INTEN_CR_DFI_LOCK_MASK PLL_STATUS_INTEN_CR_DFI_LOCK_OFFSET PLL_STATUS_INTEN_CR_DFI_UNLOCK_MASK PLL_STATUS_INTEN_CR_DFI_UNLOCK_OFFSET PLL_STATUS_INTEN_CR_OFFSET PLL_STATUS_INTEN_CR_SGMII_LOCK_MASK PLL_STATUS_INTEN_CR_SGMII_LOCK_OFFSET PLL_STATUS_INTEN_CR_SGMII_UNLOCK_MASK PLL_STATUS_INTEN_CR_SGMII_UNLOCK_OFFSET PLL_STATUS_SR_CPU_LOCK_MASK PLL_STATUS_SR_CPU_LOCK_NOW_MASK PLL_STATUS_SR_CPU_LOCK_NOW_OFFSET PLL_STATUS_SR_CPU_LOCK_OFFSET PLL_STATUS_SR_CPU_UNLOCK_MASK PLL_STATUS_SR_CPU_UNLOCK_OFFSET PLL_STATUS_SR_DFI_LOCK_MASK PLL_STATUS_SR_DFI_LOCK_NOW_MASK PLL_STATUS_SR_DFI_LOCK_NOW_OFFSET PLL_STATUS_SR_DFI_LOCK_OFFSET PLL_STATUS_SR_DFI_UNLOCK_MASK PLL_STATUS_SR_DFI_UNLOCK_OFFSET PLL_STATUS_SR_OFFSET PLL_STATUS_SR_SGMII_LOCK_MASK PLL_STATUS_SR_SGMII_LOCK_NOW_MASK PLL_STATUS_SR_SGMII_LOCK_NOW_OFFSET PLL_STATUS_SR_SGMII_LOCK_OFFSET PLL_STATUS_SR_SGMII_UNLOCK_MASK PLL_STATUS_SR_SGMII_UNLOCK_OFFSET PMP_A PMP_ENABLED_MASK PMP_L PMP_NA4 PMP_NAPOT PMP_R PMP_SHIFT PMP_TOR PMP_W PMP_X POWER_REG_BUS_RESET_SIGNAL_MASK POWER_REG_ENABLE_HS_MASK POWER_REG_ENABLE_SUSPENDM_MASK POWER_REG_HS_MODE_MASK POWER_REG_ISO_UPDATE_MASK POWER_REG_RESUME_SIGNAL_MASK POWER_REG_SOFT_CONN_MASK POWER_REG_SUSPEND_MODE_MASK PRV_H PRV_M PRV_S PRV_U PTE_A PTE_D PTE_G PTE_PPN_SHIFT PTE_R PTE_SOFT PTE_U PTE_V PTE_W PTE_X QOS_CPLEXDDR_CR_CACHE_READ_MASK QOS_CPLEXDDR_CR_CACHE_READ_OFFSET QOS_CPLEXDDR_CR_CACHE_WRITE_MASK QOS_CPLEXDDR_CR_CACHE_WRITE_OFFSET QOS_CPLEXDDR_CR_NCACHE_READ_MASK QOS_CPLEXDDR_CR_NCACHE_READ_OFFSET QOS_CPLEXDDR_CR_NCACHE_WRITE_MASK QOS_CPLEXDDR_CR_NCACHE_WRITE_OFFSET QOS_CPLEXDDR_CR_OFFSET QOS_CPLEXIO_CR_DEVICE0_READ_MASK QOS_CPLEXIO_CR_DEVICE0_READ_OFFSET QOS_CPLEXIO_CR_DEVICE0_WRITE_MASK QOS_CPLEXIO_CR_DEVICE0_WRITE_OFFSET QOS_CPLEXIO_CR_DEVICE1_READ_MASK QOS_CPLEXIO_CR_DEVICE1_READ_OFFSET QOS_CPLEXIO_CR_DEVICE1_WRITE_MASK QOS_CPLEXIO_CR_DEVICE1_WRITE_OFFSET QOS_CPLEXIO_CR_FABRIC0_READ_MASK QOS_CPLEXIO_CR_FABRIC0_READ_OFFSET QOS_CPLEXIO_CR_FABRIC0_WRITE_MASK QOS_CPLEXIO_CR_FABRIC0_WRITE_OFFSET QOS_CPLEXIO_CR_FABRIC1_READ_MASK QOS_CPLEXIO_CR_FABRIC1_READ_OFFSET QOS_CPLEXIO_CR_FABRIC1_WRITE_MASK QOS_CPLEXIO_CR_FABRIC1_WRITE_OFFSET QOS_CPLEXIO_CR_OFFSET QOS_PERIPHERAL_CR_ATHENA_READ_MASK QOS_PERIPHERAL_CR_ATHENA_READ_OFFSET QOS_PERIPHERAL_CR_ATHENA_WRITE_MASK QOS_PERIPHERAL_CR_ATHENA_WRITE_OFFSET QOS_PERIPHERAL_CR_MMC_READ_MASK QOS_PERIPHERAL_CR_MMC_READ_OFFSET QOS_PERIPHERAL_CR_MMC_WRITE_MASK QOS_PERIPHERAL_CR_MMC_WRITE_OFFSET QOS_PERIPHERAL_CR_OFFSET QOS_PERIPHERAL_CR_TRACE_READ_MASK QOS_PERIPHERAL_CR_TRACE_READ_OFFSET QOS_PERIPHERAL_CR_TRACE_WRITE_MASK QOS_PERIPHERAL_CR_TRACE_WRITE_OFFSET QOS_PERIPHERAL_CR_USB_READ_MASK QOS_PERIPHERAL_CR_USB_READ_OFFSET QOS_PERIPHERAL_CR_USB_WRITE_MASK QOS_PERIPHERAL_CR_USB_WRITE_OFFSET QSPI QSPI_BASE RAM_DEEPSLEEP_CR_ATHENA_MASK RAM_DEEPSLEEP_CR_ATHENA_OFFSET RAM_DEEPSLEEP_CR_CAN0_MASK RAM_DEEPSLEEP_CR_CAN0_OFFSET RAM_DEEPSLEEP_CR_CAN1_MASK RAM_DEEPSLEEP_CR_CAN1_OFFSET RAM_DEEPSLEEP_CR_DDRC_MASK RAM_DEEPSLEEP_CR_DDRC_OFFSET RAM_DEEPSLEEP_CR_E51_MASK RAM_DEEPSLEEP_CR_E51_OFFSET RAM_DEEPSLEEP_CR_GEM0_MASK RAM_DEEPSLEEP_CR_GEM0_OFFSET RAM_DEEPSLEEP_CR_GEM1_MASK RAM_DEEPSLEEP_CR_GEM1_OFFSET RAM_DEEPSLEEP_CR_L2_MASK RAM_DEEPSLEEP_CR_L2_OFFSET RAM_DEEPSLEEP_CR_MMC_MASK RAM_DEEPSLEEP_CR_MMC_OFFSET RAM_DEEPSLEEP_CR_OFFSET RAM_DEEPSLEEP_CR_U54_1_MASK RAM_DEEPSLEEP_CR_U54_1_OFFSET RAM_DEEPSLEEP_CR_U54_2_MASK RAM_DEEPSLEEP_CR_U54_2_OFFSET RAM_DEEPSLEEP_CR_U54_3_MASK RAM_DEEPSLEEP_CR_U54_3_OFFSET RAM_DEEPSLEEP_CR_U54_4_MASK RAM_DEEPSLEEP_CR_U54_4_OFFSET RAM_DEEPSLEEP_CR_USB_MASK RAM_DEEPSLEEP_CR_USB_OFFSET RAM_LIGHTSLEEP_CR_ATHENA_MASK RAM_LIGHTSLEEP_CR_ATHENA_OFFSET RAM_LIGHTSLEEP_CR_CAN0_MASK RAM_LIGHTSLEEP_CR_CAN0_OFFSET RAM_LIGHTSLEEP_CR_CAN1_MASK RAM_LIGHTSLEEP_CR_CAN1_OFFSET RAM_LIGHTSLEEP_CR_DDRC_MASK RAM_LIGHTSLEEP_CR_DDRC_OFFSET RAM_LIGHTSLEEP_CR_E51_MASK RAM_LIGHTSLEEP_CR_E51_OFFSET RAM_LIGHTSLEEP_CR_GEM0_MASK RAM_LIGHTSLEEP_CR_GEM0_OFFSET RAM_LIGHTSLEEP_CR_GEM1_MASK RAM_LIGHTSLEEP_CR_GEM1_OFFSET RAM_LIGHTSLEEP_CR_L2_MASK RAM_LIGHTSLEEP_CR_L2_OFFSET RAM_LIGHTSLEEP_CR_MMC_MASK RAM_LIGHTSLEEP_CR_MMC_OFFSET RAM_LIGHTSLEEP_CR_OFFSET RAM_LIGHTSLEEP_CR_U54_1_MASK RAM_LIGHTSLEEP_CR_U54_1_OFFSET RAM_LIGHTSLEEP_CR_U54_2_MASK RAM_LIGHTSLEEP_CR_U54_2_OFFSET RAM_LIGHTSLEEP_CR_U54_3_MASK RAM_LIGHTSLEEP_CR_U54_3_OFFSET RAM_LIGHTSLEEP_CR_U54_4_MASK RAM_LIGHTSLEEP_CR_U54_4_OFFSET RAM_LIGHTSLEEP_CR_USB_MASK RAM_LIGHTSLEEP_CR_USB_OFFSET RAM_SHUTDOWN_CR_ATHENA_MASK RAM_SHUTDOWN_CR_ATHENA_OFFSET RAM_SHUTDOWN_CR_CAN0_MASK RAM_SHUTDOWN_CR_CAN0_OFFSET RAM_SHUTDOWN_CR_CAN1_MASK RAM_SHUTDOWN_CR_CAN1_OFFSET RAM_SHUTDOWN_CR_DDRC_MASK RAM_SHUTDOWN_CR_DDRC_OFFSET RAM_SHUTDOWN_CR_E51_MASK RAM_SHUTDOWN_CR_E51_OFFSET RAM_SHUTDOWN_CR_GEM0_MASK RAM_SHUTDOWN_CR_GEM0_OFFSET RAM_SHUTDOWN_CR_GEM1_MASK RAM_SHUTDOWN_CR_GEM1_OFFSET RAM_SHUTDOWN_CR_L2_MASK RAM_SHUTDOWN_CR_L2_OFFSET RAM_SHUTDOWN_CR_MMC_MASK RAM_SHUTDOWN_CR_MMC_OFFSET RAM_SHUTDOWN_CR_OFFSET RAM_SHUTDOWN_CR_U54_1_MASK RAM_SHUTDOWN_CR_U54_1_OFFSET RAM_SHUTDOWN_CR_U54_2_MASK RAM_SHUTDOWN_CR_U54_2_OFFSET RAM_SHUTDOWN_CR_U54_3_MASK RAM_SHUTDOWN_CR_U54_3_OFFSET RAM_SHUTDOWN_CR_U54_4_MASK RAM_SHUTDOWN_CR_U54_4_OFFSET RAM_SHUTDOWN_CR_USB_MASK RAM_SHUTDOWN_CR_USB_OFFSET RDAT RDAT_MASK RDGATE_BIT REGBYTES REG_CDR_MOVE_STEP REG_LOAD_METHOD__RPC_REG_UPDATE < 1 RPC -> SCB load REG_LOAD_METHOD__SCB_UPDATE < 0 SCB direct load REG_RX0_EN_FLAG_N REG_RX0_EN_OFFSET REG_RX0_EYEWIDTH_P_MASK REG_RX1_EN_FLAG_N REG_RX1_EN_OFFSET REG_RX1_EYEWIDTH_P_MASK RESERVED_BC_OFFSET RESERVED_BC_RESERVED_MASK RESERVED_BC_RESERVED_OFFSET RESET_IRQ_MASK RESET_SR_CPU_SOFTCB_BUS_RESET_MASK RESET_SR_CPU_SOFT_RESET_OFFSET RESET_SR_DEBUGER_RESET_MASK RESET_SR_DEBUGER_RESET_OFFSET RESET_SR_FABRIC_RESET_MASK RESET_SR_FABRIC_RESET_OFFSET RESET_SR_GPIO_RESET_MASK RESET_SR_GPIO_RESET_OFFSET RESET_SR_OFFSET RESET_SR_SCB_BUS_RESET_MASK RESET_SR_SCB_BUS_RESET_OFFSET RESET_SR_SCB_CPU_RESET_MASK RESET_SR_SCB_CPU_RESET_OFFSET RESET_SR_SCB_MSS_RESET_MASK RESET_SR_SCB_MSS_RESET_OFFSET RESET_SR_SCB_PERIPH_RESET_MASK RESET_SR_SCB_PERIPH_RESET_OFFSET RESET_SR_WDOG_RESET_MASK RESET_SR_WDOG_RESET_OFFSET RESUME_IRQ_MASK RISCV_PGLEVEL_BITS RISCV_PGSHIFT RISCV_PGSIZE RPC_OVERRIDE_166_LANE_FIFO RTC_CLK_SOURCE__MSS_PLL_CLOCK < 1 MSS PLL clock source RTC_CLK_SOURCE__SCB_80M_CLOCK < 0 SCB clock source RTC_CLOCK_CR_ENABLE_MASK RTC_CLOCK_CR_ENABLE_OFFSET RTC_CLOCK_CR_OFFSET RTC_CLOCK_CR_PERIOD_MASK RTC_CLOCK_CR_PERIOD_OFFSET RTC_PRESCALER RXCSRH_HOST_EPN_DATA_TOG_MASK RXCSRH_HOST_EPN_DATA_TOG_WE_MASK RXCSRH_HOST_EPN_DMA_MODE_MASK RXCSRH_HOST_EPN_ENABLE_AUTOCLR_MASK RXCSRH_HOST_EPN_ENABLE_AUTOREQ_MASK RXCSRH_HOST_EPN_ENABLE_DMA_MASK RXCSRH_HOST_EPN_PID_ERR_MASK RXCSRH_HOST_EPN_RX_ISO_INCOMP RXCSRL_HOST_EPN_CLR_DATA_TOG_MASK RXCSRL_HOST_EPN_FLUSH_FIFO_MASK RXCSRL_HOST_EPN_IN_PKT_REQ_MASK RXCSRL_HOST_EPN_NAK_TIMEOUT_ERR_MASK RXCSRL_HOST_EPN_RESPONSE_ERR_MASK RXCSRL_HOST_EPN_RX_FIFO_FULL_MASK RXCSRL_HOST_EPN_RX_PKT_RDY_MASK RXCSRL_HOST_EPN_STALL_RCVD_MASK RXFIFOSZ_REG_DPB_SHIFT RXINTERVAL_HOST_REG_MASK RXTYPE_HOST_TARGET_EP_NUM_MASK RXTYPE_HOST_TARGET_EP_NUM_SHIFT RXTYPE_HOST_TARGET_EP_PROTOCOL_MASK RXTYPE_HOST_TARGET_EP_PROTOCOL_SHIFT RXTYPE_HOST_TARGET_EP_SPEED_MASK RXTYPE_HOST_TARGET_EP_SPEED_SHIFT RX_EP_DATA_ERROR RX_EP_ISO_INCOMP_ERROR RX_EP_OVER_RUN_ERROR RX_EP_PID_ERROR RX_EP_STALL_ERROR RX_MAX_P_REG_NUM_USB_PKT_SHIFT RxCSRL_REG_EPN_BI_DIS_NYET_MASK RxCSRL_REG_EPN_CLR_DAT_TOG_MASK RxCSRL_REG_EPN_DATA_ERR_MASK RxCSRL_REG_EPN_DMA_MODE_MASK RxCSRL_REG_EPN_ENABLE_AUTOCLR_MASK RxCSRL_REG_EPN_ENABLE_DMA_MASK RxCSRL_REG_EPN_ENABLE_ISO_MASK RxCSRL_REG_EPN_FLUSH_FIFO_MASK RxCSRL_REG_EPN_ISO_PID_ERR_MASK RxCSRL_REG_EPN_OVERRUN_MASK RxCSRL_REG_EPN_RX_FIFO_FULL_MASK RxCSRL_REG_EPN_RX_ISO_INCOMP RxCSRL_REG_EPN_RX_PKT_RDY_MASK RxCSRL_REG_EPN_SEND_STALL_MASK RxCSRL_REG_EPN_STALL_SENT_MASK SC_ABORTED_COMMAND SC_BLANK_CHECK SC_COPY_ABORTED SC_DATA_PROTECT SC_HARDWARE_ERR SC_ILLEGAL_REQUEST SC_MEDIUM_ERROR SC_MISCOMPARE SC_NOT_READY SC_NO_SENSE SC_RECOVERED_ERR SC_UNIT_ATTENTION SC_VENDOR_SPECIFIC SC_VOLUME_OVERFLOW SD_CONFIGURED_MASK SEG_SETUP__DEFAULT_SEG_SETUP SEG_SETUP__LIBERO_SEG_SETUP SESSION_REQUEST_IRQ_MASK SETUP_PKT_SIZE SGMIIPHY_LANE01_BASE SGMIIPHY_LANE23_BASE SGMII_FINISHED_SETUP SGMII_IN_SETUP SGMII_MDIO_ADDR SGMII_TRAINING_SM__SGMII_ASSERT_CALIB_LOCK SGMII_TRAINING_SM__SGMII_CHANNELS_UP SGMII_TRAINING_SM__SGMII_CHECK_REVC_RESULT SGMII_TRAINING_SM__SGMII_DETERMINE_SILICON_VARIANT SGMII_TRAINING_SM__SGMII_IO_EN SGMII_TRAINING_SM__SGMII_IO_SETUP SGMII_TRAINING_SM__SGMII_RAMP_TIMER SGMII_TRAINING_SM__SGMII_RESET_CHANNELS SGMII_TRAINING_SM__SGMII_SETUP_INIT < SGMII_TRAINING_INIT SGMII_TRAINING_SM__SGMII_SET_UP_PLL SGMII_TRAINING_SM__SGMII_TURN_ON_MACS SGMII_TRAINING_SM__SGMII_WAIT_10MS SGMII_TRAINING_SM__SGMII_WAIT_FOR_CALIB_COMPLETE SGMII_TRAINING_SM__SGMII_WAIT_FOR_DLL_LOCK SGMII_TRAINING_SM__SGMII_WAIT_FOR_MSS_LOCK SGMII_TYPE_6_WIRE SHARED_MEM_DEFAULT_STATUS SHARED_MEM_INITALISED_MARKER SHIFT_TO_CH0_N_EYE_VALUE SHIFT_TO_CH1_N_EYE_VALUE SHIFT_TO_REG_RX0_EYEWIDTH SHIFT_TO_REG_RX1_EYEWIDTH SHUTDOWN_CACHE_CC24_00_07_MASK SHUTDOWN_CACHE_CC24_08_15_MASK SHUTDOWN_CACHE_CC24_16_23_MASK SHUTDOWN_CACHE_CC24_24_31_MASK SOFT_FLOAT_CONTEXT_SIZE SOFT_RESET_CR_ATHENA_MASK SOFT_RESET_CR_ATHENA_OFFSET SOFT_RESET_CR_CAN0_MASK SOFT_RESET_CR_CAN0_OFFSET SOFT_RESET_CR_CAN1_MASK SOFT_RESET_CR_CAN1_OFFSET SOFT_RESET_CR_CFM_MASK SOFT_RESET_CR_CFM_OFFSET SOFT_RESET_CR_DDRC_MASK SOFT_RESET_CR_DDRC_OFFSET SOFT_RESET_CR_ENVM_MASK SOFT_RESET_CR_ENVM_OFFSET SOFT_RESET_CR_FIC0_MASK SOFT_RESET_CR_FIC0_OFFSET SOFT_RESET_CR_FIC1_MASK SOFT_RESET_CR_FIC1_OFFSET SOFT_RESET_CR_FIC2_MASK SOFT_RESET_CR_FIC2_OFFSET SOFT_RESET_CR_FIC3_MASK SOFT_RESET_CR_FIC3_OFFSET SOFT_RESET_CR_FPGA_MASK SOFT_RESET_CR_FPGA_OFFSET SOFT_RESET_CR_GPIO0_MASK SOFT_RESET_CR_GPIO0_OFFSET SOFT_RESET_CR_GPIO1_MASK SOFT_RESET_CR_GPIO1_OFFSET SOFT_RESET_CR_GPIO2_MASK SOFT_RESET_CR_GPIO2_OFFSET SOFT_RESET_CR_I2C0_MASK SOFT_RESET_CR_I2C0_OFFSET SOFT_RESET_CR_I2C1_MASK SOFT_RESET_CR_I2C1_OFFSET SOFT_RESET_CR_MAC0_MASK SOFT_RESET_CR_MAC0_OFFSET SOFT_RESET_CR_MAC1_MASK SOFT_RESET_CR_MAC1_OFFSET SOFT_RESET_CR_MMC_MASK SOFT_RESET_CR_MMC_OFFSET SOFT_RESET_CR_MMUART0_MASK SOFT_RESET_CR_MMUART0_OFFSET SOFT_RESET_CR_MMUART1_MASK SOFT_RESET_CR_MMUART1_OFFSET SOFT_RESET_CR_MMUART2_MASK SOFT_RESET_CR_MMUART2_OFFSET SOFT_RESET_CR_MMUART3_MASK SOFT_RESET_CR_MMUART3_OFFSET SOFT_RESET_CR_MMUART4_MASK SOFT_RESET_CR_MMUART4_OFFSET SOFT_RESET_CR_OFFSET SOFT_RESET_CR_QSPI_MASK SOFT_RESET_CR_QSPI_OFFSET SOFT_RESET_CR_RTC_MASK SOFT_RESET_CR_RTC_OFFSET SOFT_RESET_CR_SGMII_MASK SOFT_RESET_CR_SGMII_OFFSET SOFT_RESET_CR_SPI0_MASK SOFT_RESET_CR_SPI0_OFFSET SOFT_RESET_CR_SPI1_MASK SOFT_RESET_CR_SPI1_OFFSET SOFT_RESET_CR_TIMER_MASK SOFT_RESET_CR_TIMER_OFFSET SOFT_RESET_CR_USB_MASK SOFT_RESET_CR_USB_OFFSET SOFT_RESET_REG_MASK SOF_IRQ_MASK SPARE_FIC_OFFSET SPARE_FIC_RESET_MASK SPARE_FIC_RESET_OFFSET SPARE_PERIM_RW_DATA_MASK SPARE_PERIM_RW_DATA_OFFSET SPARE_PERIM_RW_OFFSET SPARE_REGISTER_RO_DATA_MASK SPARE_REGISTER_RO_DATA_OFFSET SPARE_REGISTER_RO_OFFSET SPARE_REGISTER_RW_DATA_MASK SPARE_REGISTER_RW_DATA_OFFSET SPARE_REGISTER_RW_OFFSET SPARE_REGISTER_W1P_DATA_MASK SPARE_REGISTER_W1P_DATA_OFFSET SPARE_REGISTER_W1P_OFFSET SPTBR32_ASID SPTBR32_MODE SPTBR32_PPN SPTBR64_ASID SPTBR64_MODE SPTBR64_PPN SPTBR_MODE SPTBR_MODE_OFF SPTBR_MODE_SV32 SPTBR_MODE_SV39 SPTBR_MODE_SV48 SPTBR_MODE_SV57 SPTBR_MODE_SV64 SSTATUS32_SD SSTATUS64_SD SSTATUS_FS SSTATUS_MXR SSTATUS_SD SSTATUS_SIE SSTATUS_SPIE SSTATUS_SPP SSTATUS_SUM SSTATUS_UIE SSTATUS_UPIE SSTATUS_XS STTS_FLAGSX4 STTS_FLAGSX4_MASK STTS_RAVLB STTS_RAVLB_MASK STTS_RDONE STTS_RDONE_MASK STTS_READY STTS_READY_MASK STTS_RFEMPTY STTS_RFEMPTY_MASK STTS_TAVLB STTS_TAVLB_MASK STTS_TDONE STTS_TDONE_MASK STTS_TFFULL STTS_TFFULL_MASK SUBBLK_CLOCK_CR_ATHENA_MASK SUBBLK_CLOCK_CR_ATHENA_OFFSET SUBBLK_CLOCK_CR_CAN0_MASK SUBBLK_CLOCK_CR_CAN0_OFFSET SUBBLK_CLOCK_CR_CAN1_MASK SUBBLK_CLOCK_CR_CAN1_OFFSET SUBBLK_CLOCK_CR_CFM_MASK SUBBLK_CLOCK_CR_CFM_OFFSET SUBBLK_CLOCK_CR_DDRC_MASK SUBBLK_CLOCK_CR_DDRC_OFFSET SUBBLK_CLOCK_CR_ENVM_MASK SUBBLK_CLOCK_CR_ENVM_OFFSET SUBBLK_CLOCK_CR_FIC0_MASK SUBBLK_CLOCK_CR_FIC0_OFFSET SUBBLK_CLOCK_CR_FIC1_MASK SUBBLK_CLOCK_CR_FIC1_OFFSET SUBBLK_CLOCK_CR_FIC2_MASK SUBBLK_CLOCK_CR_FIC2_OFFSET SUBBLK_CLOCK_CR_FIC3_MASK SUBBLK_CLOCK_CR_FIC3_OFFSET SUBBLK_CLOCK_CR_GPIO0_MASK SUBBLK_CLOCK_CR_GPIO0_OFFSET SUBBLK_CLOCK_CR_GPIO1_MASK SUBBLK_CLOCK_CR_GPIO1_OFFSET SUBBLK_CLOCK_CR_GPIO2_MASK SUBBLK_CLOCK_CR_GPIO2_OFFSET SUBBLK_CLOCK_CR_I2C0_MASK SUBBLK_CLOCK_CR_I2C0_OFFSET SUBBLK_CLOCK_CR_I2C1_MASK SUBBLK_CLOCK_CR_I2C1_OFFSET SUBBLK_CLOCK_CR_MAC0_MASK SUBBLK_CLOCK_CR_MAC0_OFFSET SUBBLK_CLOCK_CR_MAC1_MASK SUBBLK_CLOCK_CR_MAC1_OFFSET SUBBLK_CLOCK_CR_MMC_MASK SUBBLK_CLOCK_CR_MMC_OFFSET SUBBLK_CLOCK_CR_MMUART0_MASK SUBBLK_CLOCK_CR_MMUART0_OFFSET SUBBLK_CLOCK_CR_MMUART1_MASK SUBBLK_CLOCK_CR_MMUART1_OFFSET SUBBLK_CLOCK_CR_MMUART2_MASK SUBBLK_CLOCK_CR_MMUART2_OFFSET SUBBLK_CLOCK_CR_MMUART3_MASK SUBBLK_CLOCK_CR_MMUART3_OFFSET SUBBLK_CLOCK_CR_MMUART4_MASK SUBBLK_CLOCK_CR_MMUART4_OFFSET SUBBLK_CLOCK_CR_OFFSET SUBBLK_CLOCK_CR_QSPI_MASK SUBBLK_CLOCK_CR_QSPI_OFFSET SUBBLK_CLOCK_CR_RSVD_MASK SUBBLK_CLOCK_CR_RSVD_OFFSET SUBBLK_CLOCK_CR_RTC_MASK SUBBLK_CLOCK_CR_RTC_OFFSET SUBBLK_CLOCK_CR_SPI0_MASK SUBBLK_CLOCK_CR_SPI0_OFFSET SUBBLK_CLOCK_CR_SPI1_MASK SUBBLK_CLOCK_CR_SPI1_OFFSET SUBBLK_CLOCK_CR_TIMER_MASK SUBBLK_CLOCK_CR_TIMER_OFFSET SUBBLK_CLOCK_CR_USB_MASK SUBBLK_CLOCK_CR_USB_OFFSET SUBBLK_CLOCK_NA_MASK SUCCESS SUPPORTED_10baseT_Full SUPPORTED_10baseT_Half SUPPORTED_100baseT_Full SUPPORTED_100baseT_Half SUPPORTED_1000baseKX_Full SUPPORTED_1000baseT_Full SUPPORTED_1000baseT_Half SUPPORTED_2500baseX_Full SUPPORTED_10000baseKR_Full SUPPORTED_10000baseKX4_Full SUPPORTED_10000baseR_FEC SUPPORTED_10000baseT_Full SUPPORTED_AUI SUPPORTED_Asym_Pause SUPPORTED_Autoneg SUPPORTED_BNC SUPPORTED_Backplane SUPPORTED_FIBRE SUPPORTED_MII SUPPORTED_Pause SUPPORTED_TP SUSPENDM_DISABLE SUSPENDM_ENABLE SUSPEND_IRQ_MASK SWEEP_STATES__ADDR_CMD_OFFSET_SWEEP !< sweep address command SWEEP_STATES__BCLK_SCLK_OFFSET_SWEEP !< sweep bclk sclk SWEEP_STATES__DPC_VRGEN_H_SWEEP !< sweep vgen_h SWEEP_STATES__DPC_VRGEN_VS_SWEEP !< VS sweep SWEEP_STATES__DPC_VRGEN_V_SWEEP !< sweep vgen_v SWEEP_STATES__FINISHED_SWEEP !< finished sweep SWEEP_STATES__INIT_SWEEP !< start the sweep SW_CFG_NUM_READS_WRITES SW_CFG_NUM_READS_WRITES_FAST_START SW_CONFIG_PATTERN SW_CONFIG_PATTERN_FAST_START SW_FAIL_ADDR0_CR_ADDR_MASK SW_FAIL_ADDR0_CR_ADDR_OFFSET SW_FAIL_ADDR0_CR_OFFSET SW_FAIL_ADDR1_CR_ADDR_MASK SW_FAIL_ADDR1_CR_ADDR_OFFSET SW_FAIL_ADDR1_CR_FAILED_MASK SW_FAIL_ADDR1_CR_FAILED_OFFSET SW_FAIL_ADDR1_CR_ID_MASK SW_FAIL_ADDR1_CR_ID_OFFSET SW_FAIL_ADDR1_CR_OFFSET SW_FAIL_ADDR1_CR_WRITE_MASK SW_FAIL_ADDR1_CR_WRITE_OFFSET SYSREG SYSREGSCB_BASE SYSREG_ATHENACR_ALARM SYSREG_ATHENACR_BUSERROR SYSREG_ATHENACR_COMPLETE SYSREG_ATHENACR_GO SYSREG_ATHENACR_PURGE SYSREG_ATHENACR_RESET SYSREG_ATHENACR_RINGOSCON SYSREG_SOFTRESET_ATHENA SYSREG_SOFTRESET_DDRC SYSREG_SOFTRESET_ENVM SYSREG_SOFTRESET_FIC3 SYSREG_SOFTRESET_MMUART0 SYSREG_SOFTRESET_TIMER TARGET_DEVICE_ADDR_MASK TARGET_DEVICE_HUB_ADDR_MASK TARGET_DEVICE_HUB_MT_MASK TARGET_DEVICE_HUB_MT_SHIFT TARGET_DEVICE_HUB_PORT_MASK TARGET_OFFSET_HART0_M TARGET_OFFSET_HART1_M TARGET_OFFSET_HART1_S TARGET_OFFSET_HART2_M TARGET_OFFSET_HART2_S TARGET_OFFSET_HART3_M TARGET_OFFSET_HART3_S TARGET_OFFSET_HART4_M TARGET_OFFSET_HART4_S TBI TDAT TDAT_MASK TEMP0_DATA_MASK TEMP0_DATA_OFFSET TEMP0_OFFSET TEMP1_DATA_MASK TEMP1_DATA_OFFSET TEMP1_OFFSET TESTMODE_FIFOACCESS_MASK TESTMODE_FORCEFS_MASK TESTMODE_FORCEHOST_MASK TESTMODE_FORCEHS_MASK TESTMODE_SE0NAK_MASK TESTMODE_TESTJ_MASK TESTMODE_TESTK_MASK TESTMODE_TESTPACKET_MASK TEST_32BIT_ACCESS TEST_64BIT_ACCESS TIM1_ENABLE_MASK TIM1_INTEN_MASK TIM1_MODE_MASK TIM1_MODE_SHIFT TIM2_ENABLE_MASK TIM2_INTEN_MASK TIM2_MODE_MASK TIM2_MODE_SHIFT TIM64_ENABLE_MASK TIM64_INTEN_MASK TIM64_MODE_MASK TIM64_MODE_SHIFT TIMER_HI TIMER_HI_BASE TIMER_LO TIMER_LO_BASE TRAINING_MASK TRANSITION_A5_THRESHOLD TUNE_RPC_166_VALUE TWO_MBYTES TXFIFOSZ_REG_DPB_SHIFT TXINTERVAL_HOST_REG_MASK TXTYPE_HOST_TARGET_EP_NUM_MASK TXTYPE_HOST_TARGET_EP_NUM_SHIFT TXTYPE_HOST_TARGET_EP_PROTOCOL_MASK TXTYPE_HOST_TARGET_EP_PROTOCOL_SHIFT TXTYPE_HOST_TARGET_EP_SPEED_MASK TXTYPE_HOST_TARGET_EP_SPEED_SHIFT TX_EP_STALL_ERROR TX_EP_UNDER_RUN_ERROR TX_IRQ_ENABLE_REG_CEP_MASK TX_MAX_P_REG_NUM_USB_PKT_SHIFT TX_RX_CH_EN_MASK TX_RX_CH_EN_OFFSET TYPE0_HOST_MP_TARGET_SPEED_FULL TYPE0_HOST_MP_TARGET_SPEED_HIGH TYPE0_HOST_MP_TARGET_SPEED_LOW TYPE0_HOST_MP_TARGET_SPEED_MASK TYPE0_HOST_MP_TARGET_SPEED_SELF TYPE0_HOST_MP_TARGET_SPEED_SHIFT TxCSRH_HOST_EPN_DATA_TOG_MASK TxCSRH_HOST_EPN_DATA_TOG_WE_MASK TxCSRH_HOST_EPN_DMA_MODE_MASK TxCSRH_HOST_EPN_ENABLE_AUTOSET_MASK TxCSRH_HOST_EPN_ENABLE_DMA_MASK TxCSRH_HOST_EPN_FRC_DATA_TOG_MASK TxCSRH_HOST_EPN_TXRX_MODE_MASK TxCSRH_REG_EPN_DMA_MODE_MASK TxCSRH_REG_EPN_ENABLE_AUTOSET_MASK TxCSRH_REG_EPN_ENABLE_DMA_MASK TxCSRH_REG_EPN_ENABLE_ISO_MASK TxCSRH_REG_EPN_FRC_DAT_TOG_MASK TxCSRH_REG_EPN_TXRX_MODE_MASK TxCSRL_HOST_EPN_CLR_DATA_TOG_MASK TxCSRL_HOST_EPN_FLUSH_FIFO_MASK TxCSRL_HOST_EPN_NAK_TIMEOUT_MASK TxCSRL_HOST_EPN_RESPONSE_ERR_MASK TxCSRL_HOST_EPN_SETUP_PKT_MASK TxCSRL_HOST_EPN_STALL_RCVD_MASK TxCSRL_HOST_EPN_TX_FIFO_NE_MASK TxCSRL_HOST_EPN_TX_PKT_RDY_MASK TxCSRL_REG_EPN_CLR_DATA_TOG_MASK TxCSRL_REG_EPN_FLUSH_FIFO_MASK TxCSRL_REG_EPN_ISO_INCOMP_TX_MASK TxCSRL_REG_EPN_SEND_STALL_MASK TxCSRL_REG_EPN_STALL_SENT_MASK TxCSRL_REG_EPN_TX_FIFO_NE_MASK TxCSRL_REG_EPN_TX_PKT_RDY_MASK TxCSRL_REG_EPN_UNDERRUN_MASK U54_F2M_0_INT_OFFSET U54_F2M_1_INT_OFFSET U54_F2M_2_INT_OFFSET U54_F2M_3_INT_OFFSET U54_F2M_4_INT_OFFSET U54_F2M_5_INT_OFFSET U54_F2M_6_INT_OFFSET U54_F2M_7_INT_OFFSET U54_F2M_8_INT_OFFSET U54_F2M_9_INT_OFFSET U54_F2M_10_INT_OFFSET U54_F2M_11_INT_OFFSET U54_F2M_12_INT_OFFSET U54_F2M_13_INT_OFFSET U54_F2M_14_INT_OFFSET U54_F2M_15_INT_OFFSET U54_F2M_16_INT_OFFSET U54_F2M_17_INT_OFFSET U54_F2M_18_INT_OFFSET U54_F2M_19_INT_OFFSET U54_F2M_20_INT_OFFSET U54_F2M_21_INT_OFFSET U54_F2M_22_INT_OFFSET U54_F2M_23_INT_OFFSET U54_F2M_24_INT_OFFSET U54_F2M_25_INT_OFFSET U54_F2M_26_INT_OFFSET U54_F2M_27_INT_OFFSET U54_F2M_28_INT_OFFSET U54_F2M_29_INT_OFFSET U54_F2M_30_INT_OFFSET U54_F2M_31_INT_OFFSET U54_MAC0_EMAC_INT_OFFSET U54_MAC0_INT_INT_OFFSET U54_MAC0_MMSL_INT_OFFSET U54_MAC0_QUEUE1_INT_OFFSET U54_MAC0_QUEUE2_INT_OFFSET U54_MAC0_QUEUE3_INT_OFFSET U54_MAC1_EMAC_INT_OFFSET U54_MAC1_INT_INT_OFFSET U54_MAC1_MMSL_INT_OFFSET U54_MAC1_QUEUE1_INT_OFFSET U54_MAC1_QUEUE2_INT_OFFSET U54_MAC1_QUEUE3_INT_OFFSET U54_MMUARTx_INT_OFFSET U54_WDOGx_MVRP_INT_OFFSET U54_WDOGx_TOUT_INT_OFFSET UADDAR UADDAR_MASK UINT64_BYTE_LENGTH USB USBD_MSC_BOT_CBW_LENGTH USBD_MSC_BOT_CSW_LENGTH USB_BASE USB_BCD_VERSION_1_0 USB_BCD_VERSION_1_1 USB_BCD_VERSION_2_0 USB_BCD_VERSION_2_1 USB_CDC_CLEAR_COMM_FEATURE USB_CDC_GET_COMM_FEATURE USB_CDC_GET_ENCAPSULATED_RESPONSE USB_CDC_GET_LINE_CODING USB_CDC_SEND_BREAK USB_CDC_SEND_ENCAPSULATED_COMMAND USB_CDC_SET_COMM_FEATURE USB_CDC_SET_CONTROL_LINE_STATE USB_CDC_SET_LINE_CODING USB_CLASS_CODE_MSD USB_CLASS_MSD_SUBCLASS_SCSI USB_CLASS_REQUEST USB_CLAS_MSD_PROTOCOL_BOT USB_CONFIGURATION_DESCRIPTOR_TYPE USB_CR_DDR_SELECT_MASK USB_CR_DDR_SELECT_OFFSET USB_CR_LPI_CARKIT_EN_MASK USB_CR_LPI_CARKIT_EN_OFFSET USB_CR_OFFSET USB_CR_POWERDOWN_ENABLE_MASK USB_CR_POWERDOWN_ENABLE_OFFSET USB_CR_POWERDOWN_MASK USB_CR_POWERDOWN_OFFSET USB_DEFAULT_TARGET_ADDR USB_DEF_CONFIG_NUM USB_DEVICE_BUS_POWER_MASK USB_DEVICE_DESCRIPTOR_TYPE USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE USB_DEVICE_REM_WAKEUP_MASK USB_ENDPOINT_DESCRIPTOR_TYPE USB_EP_DESCR_ATTR_BULK USB_EP_DESCR_ATTR_CONTROL USB_EP_DESCR_ATTR_INTR USB_EP_DESCR_ATTR_ISO USB_FAIL USB_FS_BULK_MAX_PKT_SIZE USB_FS_HB_ISO_MAX_PKT_SIZE USB_FS_INTERRUPT_MAX_PKT_SIZE USB_FS_ISO_MAX_PKT_SIZE USB_HID_DESCRIPTOR_TYPE USB_HID_DESCR_LENGTH USB_HS_BULK_MAX_PKT_SIZE USB_HS_HB_ISO_MAX_PKT_SIZE USB_HS_INTERRUPT_MAX_PKT_SIZE USB_HS_ISO_MAX_PKT_SIZE USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE USB_INTERFACE_DESCRIPTOR_TYPE USB_INTERFACE_POWER_DESCRIPTOR_TYPE USB_MAX_BUS_POWER USB_MSC_BOT_CBW_SIGNATURE USB_MSC_BOT_CSW_SIGNATURE USB_MSC_BOT_REQ_BMS_RESET USB_MSC_BOT_REQ_GET_MAX_LUN USB_MSC_SCSI_INQUIRY USB_MSC_SCSI_INVALID_COMMAND_CODE USB_MSC_SCSI_MODE_SELECT_6 USB_MSC_SCSI_MODE_SENSE_6 USB_MSC_SCSI_PREVENT_ALLW_MDM_RMVL USB_MSC_SCSI_READ_10 USB_MSC_SCSI_READ_CAPACITY_10 USB_MSC_SCSI_READ_FORMAT_CAPACITIES USB_MSC_SCSI_REQUEST_SENSE USB_MSC_SCSI_TEST_UNIT_READY USB_MSC_SCSI_VERIFY_10 USB_MSC_SCSI_WRITE_10 USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE USB_REPORT_DESCRIPTOR_TYPE USB_SETUP_PKT_LEN USB_STANDARD_REQUEST USB_STD_CONFIG_DESCR_LEN USB_STD_DEVICE_DESCR_LEN USB_STD_DEV_QUAL_DESCR_LENGTH USB_STD_ENDPOINT_DESCR_LEN USB_STD_FEATURE_EP_HALT USB_STD_FEATURE_REMOTE_WAKEUP USB_STD_FEATURE_TEST_MODE USB_STD_IA_DESCR_LEN USB_STD_INTERFACE_DESCR_LEN USB_STD_REQ_CLEAR_FEATURE USB_STD_REQ_DATA_DIR_IN USB_STD_REQ_DATA_DIR_MASK USB_STD_REQ_DATA_DIR_OUT USB_STD_REQ_GET_CONFIG USB_STD_REQ_GET_DESCRIPTOR USB_STD_REQ_GET_INTERFACE USB_STD_REQ_GET_STATUS USB_STD_REQ_RECIPIENT_DEVICE USB_STD_REQ_RECIPIENT_ENDPOINT USB_STD_REQ_RECIPIENT_INTERFACE USB_STD_REQ_RECIPIENT_MASK USB_STD_REQ_SET_ADDRESS USB_STD_REQ_SET_CONFIG USB_STD_REQ_SET_DESCRIPTOR USB_STD_REQ_SET_FEATURE USB_STD_REQ_SET_INTERFACE USB_STD_REQ_SYNCH_FRAME USB_STD_REQ_TYPE_MASK USB_STRING_DESCRIPTOR_TYPE USB_SUCCESS USB_TEST_MODE_SELECTOR_TEST_FORCE_ENA USB_TEST_MODE_SELECTOR_TEST_J USB_TEST_MODE_SELECTOR_TEST_K USB_TEST_MODE_SELECTOR_TEST_PACKET USB_TEST_MODE_SELECTOR_TEST_SE0NAK USB_VENDOR_REQUEST USB_WINDEX_HIBITE_SHIFT USB_WVALUE_HIBITE_SHIFT USOC_SMB_INTERRUPT_E51_INT USOC_VC_INTERRUPT_E51_INT USR_STATUS_OPTION_t_USR_OPTION_tip_register_dump !< USR_OPTION_tip_register_dump VBUS_ABOVE_AVALID VBUS_ABOVE_SESSION_END VBUS_ABOVE_VBUS_VALID VBUS_BELOW_SESSION_END VBUS_ERROR_IRQ_MASK VREF_TRAINING_MAX VREF_TRAINING_MIN WAY_BYTE_LENGTH WDOG0_MVRP_E51_INT WDOG0_TOUT_E51_INT WDOG1_TOUT_E51_INT WDOG2_TOUT_E51_INT WDOG3_TOUT_E51_INT WDOG4_TOUT_E51_INT WDOGx_MVRP_U54_INT WDOGx_TOUT_U54_INT WFI_SM__CHECK_WAKE < has hart left wfi WFI_SM__CHECK_WFI < is hart in wfi? WFI_SM__INIT_THREAD_PR < 0 init pointer WFI_SM__SEND_WFI < separate state to
add a little delay WRLVL_BIT X4RDAT X4RDAT_MASK X4TDAT X4TDAT_MASK ZERO_DEVICE_BOTTOM ZERO_DEVICE_TOP __MSS_AXISW_H_ __MSS_DDRC_H_ __MSS_DDr_DEBUG_H_ __MSS_UART_H_ __bool_true_false_are_defined __cfm_channel_mode_CFM_CH_DISABLED __cfm_channel_mode_CFM_CH_FREQUENCY_MODE __cfm_channel_mode_CFM_CH_RESERVER __cfm_channel_mode_CFM_CH_TIMER_MODE __cfm_channel_mode_CFM_CH_lastmd __cfm_count_id_CFM_COUNT_0 __cfm_count_id_CFM_COUNT_1 __cfm_count_id_CFM_COUNT_2 __cfm_count_id_CFM_COUNT_3 __cfm_count_id_CFM_COUNT_4 __cfm_count_id_CFM_COUNT_5 __cfm_count_id_CFM_COUNT_6 __cfm_count_id_CFM_COUNT_7 __cfm_count_id_cfm_lastCH __cfm_error_id_t_CFM_OK __cfm_error_id_t_ERROR_CFMLAST_ID __cfm_error_id_t_ERROR_INVALID_CFM_BUSY __cfm_error_id_t_ERROR_INVALID_CHANNEL_DRIVE_CLK_MONITOR __cfm_error_id_t_ERROR_INVALID_CLK_SELECTION_GROUP __cfm_error_id_t_ERROR_INVALID_REF_SEL0 __cfm_error_id_t_ERROR_INVALID_REF_SEL1 __cfm_error_id_t_ERROR_NULL_VALUE __gpio_apb_width_t_GPIO_APB_8_BITS_BUS __gpio_apb_width_t_GPIO_APB_16_BITS_BUS __gpio_apb_width_t_GPIO_APB_32_BITS_BUS __gpio_apb_width_t_GPIO_APB_UNKNOWN_BUS_WIDTH __gpio_id_t_GPIO_0 __gpio_id_t_GPIO_1 __gpio_id_t_GPIO_2 __gpio_id_t_GPIO_3 __gpio_id_t_GPIO_4 __gpio_id_t_GPIO_5 __gpio_id_t_GPIO_6 __gpio_id_t_GPIO_7 __gpio_id_t_GPIO_8 __gpio_id_t_GPIO_9 __gpio_id_t_GPIO_10 __gpio_id_t_GPIO_11 __gpio_id_t_GPIO_12 __gpio_id_t_GPIO_13 __gpio_id_t_GPIO_14 __gpio_id_t_GPIO_15 __gpio_id_t_GPIO_16 __gpio_id_t_GPIO_17 __gpio_id_t_GPIO_18 __gpio_id_t_GPIO_19 __gpio_id_t_GPIO_20 __gpio_id_t_GPIO_21 __gpio_id_t_GPIO_22 __gpio_id_t_GPIO_23 __gpio_id_t_GPIO_24 __gpio_id_t_GPIO_25 __gpio_id_t_GPIO_26 __gpio_id_t_GPIO_27 __gpio_id_t_GPIO_28 __gpio_id_t_GPIO_29 __gpio_id_t_GPIO_30 __gpio_id_t_GPIO_31 __mss_mac_frag_size_t_MSS_MAC_FRAG_SIZE_64 __mss_mac_frag_size_t_MSS_MAC_FRAG_SIZE_128 __mss_mac_frag_size_t_MSS_MAC_FRAG_SIZE_192 __mss_mac_frag_size_t_MSS_MAC_FRAG_SIZE_256 __mss_mac_frag_size_t_MSS_MAC_FRAG_SIZE_END __mss_mac_hash_mode_t_MSS_MAC_HASH_ALL < Multicast and Unicast matching enabled __mss_mac_hash_mode_t_MSS_MAC_HASH_MULTICAST < Multicast matching enabled __mss_mac_hash_mode_t_MSS_MAC_HASH_NONE < Hash matching disabled __mss_mac_hash_mode_t_MSS_MAC_HASH_UNIICAST < Unicast matching enabled __mss_mac_oss_mode_t_MSS_MAC_OSS_MODE_ADJUST < Sync time stamp adjust correction field mode __mss_mac_oss_mode_t_MSS_MAC_OSS_MODE_DISABLED < Sync time stamp adjust disabled __mss_mac_oss_mode_t_MSS_MAC_OSS_MODE_END __mss_mac_oss_mode_t_MSS_MAC_OSS_MODE_INVALID < Only for reporting mis-configured setup, not setting thingsโฆ __mss_mac_oss_mode_t_MSS_MAC_OSS_MODE_REPLACE < Sync time stamp replace mode __mss_mac_phy_reset_t_MSS_MAC_HARD_RESET __mss_mac_phy_reset_t_MSS_MAC_SOFT_RESET __mss_mac_rx_int_ctrl_t_MSS_MAC_INT_ARM < Last buffer in chain so arm the RX interrupt __mss_mac_rx_int_ctrl_t_MSS_MAC_INT_DISABLE < Disable interrupts on exit __mss_mac_rx_int_ctrl_t_MSS_MAC_INT_ENABLE < Leave interrupts enabled on exit __mss_mac_speed_mode_t_INVALID_SPEED_MODE __mss_mac_speed_mode_t_MSS_MAC_10_FDX < Link operates in 10M full duplex mode __mss_mac_speed_mode_t_MSS_MAC_10_HDX < Link operates in 10M half duplex mode __mss_mac_speed_mode_t_MSS_MAC_100_FDX < Link operates in 100M full duplex mode __mss_mac_speed_mode_t_MSS_MAC_100_HDX < Link operates in 100M half duplex mode __mss_mac_speed_mode_t_MSS_MAC_1000_FDX < Link operates in 1000M full duplex mode __mss_mac_speed_mode_t_MSS_MAC_1000_HDX < Link operates in 1000M half duplex mode __mss_mac_speed_mode_t_MSS_MAC_SPEED_AN < Link operates in autonegotiation mode __mss_mac_speed_t_INVALID_SPEED __mss_mac_speed_t_MSS_MAC_10MBPS __mss_mac_speed_t_MSS_MAC_100MBPS __mss_mac_speed_t_MSS_MAC_1000MBPS __mss_mac_stat_t_MSS_MAC_LAST_STAT < Marker for end of valid statistics references __mss_mac_stat_t_MSS_MAC_RX_64_BYTE_FRAMES_OK < 32-bit - Count of 64 byte frames successfully received (excluding pause frames) __mss_mac_stat_t_MSS_MAC_RX_65_BYTE_FRAMES_OK < 32-bit - Count of 65 to 127 byte frames successfully received __mss_mac_stat_t_MSS_MAC_RX_128_BYTE_FRAMES_OK < 32-bit - Count of 128 to 255 byte frames successfully received __mss_mac_stat_t_MSS_MAC_RX_256_BYTE_FRAMES_OK < 32-bit - Count of 256 to 511 byte frames successfully received __mss_mac_stat_t_MSS_MAC_RX_512_BYTE_FRAMES_OK < 32-bit - Count of 512 to 1023 byte frames successfully received __mss_mac_stat_t_MSS_MAC_RX_1024_BYTE_FRAMES_OK < 32-bit - Count of 1024 to 1518 byte frames successfully received __mss_mac_stat_t_MSS_MAC_RX_1519_BYTE_FRAMES_OK < 32-bit - Count of frames longer than 1518 bytes successfully received __mss_mac_stat_t_MSS_MAC_RX_ALIGNMENT_ERRORS < 10-bit - Count of frames received with non integral byte counts __mss_mac_stat_t_MSS_MAC_RX_AUTO_FLUSHED_PACKETS < 16-bit - Count of frames flushed from receive SRAM buffers __mss_mac_stat_t_MSS_MAC_RX_BCAST_FRAMES_OK < 32-bit - Count of broadcast frames successfully received __mss_mac_stat_t_MSS_MAC_RX_FCS_ERRORS < 10-bit - Count of frames received with incorrect CRC values __mss_mac_stat_t_MSS_MAC_RX_FRAMES_OK < 32-bit - Overall count of frames successfully received __mss_mac_stat_t_MSS_MAC_RX_IP_CHECKSUM_ERRORS < 8-bit - Count of frames received with IP header checksum errors __mss_mac_stat_t_MSS_MAC_RX_JABBERS < 10-bit - Count of received jabber frames - excess length with errors __mss_mac_stat_t_MSS_MAC_RX_LENGTH_ERRORS < 10-bit - Count of frames received ok where the length received does not match the length field __mss_mac_stat_t_MSS_MAC_RX_MCAST_FRAMES_OK < 32-bit - Count of multicast cast frames successfully received __mss_mac_stat_t_MSS_MAC_RX_OCTETS_HIGH < 16-bit - MSBs of received octets count __mss_mac_stat_t_MSS_MAC_RX_OCTETS_LOW < 32-bit - LSBs of received octets count __mss_mac_stat_t_MSS_MAC_RX_OVERRUNS < 10-bit - Count of frames not copied to memory due to receive overrun __mss_mac_stat_t_MSS_MAC_RX_OVERSIZE_FRAMES_OK < 10-bit - Count of frames received over the maximum allowed length (1518, 1536 or 10240 depending on settings) __mss_mac_stat_t_MSS_MAC_RX_PAUSE_FRAMES_OK < 32-bit - Count of pause frames successfully received __mss_mac_stat_t_MSS_MAC_RX_RESOURCE_ERRORS < 18-bit - Count of times a receive buffer descriptor was read with the used bit set __mss_mac_stat_t_MSS_MAC_RX_SYMBOL_ERRORS < 10-bit - Count of frames received with symbol errors __mss_mac_stat_t_MSS_MAC_RX_TCP_CHECKSUM_ERRORS < 8-bit - Count of frames received with TCP checksum errors __mss_mac_stat_t_MSS_MAC_RX_UDP_CHECKSUM_ERRORS < 8-bit - Count of frames received with UDP checksum errors __mss_mac_stat_t_MSS_MAC_RX_UNDERSIZE_FRAMES_OK < 10-bit - Count of undersize frames received __mss_mac_stat_t_MSS_MAC_TX_64_BYTE_FRAMES_OK < 32-bit - Count of 64 byte frames successfully transmitted (excluding pause frames) __mss_mac_stat_t_MSS_MAC_TX_65_BYTE_FRAMES_OK < 32-bit - Count of 65 to 127 byte frames successfully transmitted __mss_mac_stat_t_MSS_MAC_TX_128_BYTE_FRAMES_OK < 32-bit - Count of 128 to 255 byte frames successfully transmitted __mss_mac_stat_t_MSS_MAC_TX_256_BYTE_FRAMES_OK < 32-bit - Count of 256 to 511 byte frames successfully transmitted __mss_mac_stat_t_MSS_MAC_TX_512_BYTE_FRAMES_OK < 32-bit - Count of 512 to 1023 byte frames successfully transmitted __mss_mac_stat_t_MSS_MAC_TX_1024_BYTE_FRAMES_OK < 32-bit - Count of 1024 to 1518 byte frames successfully transmitted __mss_mac_stat_t_MSS_MAC_TX_1519_BYTE_FRAMES_OK < 32-bit - Count of frames longer than 1518 bytes successfully transmitted __mss_mac_stat_t_MSS_MAC_TX_BCAST_FRAMES_OK < 32-bit - Count of broadcast frames successfully transmitted __mss_mac_stat_t_MSS_MAC_TX_CRS_ERRORS < 10-bit - Count of Carrier Sense Errors __mss_mac_stat_t_MSS_MAC_TX_DEFERRED_FRAMES < 18-bit - Count of frames deferred due to carrier sense being active __mss_mac_stat_t_MSS_MAC_TX_EXCESSIVE_COLLISIONS < 10-bit - Count of frames discarded because 16 collisions occurred __mss_mac_stat_t_MSS_MAC_TX_FRAMES_OK < 32-bit - Overall count of frames successfully transmitted __mss_mac_stat_t_MSS_MAC_TX_LATE_COLLISIONS < 10-bit - Count of collisions detected after the 512 bit slot time __mss_mac_stat_t_MSS_MAC_TX_MCAST_FRAMES_OK < 32-bit - Count of multicast frames successfully transmitted __mss_mac_stat_t_MSS_MAC_TX_MULTIPLE_COLLISIONS < 18-bit - Count of 2 to 15 collision burst events __mss_mac_stat_t_MSS_MAC_TX_OCTETS_HIGH < 16-bit - MSBs of transmitted octets count __mss_mac_stat_t_MSS_MAC_TX_OCTETS_LOW < 32-bit - LSBs of transmitted octets count __mss_mac_stat_t_MSS_MAC_TX_PAUSE_FRAMES_OK < 32-bit - Count of pause successfully transmitted __mss_mac_stat_t_MSS_MAC_TX_SINGLE_COLLISIONS < 18-bit - Count of single collision transmit events __mss_mac_stat_t_MSS_MAC_TX_UNDERRUNS < 10-bit - Count of frames not transmitted due to under runs __mss_mac_tsu_addr_t_MSS_MAC_TSU_UNICAST_RX __mss_mac_tsu_addr_t_MSS_MAC_TSU_UNICAST_TX __mss_mac_tsu_mode_t_MSS_MAC_TSU_MODE_ALL < Time stamp insertion for all frames __mss_mac_tsu_mode_t_MSS_MAC_TSU_MODE_DISABLED < Time stamp insertion disabled __mss_mac_tsu_mode_t_MSS_MAC_TSU_MODE_END __mss_mac_tsu_mode_t_MSS_MAC_TSU_MODE_PTP_ALL < Time stamp insertion all PTP frames __mss_mac_tsu_mode_t_MSS_MAC_TSU_MODE_PTP_EVENT < Time stamp insertion for PTP Event frames only __mss_timer_mode_MSS_TIMER_ONE_SHOT_MODE !< MSS_TIMER_ONE_SHOT_MODE __mss_timer_mode_MSS_TIMER_PERIODIC_MODE !< MSS_TIMER_PERIODIC_MODE __pdma_channel_id_MSS_PDMA_CHANNEL_0 __pdma_channel_id_MSS_PDMA_CHANNEL_1 __pdma_channel_id_MSS_PDMA_CHANNEL_2 __pdma_channel_id_MSS_PDMA_CHANNEL_3 __pdma_channel_id_MSS_PDMA_lAST_CHANNEL __pdma_error_id_t_MSS_PDMA_ERROR_INVALID_CHANNEL_ID !< ERROR_INVALID_CHANNEL_ID __pdma_error_id_t_MSS_PDMA_ERROR_INVALID_DEST_ADDR !< ERROR_INVALID_DEST_ADDR __pdma_error_id_t_MSS_PDMA_ERROR_INVALID_NEXTCFG_RSIZE !< ERROR_INVALID_NEXTCFG_RSIZE __pdma_error_id_t_MSS_PDMA_ERROR_INVALID_NEXTCFG_WSIZE !< ERROR_INVALID_NEXTCFG_WSIZE __pdma_error_id_t_MSS_PDMA_ERROR_INVALID_SRC_ADDR !< ERROR_INVALID_SRC_ADDR __pdma_error_id_t_MSS_PDMA_ERROR_LAST_ID !< ERROR_LAST_ID __pdma_error_id_t_MSS_PDMA_ERROR_TRANSACTION_IN_PROGRESS !< ERROR_TRANSACTION_IN_PROGRESS __pdma_error_id_t_MSS_PDMA_OK !< PDMA_OK false_ gpio_inout_state_GPIO_DRIVE_HIGH gpio_inout_state_GPIO_DRIVE_LOW gpio_inout_state_GPIO_HIGH_Z mss_axisw_cmd_t_MSS_AXISW_BURSTINESS_EN mss_axisw_cmd_t_MSS_AXISW_PEAKRT_XCTRT mss_axisw_cmd_t_MSS_AXISW_QOS_VAL mss_axisw_cmd_t_MSS_AXISW_SLV_RDY mss_axisw_mchan_t_MSS_AXISW_MASTER_RD_CHAN mss_axisw_mchan_t_MSS_AXISW_MASTER_WR_CHAN mss_axisw_mport_t_MSS_AXISW_ATHENA_RD_CHAN mss_axisw_mport_t_MSS_AXISW_ATHENA_WR_CHAN mss_axisw_mport_t_MSS_AXISW_CPLEX_D0_RD_CHAN mss_axisw_mport_t_MSS_AXISW_CPLEX_D0_WR_CHAN mss_axisw_mport_t_MSS_AXISW_CPLEX_D1_RD_CHAN mss_axisw_mport_t_MSS_AXISW_CPLEX_D1_WR_CHAN mss_axisw_mport_t_MSS_AXISW_CPLEX_F0_RD_CHAN mss_axisw_mport_t_MSS_AXISW_CPLEX_F0_WR_CHAN mss_axisw_mport_t_MSS_AXISW_CPLEX_F1_RD_CHAN mss_axisw_mport_t_MSS_AXISW_CPLEX_F1_WR_CHAN mss_axisw_mport_t_MSS_AXISW_CPLEX_NC_RD_CHAN mss_axisw_mport_t_MSS_AXISW_CPLEX_NC_WR_CHAN mss_axisw_mport_t_MSS_AXISW_FIC0_RD_CHAN mss_axisw_mport_t_MSS_AXISW_FIC0_WR_CHAN mss_axisw_mport_t_MSS_AXISW_FIC1_RD_CHAN mss_axisw_mport_t_MSS_AXISW_FIC1_WR_CHAN mss_axisw_mport_t_MSS_AXISW_FIC2_RD_CHAN mss_axisw_mport_t_MSS_AXISW_FIC2_WR_CHAN mss_axisw_mport_t_MSS_AXISW_GEM0_RD_CHAN mss_axisw_mport_t_MSS_AXISW_GEM0_WR_CHAN mss_axisw_mport_t_MSS_AXISW_GEM1_RD_CHAN mss_axisw_mport_t_MSS_AXISW_GEM1_WR_CHAN mss_axisw_mport_t_MSS_AXISW_MMC_RD_CHAN mss_axisw_mport_t_MSS_AXISW_MMC_WR_CHAN mss_axisw_mport_t_MSS_AXISW_SCB_RD_CHAN mss_axisw_mport_t_MSS_AXISW_SCB_WR_CHAN mss_axisw_mport_t_MSS_AXISW_TRACE_RD_CHAN mss_axisw_mport_t_MSS_AXISW_TRACE_WR_CHAN mss_axisw_mport_t_MSS_AXISW_USB_RD_CHAN mss_axisw_mport_t_MSS_AXISW_USB_WR_CHAN mss_axisw_rate_t_MSS_AXISW_TXNRATE_BY2 mss_axisw_rate_t_MSS_AXISW_TXNRATE_BY4 mss_axisw_rate_t_MSS_AXISW_TXNRATE_BY8 mss_axisw_rate_t_MSS_AXISW_TXNRATE_BY16 mss_axisw_rate_t_MSS_AXISW_TXNRATE_BY32 mss_axisw_rate_t_MSS_AXISW_TXNRATE_BY64 mss_axisw_rate_t_MSS_AXISW_TXNRATE_BY128 mss_axisw_rate_t_MSS_AXISW_TXNRATE_BY256 mss_axisw_rate_t_MSS_AXISW_TXNRATE_BY512 mss_axisw_rate_t_MSS_AXISW_TXNRATE_BY1024 mss_axisw_rate_t_MSS_AXISW_TXNRATE_BY2098 mss_axisw_rate_t_MSS_AXISW_TXNRATE_BY4096 mss_axisw_rate_t_MSS_AXISW_TXNRATE_DISABLE mss_can_mode_CANOP_MODE_EXT_LOOPBACK mss_can_mode_CANOP_MODE_INT_LOOPBACK mss_can_mode_CANOP_MODE_LISTEN_ONLY mss_can_mode_CANOP_MODE_NORMAL mss_can_mode_CANOP_SRAM_TEST_MODE mss_can_mode_CANOP_SW_RESET mss_gpio_byte_num_MSS_GPIO_BYTE_0 mss_gpio_byte_num_MSS_GPIO_BYTE_1 mss_gpio_byte_num_MSS_GPIO_BYTE_2 mss_gpio_byte_num_MSS_GPIO_BYTE_3 mss_gpio_byte_num_MSS_GPIO_BYTE_INVALID mss_gpio_id_MSS_GPIO_0 mss_gpio_id_MSS_GPIO_1 mss_gpio_id_MSS_GPIO_2 mss_gpio_id_MSS_GPIO_3 mss_gpio_id_MSS_GPIO_4 mss_gpio_id_MSS_GPIO_5 mss_gpio_id_MSS_GPIO_6 mss_gpio_id_MSS_GPIO_7 mss_gpio_id_MSS_GPIO_8 mss_gpio_id_MSS_GPIO_9 mss_gpio_id_MSS_GPIO_10 mss_gpio_id_MSS_GPIO_11 mss_gpio_id_MSS_GPIO_12 mss_gpio_id_MSS_GPIO_13 mss_gpio_id_MSS_GPIO_14 mss_gpio_id_MSS_GPIO_15 mss_gpio_id_MSS_GPIO_16 mss_gpio_id_MSS_GPIO_17 mss_gpio_id_MSS_GPIO_18 mss_gpio_id_MSS_GPIO_19 mss_gpio_id_MSS_GPIO_20 mss_gpio_id_MSS_GPIO_21 mss_gpio_id_MSS_GPIO_22 mss_gpio_id_MSS_GPIO_23 mss_gpio_id_MSS_GPIO_24 mss_gpio_id_MSS_GPIO_25 mss_gpio_id_MSS_GPIO_26 mss_gpio_id_MSS_GPIO_27 mss_gpio_id_MSS_GPIO_28 mss_gpio_id_MSS_GPIO_29 mss_gpio_id_MSS_GPIO_30 mss_gpio_id_MSS_GPIO_31 mss_gpio_inout_state_MSS_GPIO_DRIVE_HIGH mss_gpio_inout_state_MSS_GPIO_DRIVE_LOW mss_gpio_inout_state_MSS_GPIO_HIGH_Z mss_i2c_clock_divider_MSS_I2C_BCLK_DIV_8 mss_i2c_clock_divider_MSS_I2C_PCLK_DIV_60 mss_i2c_clock_divider_MSS_I2C_PCLK_DIV_120 mss_i2c_clock_divider_MSS_I2C_PCLK_DIV_160 mss_i2c_clock_divider_MSS_I2C_PCLK_DIV_192 mss_i2c_clock_divider_MSS_I2C_PCLK_DIV_224 mss_i2c_clock_divider_MSS_I2C_PCLK_DIV_256 mss_i2c_clock_divider_MSS_I2C_PCLK_DIV_960 mss_i2c_slave_handler_ret_MSS_I2C_PAUSE_SLAVE_RX mss_i2c_slave_handler_ret_MSS_I2C_REENABLE_SLAVE_RX mss_i2c_status_MSS_I2C_FAILED mss_i2c_status_MSS_I2C_IN_PROGRESS mss_i2c_status_MSS_I2C_SUCCESS mss_i2c_status_MSS_I2C_TIMED_OUT mss_mmc_status_MSS_MMC_BASE_CLK_IS_ZERO_ERR mss_mmc_status_MSS_MMC_CARD_INSERTED_ERR mss_mmc_status_MSS_MMC_CARD_SELECT_ERROR mss_mmc_status_MSS_MMC_CARD_SELECT_SUCCESS mss_mmc_status_MSS_MMC_CARD_STATE_STABLE_ERR mss_mmc_status_MSS_MMC_CID_RESP_ERR mss_mmc_status_MSS_MMC_CLK_DIV_ERR mss_mmc_status_MSS_MMC_CQ_INIT_FAILURE mss_mmc_status_MSS_MMC_CQ_NOT_INITIALISED mss_mmc_status_MSS_MMC_CRC_ERR mss_mmc_status_MSS_MMC_DATA_SIZE_IS_NOT_MULTI_BLOCK mss_mmc_status_MSS_MMC_DEVICE_ERROR mss_mmc_status_MSS_MMC_DEVICE_HPI_NOT_DISABLED mss_mmc_status_MSS_MMC_DEVICE_IS_NOT_IN_HPI_MODE mss_mmc_status_MSS_MMC_DEVICE_NOT_SUPPORT_CQ mss_mmc_status_MSS_MMC_DEVICE_NOT_SUPPORT_DDR mss_mmc_status_MSS_MMC_DEVICE_NOT_SUPPORT_HPI mss_mmc_status_MSS_MMC_DEVICE_NOT_SUPPORT_HS200 mss_mmc_status_MSS_MMC_DEVICE_NOT_SUPPORT_HS400 mss_mmc_status_MSS_MMC_DEVICE_NOT_SUPPORT_LOW_POWER mss_mmc_status_MSS_MMC_DEVICE_NOT_SUPPORT_SDR mss_mmc_status_MSS_MMC_DWIDTH_ERR mss_mmc_status_MSS_MMC_ERR_INTERRUPT mss_mmc_status_MSS_MMC_ERR_SWITCH_VOLTAGE_FAILED mss_mmc_status_MSS_MMC_HS400_MODE_SETUP_FAILURE mss_mmc_status_MSS_MMC_INIT_FAILURE mss_mmc_status_MSS_MMC_INIT_SUCCESS mss_mmc_status_MSS_MMC_INVALID_PARAMETER mss_mmc_status_MSS_MMC_MODE_NOT_SUPPORT_DATAWIDTH mss_mmc_status_MSS_MMC_NOT_INITIALISED mss_mmc_status_MSS_MMC_NO_ERROR mss_mmc_status_MSS_MMC_OP_COND_ERR mss_mmc_status_MSS_MMC_RCA_ERROR mss_mmc_status_MSS_MMC_RESET_ERR mss_mmc_status_MSS_MMC_RESPONSE_ERROR mss_mmc_status_MSS_MMC_SDCARD_CMD6_SWITCH_ERROR mss_mmc_status_MSS_MMC_SDCARD_NOT_SUPPORT_BUS_MODE mss_mmc_status_MSS_MMC_SDCARD_NOT_SUPPORT_SPEED mss_mmc_status_MSS_MMC_SDCARD_NOT_SUPPORT_VOLTAGE mss_mmc_status_MSS_MMC_SDCARD_TUNING_FAILED mss_mmc_status_MSS_MMC_SDIO_ERR_BUS_SPEED_UNSUPP mss_mmc_status_MSS_MMC_TRANSFER_FAIL mss_mmc_status_MSS_MMC_TRANSFER_IN_PROGRESS mss_mmc_status_MSS_MMC_TRANSFER_SUCCESS mss_mmc_status_MSS_MMC_UNSUPPORTED_HW_REVISION mss_mpu_addrm_t_MSS_MPU_AM_NAPOT mss_mpu_addrm_t_MSS_MPU_AM_OFF mss_mpu_mport_t_MSS_MPU_CRYPTO mss_mpu_mport_t_MSS_MPU_FIC0 mss_mpu_mport_t_MSS_MPU_FIC1 mss_mpu_mport_t_MSS_MPU_FIC2 mss_mpu_mport_t_MSS_MPU_GEM0 mss_mpu_mport_t_MSS_MPU_GEM1 mss_mpu_mport_t_MSS_MPU_MMC mss_mpu_mport_t_MSS_MPU_SCB mss_mpu_mport_t_MSS_MPU_SEG0 mss_mpu_mport_t_MSS_MPU_SEG1 mss_mpu_mport_t_MSS_MPU_TRACE mss_mpu_mport_t_MSS_MPU_USB mss_mpu_pmp_region_t_MSS_MPU_PMP_REGION0 mss_mpu_pmp_region_t_MSS_MPU_PMP_REGION1 mss_mpu_pmp_region_t_MSS_MPU_PMP_REGION2 mss_mpu_pmp_region_t_MSS_MPU_PMP_REGION3 mss_mpu_pmp_region_t_MSS_MPU_PMP_REGION4 mss_mpu_pmp_region_t_MSS_MPU_PMP_REGION5 mss_mpu_pmp_region_t_MSS_MPU_PMP_REGION6 mss_mpu_pmp_region_t_MSS_MPU_PMP_REGION7 mss_mpu_pmp_region_t_MSS_MPU_PMP_REGION8 mss_mpu_pmp_region_t_MSS_MPU_PMP_REGION9 mss_mpu_pmp_region_t_MSS_MPU_PMP_REGION10 mss_mpu_pmp_region_t_MSS_MPU_PMP_REGION11 mss_mpu_pmp_region_t_MSS_MPU_PMP_REGION12 mss_mpu_pmp_region_t_MSS_MPU_PMP_REGION13 mss_mpu_pmp_region_t_MSS_MPU_PMP_REGION14 mss_mpu_pmp_region_t_MSS_MPU_PMP_REGION15 mss_peripherals__MSS_PERIPH_ATHENA mss_peripherals__MSS_PERIPH_CAN0 mss_peripherals__MSS_PERIPH_CAN1 mss_peripherals__MSS_PERIPH_CFM mss_peripherals__MSS_PERIPH_CRYPTO mss_peripherals__MSS_PERIPH_EMMC mss_peripherals__MSS_PERIPH_FIC0 mss_peripherals__MSS_PERIPH_FIC1 mss_peripherals__MSS_PERIPH_FIC2 mss_peripherals__MSS_PERIPH_FIC3 mss_peripherals__MSS_PERIPH_GPIO0 mss_peripherals__MSS_PERIPH_GPIO1 mss_peripherals__MSS_PERIPH_GPIO2 mss_peripherals__MSS_PERIPH_I2C0 mss_peripherals__MSS_PERIPH_I2C1 mss_peripherals__MSS_PERIPH_INVALID mss_peripherals__MSS_PERIPH_M2FINT mss_peripherals__MSS_PERIPH_MAC0 mss_peripherals__MSS_PERIPH_MAC1 mss_peripherals__MSS_PERIPH_MAILBOX_SC mss_peripherals__MSS_PERIPH_MMUART0 mss_peripherals__MSS_PERIPH_MMUART1 mss_peripherals__MSS_PERIPH_MMUART2 mss_peripherals__MSS_PERIPH_MMUART3 mss_peripherals__MSS_PERIPH_MMUART4 mss_peripherals__MSS_PERIPH_QSPIXIP mss_peripherals__MSS_PERIPH_RTC mss_peripherals__MSS_PERIPH_SPI0 mss_peripherals__MSS_PERIPH_SPI1 mss_peripherals__MSS_PERIPH_TIMER mss_peripherals__MSS_PERIPH_TRACE mss_peripherals__MSS_PERIPH_USB mss_peripherals__MSS_PERIPH_WDOG0 mss_peripherals__MSS_PERIPH_WDOG1 mss_peripherals__MSS_PERIPH_WDOG2 mss_peripherals__MSS_PERIPH_WDOG3 mss_peripherals__MSS_PERIPH_WDOG4 mss_qspi_clk_div_t_MSS_QSPI_CLK_DIV_2 mss_qspi_clk_div_t_MSS_QSPI_CLK_DIV_4 mss_qspi_clk_div_t_MSS_QSPI_CLK_DIV_6 mss_qspi_clk_div_t_MSS_QSPI_CLK_DIV_8 mss_qspi_clk_div_t_MSS_QSPI_CLK_DIV_10 mss_qspi_clk_div_t_MSS_QSPI_CLK_DIV_12 mss_qspi_clk_div_t_MSS_QSPI_CLK_DIV_14 mss_qspi_clk_div_t_MSS_QSPI_CLK_DIV_16 mss_qspi_clk_div_t_MSS_QSPI_CLK_DIV_18 mss_qspi_clk_div_t_MSS_QSPI_CLK_DIV_20 mss_qspi_clk_div_t_MSS_QSPI_CLK_DIV_22 mss_qspi_clk_div_t_MSS_QSPI_CLK_DIV_24 mss_qspi_clk_div_t_MSS_QSPI_CLK_DIV_26 mss_qspi_clk_div_t_MSS_QSPI_CLK_DIV_28 mss_qspi_clk_div_t_MSS_QSPI_CLK_DIV_30 mss_qspi_io_format_t_MSS_QSPI_DUAL_EX_RO mss_qspi_io_format_t_MSS_QSPI_DUAL_EX_RW mss_qspi_io_format_t_MSS_QSPI_DUAL_FULL mss_qspi_io_format_t_MSS_QSPI_NORMAL mss_qspi_io_format_t_MSS_QSPI_QUAD_EX_RO mss_qspi_io_format_t_MSS_QSPI_QUAD_EX_RW mss_qspi_io_format_t_MSS_QSPI_QUAD_FULL mss_qspi_protocol_mode_t_MSS_QSPI_MODE0 mss_qspi_protocol_mode_t_MSS_QSPI_MODE3 mss_uart_endian_t_MSS_UART_BIGEND mss_uart_endian_t_MSS_UART_INVALID_ENDIAN mss_uart_endian_t_MSS_UART_LITTLEEND mss_uart_filter_length_t_MSS_UART_INVALID_FILTER_LENGTH mss_uart_filter_length_t_MSS_UART_LEN0 mss_uart_filter_length_t_MSS_UART_LEN1 mss_uart_filter_length_t_MSS_UART_LEN2 mss_uart_filter_length_t_MSS_UART_LEN3 mss_uart_filter_length_t_MSS_UART_LEN4 mss_uart_filter_length_t_MSS_UART_LEN5 mss_uart_filter_length_t_MSS_UART_LEN6 mss_uart_filter_length_t_MSS_UART_LEN7 mss_uart_loopback_t_MSS_UART_AUTO_ECHO_OFF mss_uart_loopback_t_MSS_UART_AUTO_ECHO_ON mss_uart_loopback_t_MSS_UART_INVALID_LOOPBACK mss_uart_loopback_t_MSS_UART_LOCAL_LOOPBACK_OFF mss_uart_loopback_t_MSS_UART_LOCAL_LOOPBACK_ON mss_uart_loopback_t_MSS_UART_REMOTE_LOOPBACK_OFF mss_uart_loopback_t_MSS_UART_REMOTE_LOOPBACK_ON mss_uart_num_t_MSS_UAR4_HI mss_uart_num_t_MSS_UART0_HI mss_uart_num_t_MSS_UART0_LO mss_uart_num_t_MSS_UART1_HI mss_uart_num_t_MSS_UART1_LO mss_uart_num_t_MSS_UART2_HI mss_uart_num_t_MSS_UART2_LO mss_uart_num_t_MSS_UART3_HI mss_uart_num_t_MSS_UART3_LO mss_uart_num_t_MSS_UART4_LO mss_uart_ready_mode_t_MSS_UART_INVALID_READY_MODE mss_uart_ready_mode_t_MSS_UART_READY_MODE0 mss_uart_ready_mode_t_MSS_UART_READY_MODE1 mss_uart_rx_trig_level_t_MSS_UART_FIFO_EIGHT_BYTES mss_uart_rx_trig_level_t_MSS_UART_FIFO_FOURTEEN_BYTES mss_uart_rx_trig_level_t_MSS_UART_FIFO_FOUR_BYTES mss_uart_rx_trig_level_t_MSS_UART_FIFO_INVALID_TRIG_LEVEL mss_uart_rx_trig_level_t_MSS_UART_FIFO_SINGLE_BYTE mss_uart_rzi_polarity_t_MSS_UART_ACTIVE_HIGH mss_uart_rzi_polarity_t_MSS_UART_ACTIVE_LOW mss_uart_rzi_polarity_t_MSS_UART_INVALID_POLARITY mss_uart_rzi_pulsewidth_t_MSS_UART_1_BY_4 mss_uart_rzi_pulsewidth_t_MSS_UART_3_BY_16 mss_uart_rzi_pulsewidth_t_MSS_UART_INVALID_PW mss_uart_usart_mode_t_MSS_UART_ASYNC_MODE mss_uart_usart_mode_t_MSS_UART_INVALID_SYNC_MODE mss_uart_usart_mode_t_MSS_UART_SYNC_MASTER_NEG_EDGE_CLK mss_uart_usart_mode_t_MSS_UART_SYNC_MASTER_POS_EDGE_CLK mss_uart_usart_mode_t_MSS_UART_SYNC_SLAVE_NEG_EDGE_CLK mss_uart_usart_mode_t_MSS_UART_SYNC_SLAVE_POS_EDGE_CLK mss_usb_core_mode_t_MSS_USB_CORE_MODE_DEVICE mss_usb_core_mode_t_MSS_USB_CORE_MODE_HOST mss_usb_device_role_MSS_USB_DEVICE_ROLE_DEVICE_A mss_usb_device_role_MSS_USB_DEVICE_ROLE_DEVICE_B mss_usb_device_speed_t_MSS_USB_DEVICE_FS mss_usb_device_speed_t_MSS_USB_DEVICE_HS mss_usb_device_speed_t_MSS_USB_DEVICE_LS mss_usb_dma_burst_mode_t_MSS_USB_DMA_BURST_MODE0 mss_usb_dma_burst_mode_t_MSS_USB_DMA_BURST_MODE1 mss_usb_dma_burst_mode_t_MSS_USB_DMA_BURST_MODE2 mss_usb_dma_burst_mode_t_MSS_USB_DMA_BURST_MODE3 mss_usb_dma_channel_t_MSS_USB_DMA_CHANNEL1 mss_usb_dma_channel_t_MSS_USB_DMA_CHANNEL2 mss_usb_dma_channel_t_MSS_USB_DMA_CHANNEL3 mss_usb_dma_channel_t_MSS_USB_DMA_CHANNEL4 mss_usb_dma_channel_t_MSS_USB_DMA_CHANNEL_NA mss_usb_dma_dir_t_MSS_USB_DMA_READ mss_usb_dma_dir_t_MSS_USB_DMA_WRITE mss_usb_dma_mode_t_MSS_USB_DMA_MODE0 mss_usb_dma_mode_t_MSS_USB_DMA_MODE1 mss_usb_ep_num_t_MSS_USB_CEP mss_usb_ep_num_t_MSS_USB_RX_EP_1 mss_usb_ep_num_t_MSS_USB_RX_EP_2 mss_usb_ep_num_t_MSS_USB_RX_EP_3 mss_usb_ep_num_t_MSS_USB_RX_EP_4 mss_usb_ep_num_t_MSS_USB_TX_EP_1 mss_usb_ep_num_t_MSS_USB_TX_EP_2 mss_usb_ep_num_t_MSS_USB_TX_EP_3 mss_usb_ep_num_t_MSS_USB_TX_EP_4 mss_usb_ep_state_t_MSS_USB_CEP_IDLE mss_usb_ep_state_t_MSS_USB_CEP_RX mss_usb_ep_state_t_MSS_USB_CEP_SETUP mss_usb_ep_state_t_MSS_USB_CEP_STATUS_AFTER_IN mss_usb_ep_state_t_MSS_USB_CEP_STATUS_AFTER_OUT mss_usb_ep_state_t_MSS_USB_CEP_TX mss_usb_ep_state_t_MSS_USB_EP_ABORTED mss_usb_ep_state_t_MSS_USB_EP_NAK mss_usb_ep_state_t_MSS_USB_EP_NAK_TOUT mss_usb_ep_state_t_MSS_USB_EP_NO_RESPONSE mss_usb_ep_state_t_MSS_USB_EP_NYET mss_usb_ep_state_t_MSS_USB_EP_STALLED mss_usb_ep_state_t_MSS_USB_EP_STALL_RCVD mss_usb_ep_state_t_MSS_USB_EP_TXN_SUCCESS mss_usb_ep_state_t_MSS_USB_EP_VALID mss_usb_ep_state_t_MSS_USB_EP_XFR_SUCCESS mss_usb_pkt_type_MSS_USB_IN_DATA_PKT mss_usb_pkt_type_MSS_USB_OUT_DATA_PKT mss_usb_pkt_type_MSS_USB_SETUP_PKT mss_usb_pkt_type_MSS_USB_STATUS_PKT_AFTER_IN mss_usb_pkt_type_MSS_USB_STATUS_PKT_AFTER_OUT mss_usb_state_t_MSS_USB_ADDRESS_STATE mss_usb_state_t_MSS_USB_ATTACHED_STATE mss_usb_state_t_MSS_USB_CONFIGURED_STATE mss_usb_state_t_MSS_USB_DEFAULT_STATE mss_usb_state_t_MSS_USB_NOT_ATTACHED_STATE mss_usb_state_t_MSS_USB_POWERED_STATE mss_usb_state_t_MSS_USB_SUSPENDED_STATE mss_usb_vbus_level_t_VBUS_ABV_AVALID_BLOW_VB_VALID mss_usb_vbus_level_t_VBUS_ABV_SESSIONEND_BLOW_AVALID mss_usb_vbus_level_t_VBUS_ABV_VB_VALID mss_usb_vbus_level_t_VBUS_BLOW_SESSIONEND mss_usb_xfr_type_t_MSS_USB_XFR_BULK mss_usb_xfr_type_t_MSS_USB_XFR_CONTROL mss_usb_xfr_type_t_MSS_USB_XFR_HB_INTERRUPT mss_usb_xfr_type_t_MSS_USB_XFR_HB_ISO mss_usb_xfr_type_t_MSS_USB_XFR_INTERRUPT mss_usb_xfr_type_t_MSS_USB_XFR_ISO mss_usbd_cep_state_t_MSS_USB_CTRL_EP_IDLE mss_usbd_cep_state_t_MSS_USB_CTRL_EP_RX mss_usbd_cep_state_t_MSS_USB_CTRL_EP_TX mss_watchdog_num_MSS_WDOG0_HI mss_watchdog_num_MSS_WDOG0_LO mss_watchdog_num_MSS_WDOG1_HI mss_watchdog_num_MSS_WDOG1_LO mss_watchdog_num_MSS_WDOG2_HI mss_watchdog_num_MSS_WDOG2_LO mss_watchdog_num_MSS_WDOG3_HI mss_watchdog_num_MSS_WDOG3_LO mss_watchdog_num_MSS_WDOG4_HI mss_watchdog_num_MSS_WDOG4_LO pf_pcie_atr_size_t_PF_PCIE_SIZE_1GB pf_pcie_atr_size_t_PF_PCIE_SIZE_1MB pf_pcie_atr_size_t_PF_PCIE_SIZE_1TB pf_pcie_atr_size_t_PF_PCIE_SIZE_2GB pf_pcie_atr_size_t_PF_PCIE_SIZE_2MB pf_pcie_atr_size_t_PF_PCIE_SIZE_2TB pf_pcie_atr_size_t_PF_PCIE_SIZE_4GB pf_pcie_atr_size_t_PF_PCIE_SIZE_4KB pf_pcie_atr_size_t_PF_PCIE_SIZE_4MB pf_pcie_atr_size_t_PF_PCIE_SIZE_4TB pf_pcie_atr_size_t_PF_PCIE_SIZE_8GB pf_pcie_atr_size_t_PF_PCIE_SIZE_8KB pf_pcie_atr_size_t_PF_PCIE_SIZE_8MB pf_pcie_atr_size_t_PF_PCIE_SIZE_8TB pf_pcie_atr_size_t_PF_PCIE_SIZE_16GB pf_pcie_atr_size_t_PF_PCIE_SIZE_16KB pf_pcie_atr_size_t_PF_PCIE_SIZE_16MB pf_pcie_atr_size_t_PF_PCIE_SIZE_16TB pf_pcie_atr_size_t_PF_PCIE_SIZE_32GB pf_pcie_atr_size_t_PF_PCIE_SIZE_32KB pf_pcie_atr_size_t_PF_PCIE_SIZE_32MB pf_pcie_atr_size_t_PF_PCIE_SIZE_32TB pf_pcie_atr_size_t_PF_PCIE_SIZE_64GB pf_pcie_atr_size_t_PF_PCIE_SIZE_64KB pf_pcie_atr_size_t_PF_PCIE_SIZE_64MB pf_pcie_atr_size_t_PF_PCIE_SIZE_64TB pf_pcie_atr_size_t_PF_PCIE_SIZE_128GB pf_pcie_atr_size_t_PF_PCIE_SIZE_128KB pf_pcie_atr_size_t_PF_PCIE_SIZE_128MB pf_pcie_atr_size_t_PF_PCIE_SIZE_128TB pf_pcie_atr_size_t_PF_PCIE_SIZE_256GB pf_pcie_atr_size_t_PF_PCIE_SIZE_256KB pf_pcie_atr_size_t_PF_PCIE_SIZE_256MB pf_pcie_atr_size_t_PF_PCIE_SIZE_256TB pf_pcie_atr_size_t_PF_PCIE_SIZE_512GB pf_pcie_atr_size_t_PF_PCIE_SIZE_512KB pf_pcie_atr_size_t_PF_PCIE_SIZE_512MB pf_pcie_atr_size_t_PF_PCIE_SIZE_512TB pf_pcie_bar_type_t_PF_PCIE_BAR_TYPE_32BIT_MEM pf_pcie_bar_type_t_PF_PCIE_BAR_TYPE_32BIT_PREFET_MEM pf_pcie_bar_type_t_PF_PCIE_BAR_TYPE_64BIT_PREFET_MEM pf_pcie_ep_dma_status_t_PF_PCIE_EP_DMA_COMPLETED pf_pcie_ep_dma_status_t_PF_PCIE_EP_DMA_ERROR pf_pcie_ep_dma_status_t_PF_PCIE_EP_DMA_IN_PROGRESS pf_pcie_ep_dma_status_t_PF_PCIE_EP_DMA_NOT_INITIALIZED pf_pcie_tlp_type_t_PF_PCIE_TLP_IO pf_pcie_tlp_type_t_PF_PCIE_TLP_MEM pf_pcie_tlp_type_t_PF_PCIE_TLP_MEM_LOCKED pf_pcie_tlp_type_t_PF_PCIE_TLP_MEM_TRSNL_REQUEST pf_pcie_tlp_type_t_PF_PCIE_TLP_MESSAGE pf_pcie_tlp_type_t_PF_PCIE_TLP_TRSNL_REQUEST scb_INTERRUPT_E51_INT true_ CFG_DDR_SGMII_PHY โ DDRCFG โ IOSCB_IO_CALIB_DDR โ IOSCB_IO_CALIB_SGMII โ MSS_SCB_CFM_MSS_MUX โ MSS_SCB_CFM_SGMII_MUX โ MSS_SCB_DDR_PLL โ MSS_SCB_MSS_PLL โ MSS_SCB_SGMII_PLL โ SCBCFG_REGS โ SCB_REGS โ __app_hart_common_end โ __app_hart_common_start โ __bss_end โ __bss_start โ __data_end โ __data_load โ __data_start โ __e51itim_end โ __e51itim_start โ __init_array_end โ __init_array_start โ __l2lim_end โ __l2lim_start โ __sbss_end โ __sbss_start โ __sdata_end โ __sdata_load โ __sdata_start โ __stack_bottom_h0__ โ __stack_bottom_h1__ โ __stack_bottom_h2__ โ __stack_bottom_h3__ โ __stack_bottom_h4__ โ __stack_top_h0__ โ __stack_top_h1__ โ __stack_top_h2__ โ __stack_top_h3__ โ __stack_top_h4__ โ __text_end โ __text_load โ __text_start โ __u54_1_itim_end โ __u54_1_itim_start โ __u54_2_itim_end โ __u54_2_itim_start โ __u54_3_itim_end โ __u54_3_itim_start โ __u54_4_itim_end โ __u54_4_itim_start โ __uninit_bottom__ โ __uninit_top__ โ g_emac0 โ g_emac1 โ g_mac0 โ g_mac1 โ g_mss_can_0_hi โ g_mss_can_0_lo โ This instances of mss_can_instance_t holds all data related to the operations
performed by CAN. A pointer to instance is passed as the first parameter
to CAN driver functions to indicate that which CAN instance should perform the
requested operation. g_mss_can_1_hi โ g_mss_can_1_lo โ g_mss_i2c0_hi โ This instance of mss_i2c_instance_t holds all data related to the operations
performed by MSS I2C 0 connected on main APB bus. The MSS_I2C_init()function
initializes this structure. A pointer to g_mss_i2c0_lo is passed as the first
parameter to MSS I2C driver functions to indicate that MSS I2C 0 should
perform the requested operation. g_mss_i2c0_lo โ This instance of mss_i2c_instance_t holds all data related to the operations
performed by MSS I2C 0 connected on main APB bus. The MSS_I2C_init()function
initializes this structure. A pointer to g_mss_i2c0_lo is passed as the first
parameter to MSS I2C driver functions to indicate that MSS I2C 0 should
perform the requested operation. g_mss_i2c1_hi โ This instance of mss_i2c_instance_t holds all data related to the operations
performed by MSS I2C 1 connected on main APB bus. The MSS_I2C_init()function
initializes this structure. A pointer to g_mss_i2c1_lo is passed as the first
parameter to MSS I2C driver functions to indicate that MSS I2C 1 should
perform the requested operation. g_mss_i2c1_lo โ This instance of mss_i2c_instance_t holds all data related to the operations
performed by MSS I2C 1 connected on main APB bus. The MSS_I2C_init()function
initializes this structure. A pointer to g_mss_i2c1_lo is passed as the first
parameter to MSS I2C driver functions to indicate that MSS I2C 1 should
perform the requested operation. g_mss_uart0_hi โ g_mss_uart0_lo โ / /**
This instance of mss_uart_instance_t holds all data related to the operations
performed by the MMUART. The function MSS_UART_init() initializes this structure.
A pointer to g_mss_uart0_lo is passed as the first parameter to MSS UART driver
functions to indicate that MMUART0 should perform the requested operation. g_mss_uart1_hi โ g_mss_uart1_lo โ g_mss_uart2_hi โ g_mss_uart2_lo โ g_mss_uart3_hi โ g_mss_uart3_lo โ g_mss_uart4_hi โ g_mss_uart4_lo โ num_pmp_lut โ plic_hart_lookup โ readvalue โ wdog_hw_base โ E51_ecc_correct_local_IRQHandler โ E51_ecc_error_local_IRQHandler โ E51_envm_local_IRQHandler โ E51_f2m_32_local_IRQHandler โ E51_f2m_33_local_IRQHandler โ E51_f2m_34_local_IRQHandler โ E51_f2m_35_local_IRQHandler โ E51_f2m_36_local_IRQHandler โ E51_f2m_37_local_IRQHandler โ E51_f2m_38_local_IRQHandler โ E51_f2m_39_local_IRQHandler โ E51_f2m_40_local_IRQHandler โ E51_f2m_41_local_IRQHandler โ E51_f2m_42_local_IRQHandler โ E51_f2m_43_local_IRQHandler โ E51_f2m_44_local_IRQHandler โ E51_f2m_45_local_IRQHandler โ E51_f2m_46_local_IRQHandler โ E51_f2m_47_local_IRQHandler โ E51_f2m_48_local_IRQHandler โ E51_f2m_49_local_IRQHandler โ E51_f2m_50_local_IRQHandler โ E51_f2m_51_local_IRQHandler โ E51_f2m_52_local_IRQHandler โ E51_f2m_53_local_IRQHandler โ E51_f2m_54_local_IRQHandler โ E51_f2m_55_local_IRQHandler โ E51_f2m_56_local_IRQHandler โ E51_f2m_57_local_IRQHandler โ E51_f2m_58_local_IRQHandler โ E51_f2m_59_local_IRQHandler โ E51_f2m_60_local_IRQHandler โ E51_f2m_61_local_IRQHandler โ E51_f2m_62_local_IRQHandler โ E51_f2m_63_local_IRQHandler โ E51_g5c_devrst_local_IRQHandler โ E51_g5c_message_local_IRQHandler โ E51_maintenance_local_IRQHandler โ E51_mmuart0_local_IRQHandler โ E51_scb_local_IRQHandler โ E51_software_IRQHandler โ E51_sysTick_IRQHandler โ E51_usoc_smb_local_IRQHandler โ E51_usoc_vc_local_IRQHandler โ E51_wdog0_mvrp_local_IRQHandler โ E51_wdog0_tout_local_IRQHandler โ E51_wdog1_tout_local_IRQHandler โ E51_wdog2_tout_local_IRQHandler โ E51_wdog3_tout_local_IRQHandler โ E51_wdog4_tout_local_IRQHandler โ GPIO_clear_all_irq_sources โ The GPIO_clear_all_irq_sources() function is used to clear all the active
interrupts generated by the GPIO specified as a parameter. The
GPIO_clear_all_irq_sources() function must be called as part of a GPIO
interrupt service routine (ISR) in order to prevent the same interrupt event
from re-triggering a call to the GPIO ISR.
Note that interrupts may also need to be cleared in the processorโs
interrupt controller. GPIO_clear_irq โ The GPIO_clear_irq() function is used to clear the interrupt generated by
the GPIO specified as a parameter. The GPIO_clear_irq() function must be
called as part of a GPIO interrupt service routine (ISR) in order to prevent
the same interrupt event from re-triggering a call to the GPIO ISR.
Note that interrupts may also need to be cleared in the processorโs
interrupt controller. GPIO_config โ The GPIO_config() function is used to configure an individual GPIO port. GPIO_disable_irq โ The GPIO_disable_irq() function is used to disable interrupts from being
generated based on the state of the input specified as a parameter. GPIO_drive_inout โ The GPIO_drive_inout() function is used to set the output state of a
GPIO configured as INOUT. An INOUT GPIO is in one of three states: GPIO_enable_irq โ The GPIO_enable_irq() function is used to enable an interrupt to be
generated based on the state of the input identified as a parameter. GPIO_get_inputs โ The GPIO_get_inputs() function is used to read the state of all GPIOs
configured as inputs. GPIO_get_irq_sources โ The GPIO_get_irq_sources() function is used to identify the source of the
interrupt. i.e. to That is the GPIO input line, whose state change triggered
the interrupt. The GPIO_get_irq_sources() function must be called as part of
a GPIO interrupt service routine (ISR) in order to determine the interrupt
source. GPIO_get_outputs โ The GPIO_get_outputs() function is used to read the current state of all
GPIO outputs. GPIO_init โ The GPIO_init() function initializes a CoreGPIO hardware instance and the data
structure associated with the CoreGPIO hardware instance.
Note that a CoreGPIO hardware instance is generated with a fixed configuration
for some or all of its IOs as part of the hardware flow.
Attempting to modify the configuration of such a hardware-configured IO using
the GPIO_config() function has no effect. GPIO_set_output โ The GPIO_set_output() function is used to set the state of a single GPIO port
configured as an output. GPIO_set_outputs โ The GPIO_set_outputs() function is used to set the state of the GPIO ports
configured as outputs. HAL_disable_interrupts โ //**
Disable all interrupts at the processor core level.
Return the interrupts enable state before disabling occurred so that it can
later be restored. HAL_enable_interrupts โ //**
Enable all interrupts at the processor level. HAL_restore_interrupts โ //**
Restore the interrupts enable state at the processor core level.
This function is normally passed the value returned from a previous call to
HAL_disable_interrupts(). HW_get_8bit_reg โ //**
HW_get_8bit_reg is used to read the content of a 8 bits wide peripheral
register. HW_get_8bit_reg_field โ //**
HW_get_8bit_reg_field is used to read the content of a field from a
8 bits wide peripheral register. HW_get_16bit_reg โ //**
HW_get_16bit_reg is used to read the content of a 16 bits wide peripheral
register. HW_get_16bit_reg_field โ //**
HW_get_16bit_reg_field is used to read the content of a field from a
16 bits wide peripheral register. HW_get_32bit_reg โ //**
HW_get_32bit_reg is used to read the content of a 32 bits wide peripheral
register. HW_get_32bit_reg_field โ //**
HW_get_32bit_reg_field is used to read the content of a field out of a
32 bits wide peripheral register. HW_set_8bit_reg โ //**
HW_set_8bit_reg is used to write the content of a 8 bits wide peripheral
register. HW_set_8bit_reg_field โ //**
HW_set_8bit_reg_field is used to set the content of a field in a 8 bits
wide peripheral register. HW_set_16bit_reg โ //**
HW_set_16bit_reg is used to write the content of a 16 bits wide peripheral
register. HW_set_16bit_reg_field โ //**
HW_set_16bit_reg_field is used to set the content of a field in a 16 bits
wide peripheral register. HW_set_32bit_reg โ //**
HW_set_32bit_reg is used to write the content of a 32 bits wide peripheral
register. HW_set_32bit_reg_field โ //**
HW_set_32bit_reg_field is used to set the content of a field in a 32 bits
wide peripheral register. MSS_AXISW_get_hwcfg โ MSS_AXISW_get_vid โ MSS_AXISW_read_burstiness โ MSS_AXISW_read_qos_val โ MSS_AXISW_read_rate โ MSS_AXISW_read_slave_ready โ MSS_AXISW_write_burstiness โ MSS_AXISW_write_qos_val โ MSS_AXISW_write_rate โ MSS_AXISW_write_slave_ready โ MSS_CAN_clear_int_ebl โ The MSS_CAN_clear_int_ebl() function disable specific interrupt based on
irq_flag parameter. MSS_CAN_clear_int_status โ The MSS_CAN_clear_int_status() function clears the selected interrupt flags. MSS_CAN_config_buffer โ The MSS_CAN_config_buffer() function configures receive mailboxes initialized
for Basic CAN operation. MSS_CAN_config_buffer_n โ The MSS_CAN_config_buffer_n() function configures the receive mailbox
specified in mailbox_number. The function checks that the mailbox is set for
Full CAN operation, if not it return with error code. MSS_CAN_get_error_status โ The MSS_CAN_get_error_status() function returns the present error state of
the CAN controller. Error state might be error active or error passive or
bus-off. MSS_CAN_get_global_int_ebl โ The MSS_CAN_get_global_int_ebl() function returns the status of global
interrupt enable flag. MSS_CAN_get_id โ The MSS_CAN_get_id() function returns the message identifier. Bits right
justified based on message identifier (Extended identifier) type. MSS_CAN_get_int_ebl โ The MSS_CAN_get_int_ebl() function returns the status of interrupt enable
flags. MSS_CAN_get_int_status โ The MSS_CAN_get_int_status() function returns the status of interrupts. MSS_CAN_get_mask_n โ The MSS_CAN_get_mask_n() function returns the message filter settings of the
selected receive mailbox. The function is valid for Full CAN operation only. MSS_CAN_get_message โ The MSS_CAN_get_message() function read message from the first mailbox set
for Basic CAN operation that contains a message. Once the message has been
read from the mailbox, the message receipt is acknowledged.
Note: Since neither a hardware nor a software FIFO exists, message inversion
might happen (example, a newer message might be read from the receive
buffer prior to an older message). MSS_CAN_get_message_av โ The MSS_CAN_get_message_av() function indicates if receive buffer contains a
new message in Basic CAN operation. MSS_CAN_get_message_n โ The MSS_CAN_get_message_n() function read message from the receive mailbox
specified in โmailbox_numberโ parameter and returns status of operation. MSS_CAN_get_msg_filter_mask โ The MSS_CAN_get_msg_filter_mask() function packs the ID, IDE, and RTR bits
together as they are used in the message filter mask and returns packed
identifier. MSS_CAN_get_rtr_message_abort_n โ The MSS_CAN_get_rtr_message_abort_n() function aborts a RTR message transmit
request on mailbox mailbox_number and checks that message abort was
successful. MSS_CAN_get_rx_buffer_status โ The MSS_CAN_get_rx_buffer_status() function returns the buffer status of all
receive (32) mailboxes. MSS_CAN_get_rx_error_count โ The MSS_CAN_get_rx_error_count() function returns the current receive error
counter value. Counter value ranges from 0x00 - 0xFF. MSS_CAN_get_rx_gte96 โ The MSS_CAN_get_rx_gte96() function provides information about receive
error count. It identifies that receive error count is greater than or equal
to 96, and reports 1 if count exceeds 96. MSS_CAN_get_tx_buffer_status โ The MSS_CAN_get_tx_buffer_status() function returns the buffer status of all
transmit(32) mailboxes. MSS_CAN_get_tx_error_count โ The MSS_CAN_get_tx_error_count() function returns the current transmit error
counter value. Counter value ranges from 0x00 - 0xFF. MSS_CAN_get_tx_gte96 โ The MSS_CAN_get_tx_gte96() function provides information about transmit
error count. It identifies that transmit error count is greater than or equals
to 96, and reports 1 if count exceeds 96. MSS_CAN_init โ The MSS_CAN_init() function initializes the CAN driver as well as the CAN
controller. The basic_can_rx_mb and basic_can_tx_mb are used to configure the
number of receive and transmit mailboxes in basic CAN operation. This function
configures the CAN channel speed as per the โbitrateโ parameter. It
initializes all receive mailboxes and make it ready for configuration. This is
the first function to be called before using any other function. MSS_CAN_send_message โ The MSS_CAN_send_message() function will copy the data to the first available
mailbox set for Basic CAN operation and send data on to the bus.
Note: Since neither a hardware nor a software FIFO exists, message inversion
might happen (example, a newer message might be send from the transmit
buffer prior to an older message). MSS_CAN_send_message_abort_n โ The MSS_CAN_send_message_abort_n() function aborts a message transmit
request for the specified mailbox number in mailbox_number and checks that
message abort status. MSS_CAN_send_message_n โ The MSS_CAN_send_message_n() function sends a message using mailbox
โmailbox_numberโ. The function verifies that this mailbox is configured for
Full CAN operation and is empty. MSS_CAN_send_message_ready โ The MSS_CAN_send_message_ready() function will identify the availability of
mailbox to fill with new message in basic CAN operation. MSS_CAN_set_config_reg โ The MSS_CAN_set_config_reg() function sets the configuration register and
starts the CAN controller for normal mode operation. This function is used
when one needs to change the configuration settings while the CAN controller
was already initialized using MSS_CAN_init() function and is running.
MSS_CAN_set_config_reg() function should not be used when the CAN controller
wasnโt initialized yet. MSS_CAN_set_id โ The MSS_CAN_set_id() function returns ID bits left justified based on IDE
type. IDE type might be either standard or extended. MSS_CAN_set_int_ebl โ The MSS_CAN_set_int_ebl() function enable specific interrupt based on
irq_flag parameter. MSS_CAN_set_mask_n โ The MSS_CAN_set_mask_n() function configures the message filter settings for
the selected receive mailbox. The function is valid for Full CAN operation
only. MSS_CAN_set_mode โ The MSS_CAN_set_mode() function sets the CAN controller operating mode based
on the mode parameter. After this operation CAN controller is not in
operational, to do that invoke MSS_CAN_start() function. MSS_CAN_set_rtr_message_n โ The MSS_CAN_set_rtr_message_n () function loads mailbox with the given CAN
message. This message will be sent out after receipt of a RTR message
request. It verifies that whether the given mailbox is configured for Full
CAN or not and also checks for RTR auto-reply is enabled or not. MSS_CAN_start โ The MSS_CAN_start() function clears all pending interrupts and enable CAN
controller to perform normal operation. It enables receive interrupts also. MSS_CAN_stop โ The MSS_CAN_stop() function is used to disable the CAN controller. MSS_CFM_channel_mode โ The MSS_CFM_channel_mode() function is used to set the measurement mode for
the specified channel.
2โb00: Disabled
2โb01: Frequency Mode
2โb11: Timer Mode
2โb10: Reserved MSS_CFM_control_start โ The MSS_CFM_control_start() function causes the measurement circuitry
to start. This state of โbusyโ will clear which measurement is complete. MSS_CFM_control_stop โ The MSS_CFM_control_stop() function causes the measurement circuitry
to stop. MSS_CFM_get_count โ The MSS_CFM_get_count() function is used to get the count value.
Block must not be busy. MSS_CFM_runtime_register โ The MSS_CFM_runtime_register() function is used to set how many reference
clock cycles the frequency and time measurement should be made.
The register does NOT change during oepration MSS_CLF_clk_configuration โ The MSS_CLF_clk_configuration() function is used to configure the clock
selection register. MSS_DDR_init_simulation โ //** MSS_DDR_training โ //** MSS_GPIO_clear_irq โ MSS_GPIO_clear_irq() clears a pending interrupt from the specified GPIO input. MSS_GPIO_config โ MSS_GPIO_config() configures an individual GPIO port. MSS_GPIO_config_all โ MSS_GPIO_config_all() configures all the ports of the GPIO block. This
function applies the same configuration values to all GPIO ports. MSS_GPIO_config_byte โ MSS_GPIO_config_byte() configures the GPIO ports byte-wise (consecutive eight
ports). MSS_GPIO_disable_irq โ MSS_GPIO_disable_irq() disables interrupt generation for the specified GPIO
input. This function also disables the corresponding GPIO direct interrupt on
the PLIC. MSS_GPIO_disable_nondirect_irq โ MSS_GPIO_disable_nondirect_irq() disables the non-direct interrupt input at
the PLIC. MSS_GPIO_drive_inout โ MSS_GPIO_drive_inout() sets the output state of a single GPIO port configured
as an INOUT. MSS_GPIO_enable_irq โ MSS_GPIO_enable_irq() enables interrupt generation for the specified GPIO
input. Interrupts are generated based on the state of the GPIO input and the
interrupt mode configured for it by MSS_GPIO_config(). This function enables
the corresponding GPIO direct interrupt on the PLIC as well. MSS_GPIO_enable_nondirect_irq โ MSS_GPIO_enable_nondirect_irq() enables the non-direct interrupt input at the
PLIC. MSS_GPIO_init โ The MSS_GPIO_init() function initializes the PolarFire SoC MSS GPIO block. It
resets the MSS GPIO hardware block and clears any pending MSS GPIO interrupts
in the interrupt controller. When the function exits, it takes the MSS GPIO
block out of reset. MSS_GPIO_set_output โ MSS_GPIO_set_output() sets the state of a single GPIO port configured as an
output. MSS_I2C_clear_gca โ The MSS_I2C_clear_gca() function is used to clear the general call
acknowledgment bit of an MSS I2C slave device. This will stop the I2C slave
device responding to any general call or broadcast message from the master. MSS_I2C_clear_smbus_alert โ The MSS_I2C_clear_smbus_alert() function is used de-assert the MSS I2C๏ฟฝs
I2C_X_SMBALERT_NO signal once a slave device has had a response from the
master. The MSS I2C is the SMBus slave in this case. MSS_I2C_disable_slave โ I2C slave disable. MSS_I2C_disable_smbus_irq โ The MSS_I2C_disable_smbus_irq() function is used to disable the MSS I2Cโs
SMBSUS and SMBALERT SMBus interrupts. MSS_I2C_enable_slave โ I2C slave enable. MSS_I2C_enable_smbus_irq โ The MSS_I2C_enable_smbus_irq() function is used to enable the MSS I2C๏ฟฝs SMBSUS
and SMBALERT SMBus interrupts. MSS_I2C_get_status โ I2C status MSS_I2C_get_user_data โ The MSS_I2C_get_user_data() function is used to allow the retrieval of the
address of a block of application specific data associated with an MSS I2C
peripheral. The composition of the data block is an application matter and the
driver simply provides the means for the application to set and retrieve the
pointer. This may for example be used to provide additional channel specific
information to the slave write handler. MSS_I2C_init โ MSS I2C initialization routine. MSS_I2C_read โ I2C master read. MSS_I2C_register_transfer_completion_handler โ The MSS_I2C_register_transfer_completion_handler() function is used register
transfer completion call back function. This mechanism is used to
notify the completion of the previously initiated I2C transfer when MSS I2C
instance is operating as I2C Master. This call back function will be called
when the transfer is completed. It will also inform the transfer status as a
parameter of the completion handler function.
This function must be called after I2C initialization and before starting any
transmit or receive operations. MSS_I2C_register_write_handler โ I2C write handler registration. MSS_I2C_reset_smbus โ The MSS_I2C_reset_smbus() function resets the MSS I2Cโs SMBus connection by
forcing SCLK low for 35mS. The reset is automatically cleared after 35ms have
elapsed. The MSS I2C is the SMBus master in this case. MSS_I2C_resume_smbus_slave โ The MSS_I2C_resume_smbus_slave() function de-asserts the MSS I2Cโs
I2C_X_SMBSUS_NO output signal to take any connected slave devices out of
suspend mode. The MSS I2C is the SMBus master in this case. MSS_I2C_set_gca โ The MSS_I2C_set_gca() function is used to set the general call acknowledgment
bit of an MSS I2C slave device. This allows the slave device respond to a
general call or broadcast message from an I2C master. MSS_I2C_set_slave_mem_offset_length โ I2C slave memory offset length configuration. MSS_I2C_set_slave_rx_buffer โ I2C slave receive buffer configuration. MSS_I2C_set_slave_tx_buffer โ I2C slave transmit buffer configuration. MSS_I2C_set_smbus_alert โ The MSS_I2C_set_smbus_alert() function is used to force master communication
with an I2C slave device by asserting the MSS I2Cโs I2C_X_SMBALERT_NO signal.
The MSS I2C is the SMBus master in this case. MSS_I2C_set_user_data โ The MSS_I2C_set_user_data() function is used to allow the association of a
block of application specific data with an MDD I2C peripheral. The composition
of the data block is an application matter and the driver simply provides the
means for the application to set and retrieve the pointer. This may for
example be used to provide additional channel specific information to the
slave write handler. MSS_I2C_smbus_init โ The MSS_I2C_smbus_init() function enables SMBus timeouts and status logic. Set
the frequency parameter to the MSS I2C๏ฟฝs PCLK frequency for 25ms SMBus
timeouts, or to any frequency between 1 MHz and 255 MHz for to adjust the
timeout. MSS_I2C_suspend_smbus_slave โ The MSS_I2C_suspend_smbus_slave() function forces any SMBUS slave devices
connected to an MSS I2C peripheral into power down or suspend mode by
asserting the MSS I2C๏ฟฝs I2C_X_SMBSUS_NO output signal. The MSS I2C is the
SMBus master in this case. MSS_I2C_system_tick โ Time out delay expiration. MSS_I2C_wait_complete โ Wait for I2C transaction completion. MSS_I2C_write โ I2C master write function. MSS_I2C_write_read โ I2C master write-read MSS_MAC_NULL_phy_autonegotiate โ MSS_MAC_NULL_phy_get_link_status โ MSS_MAC_NULL_phy_init โ MSS_MAC_NULL_phy_mac_autonegotiate โ MSS_MAC_NULL_phy_set_link_speed โ MSS_MAC_RTL8211_mac_autonegotiate โ MSS_MAC_RTL8211_phy_autonegotiate โ MSS_MAC_RTL8211_phy_get_link_status โ MSS_MAC_RTL8211_phy_init โ MSS_MAC_RTL8211_phy_set_link_speed โ MSS_MAC_cfg_struct_def_init โ //**
The MSS_MAC_cfg_struct_def_init() function initializes a mss_mac_cfg_t
configuration data structure to default values. The default configuration uses
the NULL_PHY interface connected to a PHY at address 0x00 which is set to
auto-negotiate at all available speeds up to 1000Mbps. This default
configuration can then be used as parameter to MSS_MAC_init() . Typically,
the default configuration would be modified to suit the application before
being passed to MSS_MAC_init() . MSS_MAC_change_speed โ //**
The MSS_MAC_change_speed() function sets the speed and duplex mode for the
link and if autonegotiation is selected as the speed mode, also sets the speed
and duplex options to advertise. MSS_MAC_clear_statistics โ //**
@brief
The MSS_MAC_clear_statistics() function clears all the statistics counter
registers for the selected MAC. MSS_MAC_get_TSU_oss_mode โ //**
The MSS_MAC_get_TSU_oss_mode() function returns the currently configured one
step sync (OSS) mode for the MAC. MSS_MAC_get_TSU_rx_mode โ //**
The MSS_MAC_get_TSU_rx_mode() function allows the application determine the
current TSU receive time stamping mode. MSS_MAC_get_TSU_tx_mode โ //**
The MSS_MAC_get_TSU_tx_mode() function allows the application determine the
current TSU tranmit time stamping mode. MSS_MAC_get_TSU_unicast_addr โ //**
The MSS_MAC_get_TSU_unicast_addr() function retrieves the IP addresses that
the Ethernet MAC uses to identify unicast PTP frames. MSS_MAC_get_VLAN_only_mode โ //**
The MSS_MAC_get_VLAN_only_mode() function retrieves the current VLAN only
mode status. When VALN only mode is enabled, non VLAN tagged packets will be
discarded. MSS_MAC_get_hash โ //**
The MSS_MAC_get_hash() function retrieves the current 64 bit addressing hash
field from the Ethernet MAC. MSS_MAC_get_hash_mode โ //**
The MSS_MAC_get_hash_mode() function retrieves the current operational mode
for the hash based address matching. MSS_MAC_get_jumbo_frame_length โ //**
The MSS_MAC_get_jumbo_frame_length() function is used to retrieve the
current maximum length of Jumbo frames that can be received. For this function
to work correctly, the jumbo_frame_enable value in the mss_mac_cfg_t
structure used to configure the Ethernet MAC will have to have been set to
true. MSS_MAC_get_jumbo_frames_mode โ //**
The MSS_MAC_get_jumbo_frames_mode() function is used to determine if Jumbo
frame support is enabled or not. MSS_MAC_get_link_status โ //**
The MSS_MAC_get_link_status() function retrieves the status of the link from
the Ethernet PHY. It returns the current state of the Ethernet link. The speed
and duplex mode of the link is also returned via the two pointers passed as
parameter if the link is up, if the link is not up then these values willl not
be updated. MSS_MAC_get_mmsl_mode โ //**
The MSS_MAC_get_mmsl_mode() function is used to retrieve the current
configuration of the MAC Merge Sublayer component of the GEM. MSS_MAC_get_mmsl_stats โ //**
The MSS_MAC_get_mmsl_stats() function is used to retrieve the statistics
counts from the MAC Merge Sublayer component of the GEM. MSS_MAC_get_mmsl_status โ //**
The MSS_MAC_get_mmsl_status() function is used to monitor the current state
of the MAC Merge Sublayer component of the GEM. The function returns the raw
32 bit value from the MMSL Status register and the definitions in
mss_ethernet_mac_regs.h can be used to examine the status. MSS_MAC_get_pause_frame_copy_to_mem โ //**
The MSS_MAC_get_pause_frame_copy_to_mem() function is used to determine
whether the GEM is currently configured to copy pause frames to memory. MSS_MAC_get_rx_cutthru โ //**
The MSS_MAC_get_rx_cutthru() function is used to retrieve the current
receive cutthru level for the GEM DMA engine. MSS_MAC_get_sa_filter โ //**
The MSS_MAC_get_sa_filter() function retrieves the current specific address
filter settings from the Ethernet MAC. These filters allow selective reception
of packets based on matching the destination or source MAC address field in
the packet. MSS_MAC_get_stacked_VLAN โ //**
The MSS_MAC_get_stacked_VLAN() function retrieves the current stacked VLAN
tag register from the Ethernet MAC. MSS_MAC_get_tx_cutthru โ //**
The MSS_MAC_get_tx_cutthru() function is used to retrieve the current
transmit cutthru level for the GEM DMA engine. MSS_MAC_get_type_1_filter โ //**
The MSS_MAC_get_type_1_filter() function is used to retrieve the current
Type 1 filter configurations from the Ethernet MAC. These filters allow
selective routing of packets to specific queues based on combinations of UDP
port number and/or differentiated service/traffic class values. Packets can
also be flagged for dropping based on the same criteria. MSS_MAC_get_type_2_compare โ //**
The MSS_MAC_get_type_2_compare() function is used to retrieve the current
Type 2 data matching blocks configuration from the Ethernet MAC. MSS_MAC_get_type_2_ethertype โ //**
The MSS_MAC_get_type_2_ethertype() function is used to retrieve the current
settings for Type 2 Ethertype matching blocks in the Ethernet MAC. MSS_MAC_get_type_2_filter โ //**
The MSS_MAC_get_type_2_filter() function is used to retrieve the current
Type 2 filter configuration from the Ethernet MAC. These filters allow
selective routing of packets to specific queues based on combinations of
Ethertype field values, general data patterns and VLAN priority values.
Packets can also be flagged for dropping based on the same criteria. MSS_MAC_get_type_filter โ //**
The MSS_MAC_get_type_filter() function is used to retrieve the current
settings of the specific type filters in the Ethernet MAC. These filters allow
selective reception of packets based on matching the type ID/length field in
the packet. MSS_MAC_init โ //**
The MSS_MAC_init() function initializes the Ethernet MAC hardware and driver
internal data structures. In addition to the MAC identifier, the
MSS_MAC_init() function takes a pointer to a configuration data structure of
type mss_mac_cfg_t as parameter. This configuration data structure contains
all the information required to configure the Ethernet MAC. The
MSS_MAC_init() function initializes the descriptor rings and their pointers
to initial values. The MSS_MAC_init() function enables DMA Rx packet
received and Tx packet sent interrupts. The configuration passed to the
MSS_MAC_init() function specifies the type of interface used to connect the
Ethernet MAC and Ethernet PHY as well as the PHY type and PHY MII management
interface address. It also specifies the allowed link speed and duplex mode.
It is at this point that the application chooses if the link speed and duplex
mode will be auto-negotiated with the link partner or forced to a specific
speed and duplex mode. MSS_MAC_init_TSU โ //**
The MSS_MAC_init_TSU() function configures the Time Stamp Unit (TSU) for
operation and sets the initial count value. MSS_MAC_phy_reset โ //**
The MSS_MAC_phy_reset function provides a mechanism for resetting the PHY
device attached to a given MSS Ethernet MAC peripheral. Both soft and hard
reset signals can be controlled via this function. MSS_MAC_read_TSU โ //**
The MSS_MAC_MSS_MAC_read_TSU() function reads the current timer value from
the TSU. A strict order of reading and a check for nanoseconds overflow is
used to ensure the time is read correctly. MSS_MAC_read_phy_reg โ //**
The MSS_MAC_read_phy_reg() function reads the Ethernet PHY register
specified as parameter. It uses the MII management interface to communicate
with the Ethernet PHY. This function is used by the Ethernet PHY drivers
provided alongside the Ethernet MAC driver. You normally only need to use this
function if writing your own Ethernet PHY driver. MSS_MAC_read_stat โ //**
The MSS_MAC_read_stat() function reads the transmit and receive statistics
of the selected Ethernet MAC. This function can be used to read one of 26
receive statistics and 20 transmitter statistics as defined in the
mss_mac_stat_t enumeration. MSS_MAC_receive_pkt โ //**
The MSS_MAC_receive_pkt() function assigns a buffer to one of the Ethernet
MACโs receive descriptors. The receive buffer specified as parameter will be
used to receive one single packet. The receive buffer will be handed back to
the application via a call to the receive callback function assigned through a
call to MSS_MAC_set_rx_callback() . The MSS_MAC_receive_pkt() function will
need to be called again pointing to the same buffer if more packets are to be
received into this same buffer after the packet has been processed by the
application. MSS_MAC_send_pkt โ //**
The MSS_MAC_send_pkt() function initiates the transmission of a packet. It
places the buffer containing the packet to send into one of the Ethernet MACโs
transmit descriptors. MSS_MAC_send_pkts โ //**
The MSS_MAC_send_pkts() function initiates the transmission of one or more
packets on one or more queues. It initialises all the required transmit queues
and sets the transmit operation in motion. MSS_MAC_set_TSU_oss_mode โ //**
The MSS_MAC_set_TSU_oss_mode() function configures one step sync (OSS)
operation for the Ethernet MAC. The three options allow for disabling OSS,
enabling OSS time stamp replacement mode and enabling OSS correction field
adjustment mode. MSS_MAC_set_TSU_rx_mode โ //**
The MSS_MAC_set_TSU_rx_mode() function configures time stamp recording for
received packets. This allows recording the TSU value for received packets in
the DMA descriptor for different types of packet. MSS_MAC_set_TSU_tx_mode โ //**
The MSS_MAC_set_TSU_tx_mode() function configures time stamp recording for
transmitted packets. This allows recording the TSU value for transmitted
packets in the DMA descriptor for different types of packet. MSS_MAC_set_TSU_unicast_addr โ //**
The MSS_MAC_set_TSU_unicast_addr() function configures IP addresses that the
MAC will use to identify unicast PTP frames. The receive IPv4 address and
transmit IPv4 address can be set separately. MSS_MAC_set_VLAN_only_mode โ //**
The MSS_MAC_set_VLAN_only_mode() function allows the application enable or
disable VLAN only mode. When VALN only mode is enabled, non VLAN tagged
packets will be discarded. MSS_MAC_set_hash โ //**
The MSS_MAC_set_hash() function sets the 64 bit addressing hash field in the
Ethernet MAC. MSS_MAC_set_hash_mode โ //**
The MSS_MAC_set_hash_mode() function sets the operational mode for the hash
based address matching. MSS_MAC_set_jumbo_frame_length โ //**
The MSS_MAC_set_jumbo_frame_length() function is used to set the maximum
length of Jumbo frames that can be received. The maximum allowed is
MSS_MAC_JUMBO_MAX . For this function to work correctly, the
jumbo_frame_enable value in the mss_mac_cfg_t structure used to configure
the Ethernet MAC will have to have been set to true. MSS_MAC_set_jumbo_frames_mode โ //**
The MSS_MAC_set_jumbo_frames_mode() function is used to enable and disable
reception of Jumbo frames. For this function to work correctly, the
jumbo_frame_enable value in the mss_mac_cfg_t structure used to configure
the Ethernet MAC will have to have been set to true. MSS_MAC_set_mmsl_mode โ //**
The MSS_MAC_set_mmsl_mode() function is used to configure the operation of
the MAC Merge Sublayer component of the GEM. This function is used to enable
and disable preemption and to determine which MAC (eMAC or pMAC) is used for
reception in non preemption modes. The function also allows control of the
preemption verification functionality. MSS_MAC_set_pause_frame_copy_to_mem โ //**
The MSS_MAC_set_pause_frame_copy_to_mem() function is used to control the
writing of pause frames into memory. MSS_MAC_set_rx_callback โ //**
The MSS_MAC_set_rx_callback() function registers the function that will be
called by the Ethernet MAC driver when a packet is received. MSS_MAC_set_rx_cutthru โ //**
The MSS_MAC_set_rx_cutthru() function is used to set the receive cutthru
level for the GEM DMA engine. The useful ranges are different for the eMAC
and pMAC. MSS_MAC_set_sa_filter โ //**
The MSS_MAC_set_sa_filter() function is used to configure the specific
address filters in the Ethernet MAC. These filters allow selective reception
of packets based on matching the destination or source MAC address field in
the packet. MSS_MAC_set_stacked_VLAN โ //**
The MSS_MAC_set_stacked_VLAN() function sets the stacked VLAN tag register
in the MAC. This can be used to enable and disable stacked VLAN operation. MSS_MAC_set_tx_callback โ //**
The MSS_MAC_set_tx_callback() function registers the function that will be
called by the Ethernet MAC driver when a packet has been sent on the specified
queue. MSS_MAC_set_tx_cutthru โ //**
The MSS_MAC_set_tx_cutthru() function is used to set the transmit cutthru
level for the GEM DMA engine. The useful ranges are different for the eMAC and
pMAC and will also differ based on the allocation of DMA buffer space to
active queues. MSS_MAC_set_type_1_filter โ //**
The MSS_MAC_set_type_1_filter() function is used to configure the Type 1
filters in the Ethernet MAC. These filters allow selective routing of packets
to specific queues based on combinations of UDP port number and/or
differentiated service/traffic class values. Packets can also be flagged for
dropping based on the same criteria. MSS_MAC_set_type_2_compare โ //**
The MSS_MAC_set_type_2_compare() function is used to configure the Type 2
data matching blocks in the Ethernet MAC. These are used by Type 2 filters to
allow comparing up to 4 bytes of data at different locations in the packet.
They also allow for matching against VLAN IDs. The data matching can be
performed against 4 consecutive bytes or against up to 2 consecutive bytes
with an associated bit mask. MSS_MAC_set_type_2_ethertype โ //**
The MSS_MAC_set_type_2_ethertype() function is used to configure the Type 2
Ethertype matching blocks in the Ethernet MAC. These are used by Type 2
filters to allow selection of packet types. MSS_MAC_set_type_2_filter โ //**
The MSS_MAC_set_type_2_filter() function is used to configure the Type 2
filters in the Ethernet MAC. These filters allow selective routing of packets
to specific queues based on combinations of Ethertype field values, general
data patterns and VLAN priority values. Packets can also be flagged for
dropping based on the same criteria. MSS_MAC_set_type_filter โ //**
The MSS_MAC_set_type_filter() function is used to configure the specific
type filters in the Ethernet MAC. These filters allow selective reception of
packets based on matching the type ID/length field in the packet. MSS_MAC_start_preemption_verify โ //**
The MSS_MAC_start_preemption_verify() function is used to initiate a link
preemption verification operation by the MAC Merge Sublayer component of the
GEM. The progress and completion status of the operation can be monitored by
calling the MSS_MAC_get_mmsl_status() function until the operation
completes. MSS_MAC_tx_enable โ //**
The MSS_MAC_tx_enable() function is used to start or restart transmit
operations. It can be used as part of recovery from errors which may have
resulted in transmission being stopped. MSS_MAC_update_hw_address โ //**
The MSS_MAC_update_hw_address() function updates the MAC address for the
Ethernet MAC. In addition to the MAC identifier, the
MSS_MAC_update_hw_address() function takes a pointer to a configuration data
structure of type mss_mac_cfg_t as a parameter. This configuration data
structure contains all the information required to configure the Ethernet MAC
including the required MAC address. The MSS_MAC_update_hw_address() function
reconfigures the Ethernet MAC using the MAC address contained in the structure
pointed to by cfg. MSS_MAC_write_phy_reg โ //**
The MSS_MAC_write_phy_reg() function writes a 16-bit value to the specified
Ethernet PHY register. It uses the MII management interface to communicate
with the Ethernet PHY. This function is used by the Ethernet PHY drivers
provided alongside the Ethernet MAC driver. You normally only need to use this
function if writing your own Ethernet PHY driver. MSS_MMC_adma2_read โ The MSS_MMC_adma2_read() function is used to read a single or multiple blocks
of data from the eMMC/SD device to the host controller using ADMA2. The size
of the block of data read by this function must be set to 512 bytes or a
multiple of 512 bytes. The 512 bytes is the standard sector size for all
eMMC/SD devices with a capacity of greater than 2 GB. MSS_MMC_adma2_write โ The MSS_MMC_adma2_write() function is used to transfer a single block or
multiple blocks of data from the host controller to the eMMC/SD device using
ADMA2. The size of the block of data transferred by this function must be set
to 512 bytes or a multiple of 512 bytes. The 512 bytes is the standard sector
size for all eMMC/SD devices with a capacity of greater than 2 GB. MSS_MMC_cq_init โ The MSS_MMC_cq_init() function enables command queue in the eMMC device and
in the host controller. The command queue allows the application to queue
multiple read or write tasks. MSS_MMC_cq_read โ The MSS_MMC_cq_read() function is used to read a single block or multiple
blocks of data from the eMMC device to the host controller using command queue
with single or multiple tasks based on the data size. The size of the block of
data read by this function must be set to 512 bytes or a multiple of 512 bytes.
The 512 bytes is the standard sector size for all eMMC devices with a capacity
of greater than 2 GB. MSS_MMC_cq_write โ The MSS_MMC_cq_write() function is used to transmit a single block or multiple
blocks of data from the host controller to the eMMC device using command queue
with single or multiple tasks based on the data size. The size of the block of
data transferred by this function must be set to 512 bytes or a multiple of
512 bytes. The 512 bytes is the standard sector size for all eMMC
devices with a capacity of greater than 2 GB. MSS_MMC_erase โ The MSS_MMC_erase() function is used to erase the eMMC/SD device blocks. MSS_MMC_error_recovery โ The MSS_MMC_error_recovery() function is used to check whether the error is
recoverable or non-recoverable. An error is detected and reported in
interrupt status register by read or write operation. MSS_MMC_get_transfer_status โ The MSS_MMC_get_transfer_status() function returns the status of the MMC
transfer initiated by a call to MSS_MMC_sdma_write(), MSS_MMC_sdma_read(),
MSS_MMC_adma2_write(), MSS_MMC_adma2_read(), MSS_MMC_cq_write(),
MSS_MMC_cq_read() functions. MSS_MMC_init โ The MSS_MMC_init() function initializes the MSS eMMC SD host controller and
the eMMC/SD/SDIO device. The MSS_MMC_init()function takes a pointer to a
configuration data structure of type mss_mmc_cfg_t as parameter. This
configuration data structure contains all the information required to
configure the MSS eMMC SD.
The configuration passed to the MSS_MMC_init() function specifies the type
of interface used to connect the MSS eMMC SD host controller and the
eMMC/SD/SDIO device. It also specifies the allowed clock frequency, data bus
width and bus speed mode. The MSS_MMC_init() function must be called prior
to any MSS eMMC SD data transfer functions being called. MSS_MMC_sdio_single_block_read โ The MSS_MMC_sdio_single_block_read() function is used to read a single block
of data from the the SDIO device function 1 code storage area(CSA) to host
controller. The size of the block of data transferred by this function
is set to in the range of 1 to 512 bytes. MSS_MMC_sdio_single_block_write โ The MSS_MMC_sdio_single_block_write() function is used to transfer a single
block of data from the host controller to the SDIO device function 1
code storage area(CSA). The size of the block of data transferred by this
function is 1 to 512 bytes. MSS_MMC_sdma_read โ The MSS_MMC_sdma_read() function is used to read a single block or multiple
blocks of data from the eMMC/SD device to the host controller using SDMA. The
size of the block of data read by this function must be set to 512 bytes or
a multiple of 512 bytes. The 512 bytes is the standard sector size for all
eMMC/SD devices with a capacity of greater than 2 GB. MSS_MMC_sdma_write โ The MSS_MMC_sdma_write() function is used to transfer a single block or multi
blocks of data from the host controller to the eMMC/SD device using SDMA.
The size of the block of data transferred by this function must be set to 512
bytes or a multiple of 512 bytes. The 512 bytes is the standard sector
size for all eMMC/SD devices with a capacity of greater than 2 GB. MSS_MMC_set_handler โ The MSS_MMC_set_handler() function registers a handler function that will be
called by the driver when a read o write transfer completes. The application
must create and register a transfer completion handler function. The MSS
eMMC SD driver passes the outcome of the transfer to the completion handler
in the form of a status (SRS12 register) parameter indicating if the transfer
is successful or the type of error that occurred during the transfer if the
transfer failed. MSS_MMC_single_block_read โ The MSS_MMC_single_block_read() function is used to read a single block of
data from the eMMC/SD device to the host controller. The size of the block
of data read by this function is always 512 bytes, which is the standard
sector size for all eMMC/SD devices with a capacity of greater than 2 GB. MSS_MMC_single_block_write โ The MSS_MMC_single_block_write() function is used to transmit a single block
of data from the host controller to the eMMC/SD device. The size of the block
of data transferred by this function is always 512 bytes, which is the
standard sector size for all eMMC/SD devices with a capacity of greater than
2 GB. MSS_MPU_configure โ MSS_MPU_get_config โ MSS_PDMA_clear_transfer_complete_status โ The MSS_PDMA_clear_transfer_complete_status() function is used to request the
transfer complete interrupt status. If the function returns one, that indicates
that the transfer is complete and the transfer complete interrupt is cleared. MSS_PDMA_clear_transfer_error_status โ The MSS_PDMA_clear_transfer_error_status() function is used to request the
transfer error interrupt status. If the function returns one, that indicates
that the transfer error has occurred and error interrupt is cleared. MSS_PDMA_get_active_transfer_type โ The MSS_PDMA_get_active_transfer_type() function is used to request active
transfer type for selected DMA channel.
The transfer type for the DMA channel was configured during the channel
configuration process, calling this function will read the transfer type
from the configured DMA channel. MSS_PDMA_get_destination_current_addr โ The MSS_PDMA_get_destination_current_addr() function is used to request the
channel Destination address. MSS_PDMA_get_number_bytes_remaining โ The MSS_PDMA_get_number_bytes_remaining() function is used to request number
of bytes remaining to be transferred. MSS_PDMA_get_source_current_addr โ The MSS_PDMA_get_source_current_addr() function is used to request the
channel Source address. MSS_PDMA_get_transfer_complete_status โ The MSS_PDMA_get_transfer_complete_status() function is used to request the
completion status of last DMA transfer. MSS_PDMA_get_transfer_error_status โ The MSS_PDMA_get_transfer_error_status() function is used to request the
error status of last DMA transfer. MSS_PDMA_set_transaction_size โ The MSS_PDMA_set_transction_size() function is used to set a channel
DMA transaction size. The write_size and read_size buffers are used to
determine the size and alignment of individual PDMA transaction as a single
PDMA transfer may require multiple transaction. MSS_PDMA_setup_transfer โ The MSS_PDMA_setup_transfer() function is used to configure an individual
DMA channel. Apart from selecting the DMA channel the MSS_PDMA_setup_transfer()
function will also setup the transfer size, source and destination addresses.
This function will also configure the repeat and force order requirements as
the PolarFire SoC MSS Peripheral DMA supports multiple simultaneous transfers.
Once transfer is setup, it can be started. MSS_PDMA_start_transfer โ The MSS_PDMA_start_transfer() function is used to initiate an individual
transfer on selected DMA channel . The source and destination address of
the transfer and the number of bytes to be transferred must be configured
before calling this function. MSS_QSPI_configure โ //**
The MSS_QSPI_configure() function configures MSS QSPI to the desired
configuration values. MSS_QSPI_get_config โ //**
The MSS_QSPI_get_config() function reads back the current configurations of
MSS QSPI. The MSS_QSPI_get_config() function is used when you want to read
the current configurations, modify the configuration values of your choice,
and reconfigure the MSS QSPI hardware using the MSS_QSPI_configure() function. MSS_QSPI_init โ //**
The MSS_QSPI_init() function initializes and enables PolarFireSoC MSS QSPI. MSS_QSPI_irq_transfer_block โ //**
The MSS_QSPI_irq_transfer_block() function carries out a QSPI transfer with
the target memory device using the interrupt method of data transfers. The
QSPI transfer characteristics are configured every time a new transfer is
initiated. This is a non-blocking function. You must configure the interrupt
handler function before calling the MSS_QSPI_irq_transfer_block() function. It
enables the interrupts and starts transmitting as many bytes as requested.
When the Transmit-Done interrupt event occurs and this driver calls back the
interrupt handler function that you previously provided, you get an indication
that the actual SPI transmit process is complete. If the transfer includes
receiving data from the target memory device, then the receive-available and
receive-done interrupts are also enabled by the MSS_QSPI_irq_transfer_block()
function. The data is received in the interrupt routine. When the Receive-Done
interrupt event occurs, the interrupt handler you provided is called again. MSS_QSPI_polled_transfer_block โ //**
The MSS_QSPI_polled_transfer_block() function carries out a QSPI transfer with
the target memory device using the polling method of data transfer. The QSPI
transfer characteristics are configured every time a new transfer is
initiated. This is a blocking function. MSS_QSPI_set_status_handler โ //**
The MSS_QSPI_set_status_handler() function registers an interrupt handler
function with this driver that returns the interrupt status back to the
application. This status handler function is called by this driver on two
events. First, when the transmission of the required bytes is completed
(Transmit-Done). Second, if data is to be received from the target memory
device, the MSS_QSPI_set_status_handler() function is called again when the
required data is received (Receive-Done). MSS_SYS_authenticate_bitstream โ The MSS_SYS_authenticate_bitstream() function is used to authenticate
the Bitstream which is located in SPI through a system service routine. Prior
to using the IAP service, it may be required to first validate the new
bitstream before committing the device to reprogramming, thus avoiding the
need to invoke recovery procedures if the bitstream is invalid. MSS_SYS_authenticate_iap_image โ The MSS_SYS_authenticate_iap_image() function is used to authenticate
the IAP image which is located in SPI through a system service routine. The
service checks the image descriptor and the referenced bitstream and optional
initialization data. If the image is authenticated successfully, then the
image is guaranteed to be valid when used by an IAP function. MSS_SYS_debug_fabric_snapshot โ The MSS_SYS_debug_fabric_snapshot() will issue the Debug Snapshot Service to
the system controller. This service generates a snapshot of the volatile
fabric content. Data is read from each LSRAM, ยตRAM and probe module and copied
to the fabric APB debug port. MSS_SYS_debug_live_probe โ The MSS_SYS_debug_live_probe() function will issue the โLive Probe Debug Serviceโ
to the system controller. This service will configures channel โaโ or
โbโ of the live probe system. MSS_SYS_debug_read_apb โ The MSS_SYS_debug_read_apb() function issues the APB Read Debug Service to the
system controller. This service will read a specified number of bytes from
the fabric APB bus to the specified MSS RAM area. MSS_SYS_debug_read_mem โ The MSS_SYS_debug_read_mem() function issues the MEM Read Debug Service to the
system controller. This service provides an interface to read data from the
memory peripheral that is specified. MSS_SYS_debug_read_probe โ The MSS_SYS_debug_read_probe() function will read the content of a
probe module (59 x 18b words). MSS_SYS_debug_select_mem โ The MSS_SYS_debug_select_mem() function will issues the MEM Select Debug Service.
This service will specify a target fabric memory to be accessed by the MEM
read & MEM write services. MSS_SYS_debug_terminate โ The MSS_SYS_debug_terminate() function will issue the Terminate Debug Service
to the system controller. This service will terminate the debug session. MSS_SYS_debug_write_apb โ The MSS_SYS_debug_write_apb() function will issue the APB Write Debug Service.
This service will write bytes of data to the current fabric APB address as
specified by APBADDR. MSS_SYS_debug_write_mem โ The MSS_SYS_debug_write_mem() function issues the MEM Write Debug Service to
the system controller. This service provides an interface to write data from
the memory peripheral that is specified. MSS_SYS_debug_write_probe โ The MSS_SYS_debug_write_probe() function will issue the probe write debug
service to the system controller. It service will writes up to 18 bits of data
to selected probe address. MSS_SYS_digest_check โ The MSS_SYS_digest_check() function is used to Recalculates and compares
digests of selected non-volatile memories. MSS_SYS_digital_signature_service โ The MSS_SYS_digital_signature_service() function is used to generate P-384
ECDSA signature based on SHA384 hash value. MSS_SYS_execute_iap โ The MSS_SYS_execute_iap() function is used to IAP service. The IAP service
allows the user to reprogram the device without the need for an external
master. The user design writes the bitstream to be programmed into a SPI Flash
connected to the SPI port. When the service is invoked, the System Controller
automatically reads the bitstream from the SPI flash and programs the device.
The service allows the image to be executed in either VERIFY or PROGRAM modes.
Another option for IAP is to perform the auto-update sequence. In this case
the newest image of the first two images in the SPI directory is chosen to be
programmed. MSS_SYS_get_design_info โ The function MSS_SYS_get_design_info() is used to execute โGet Design Infoโ
system service. MSS_SYS_get_device_certificate โ The function MSS_SYS_get_device_certificate() is used to execute โGet Device
Certificateโ system service. MSS_SYS_get_serial_number โ The MSS_SYS_get_serial_number() function is used to execute the device serial
number service. MSS_SYS_get_user_code โ The function MSS_SYS_get_user_code() is used to execute โUSERCODEโ system
service. MSS_SYS_nonce_service โ The function MSS_SYS_nonce_service() is used to issue โNonce Serviceโ system
service to the system controller. MSS_SYS_one_way_passcode โ The MSS_SYS_one_way_passcode() function is used to provide a
mechanism for overriding the software debug lock SWL_DEBUG without requiring
any interaction with an external intelligence. MSS_SYS_otp_generate โ The MSS_SYS_otp_generate() function will issue the Generate OTP Service to the
system controller. This service used to set up the device to receive a
one-time passcode. MSS_SYS_otp_match โ The MSS_SYS_otp_match() function will issue the Match OTP Service to the
system controller. This service is the second part of the one-time
passcode protocol. Before using this service the GENERATE OTP service must
first be used to obtain a nonce, NFPGA from the device. MSS_SYS_puf_emulation_service โ The MSS_SYS_puf_emulation_service() function accept a challenge comprising a
8-bit optype and 128-bit challenge and return a 256-bit response unique to
the given challenge and the device. MSS_SYS_query_security โ The function MSS_SYS_query_security() is used to execute โQuery Securityโ
system service. MSS_SYS_read_debug_info โ The function MSS_SYS_read_debug_info() is used to execute โRead Debug infoโ
system service. MSS_SYS_read_digest โ The function MSS_SYS_read_digest() is used to execute โRead Digestโ system
service. MSS_SYS_read_envm_parameter โ The function MSS_SYS_read_envm_parameter() is used to retrieve all parameters
needed for eNVM operation and programming. MSS_SYS_read_response โ The function MSS_SYS_read_response() is used to read the response after
execution of system service in interrupt mode only. For polling mode call to
MSS_SYS_read_response is not required, as the drive performs the response
read operation.
@param void
This function does not have any parameters.
@return
This function returns the status code returned by the system controller
for requested service. MSS_SYS_secure_nvm_read โ The MSS_SYS_secure_nvm_read() function is used to read data present in sNVM
region. User should provide USK key, if the data was programmed using
authentication. MSS_SYS_secure_nvm_write โ The MSS_SYS_secure_nvm_write() function is used to provide write access/write the
data in the sNVM region. Data can be stored in the following format: MSS_SYS_select_service_mode โ The MSS_SYS_service_mode() function is for user to configure system service
execution in polling mode or interrupt mode. This function also registers the
callback handler to the driver which will be called when message interrupt
occurs. MSS_SYS_spi_copy โ The MSS_SYS_spi_copy() function allows data to be copied from the system
controller SPI flash to MSS memory. The SPI SCK frequency is specified by a
user-defined option with valid values shown in parameter description. MSS_SYS_unlock_debug_passcode โ The MSS_SYS_unlock_debug_passcode() will issue the Unlock Debug Passcode
Service to the system controller. This service will Attempt to match
the user debug pass code using the key loaded into the mailbox. If the match
is successful the software debug lock SWL_DEBUG is temporarily inactive. MSS_TIM1_clear_irq โ MSS_TIM1_clear_irq() clears a pending interrupt from Timer 1. This function
also clears the interrupt in the RISC-V PLIC. MSS_TIM1_disable_irq โ MSS_TIM1_disable_irq() disables interrupt generation for Timer 1. This
function also disables the interrupt in the RISC-V PLIC. MSS_TIM1_enable_irq โ MSS_TIM1_enable_irq() enables interrupt generation for Timer 1. This function
also enables the interrupt in the RISC-V PLIC. Timer1_IRQHandler() is called
when a Timer 1 interrupt occurs. MSS_TIM1_get_current_value โ MSS_TIM1_get_current_value() returns the current value of the Timer 1
down-counter. MSS_TIM1_init โ MSS_TIM1_init() initializes the MSS Timer block for use as a 32-bit timer and
selects the operating mode for Timer 1. The MSS Timer block is out of reset
before executing this function. MSS_TIM1_init() stops Timer 1, disables its
interrupt, and sets the Timer 1 operating mode. MSS_TIM1_load_background โ MSS_TIM1_load_background() specifies the value that reloads into the Timer 1
down-counter the next time the counter reaches zero. This function is
typically used when Timer 1 is configured for Periodic mode to select or
change the delay period between the interrupts generated by Timer 1. MSS_TIM1_load_immediate โ MSS_TIM1_load_immediate() loads the value passed by the load_value parameter
into the Timer 1 down-counter. The counter decrements immediately from this
value once Timer 1 is enabled. The MSS Timer generates an interrupt when the
counter reaches zero, if Timer 1 interrupts are enabled. This function is
intended to be used when Timer 1 is configured for One-shot mode to time a
single delay. MSS_TIM1_start โ MSS_TIM1_start() enables Timer 1 and starts its down-counter, decrementing
from the load_value specified in previous calls to MSS_TIM1_load_immediate()
or MSS_TIM1_load_background(). MSS_TIM1_stop โ MSS_TIM1_stop() disables Timer 1 and stops its down-counter. MSS_TIM2_clear_irq โ MSS_TIM2_clear_irq() clears a pending interrupt from Timer 2. This function
also clears the interrupt in the RISC-V PLIC. MSS_TIM2_disable_irq โ MSS_TIM2_disable_irq() disables interrupt generation for Timer 2. This
function also disables the interrupt in the RISC-V PLIC. MSS_TIM2_enable_irq โ MSS_TIM2_enable_irq() enables interrupt generation for Timer 2. This function
also enables the interrupt in the RISC-V PLIC. Timer2_IRQHandler() is called
when a Timer 2 interrupt occurs. MSS_TIM2_get_current_value โ MSS_TIM2_get_current_value() returns the current value of the Timer 2
down-counter. MSS_TIM2_init โ MSS_TIM2_init() initializes the MSS Timer block for use as a 32-bit timer and
selects the operating mode for Timer 2. The MSS Timer block is already out of
reset before executing MSS_TIM2_init(). This function stops Timer 2, disables
its interrupt, and sets the Timer 2 operating mode. MSS_TIM2_load_background โ MSS_TIM2_load_background() specifies the value that is reloaded into the Timer
2 down-counter the next time the counter reaches zero. This function is
typically used when Timer 2 is configured for Periodic mode to select or
change the delay period between the interrupts generated by Timer 2. MSS_TIM2_load_immediate โ MSS_TIM2_load_immediate() loads the value passed by the load_value parameter
into the Timer 2 down-counter. The counter decrements immediately from this
value once Timer 2 is enabled. The MSS Timer generates an interrupt when the
counter reaches zero if Timer 2 interrupts are enabled. This function is
intended to be used when Timer 2 is configured for One-shot mode to time a
single delay. MSS_TIM2_start โ MSS_TIM2_start() enables Timer 2 and starts its down-counter, decrementing
from the load_value specified in previous calls to MSS_TIM2_load_immediate()
or MSS_TIM2_load_background(). MSS_TIM2_stop โ MSS_TIM2_stop() disables Timer 2 and stops its down-counter. MSS_TIM64_clear_irq โ MSS_TIM64_clear_irq() clears a pending interrupt from the 64-bit timer. This
function also clears the interrupt in the RISC-V PLIC. MSS_TIM64_disable_irq โ MSS_TIM64_disable_irq() disables interrupt generation for the 64-bit timer.
This function also disables the interrupt in the RISC-V PLIC. MSS_TIM64_enable_irq โ MSS_TIM64_enable_irq() enables interrupt generation for the 64-bit timer. This
function also enables the interrupt in the RISC-V PLIC. Timer1_IRQHandler() is
called when a 64-bit timer interrupt occurs. MSS_TIM64_enable_irq_for_hart โ MSS_TIM64_get_current_value โ MSS_TIM64_get_current_value() is used to read the current value of the 64-bit
timer down-counter. MSS_TIM64_init โ MSS_TIM64_init() initializes the MSS Timer block for use as a single 64-bit
timer and selects the operating mode of the timer. The MSS Timer block is
already out of reset before executing MSS_TIM64_init(). This function stops
the timer, disables its interrupts, and sets the timerโs operating mode. MSS_TIM64_load_background โ MSS_TIM64_load_background() specifies the 64-bit value that reloads into the
64-bit timer down-counter the next time the counter reaches zero. This
function is typically used when the 64-bit timer is configured for Periodic
mode to select or change the delay period between the interrupts generated by
the 64-bit timer. MSS_TIM64_load_immediate โ MSS_TIM64_load_immediate() loads the values passed by the load_value_u and
load_value_l parameters into the 64-bit timer down-counter. The counter
decrements immediately from the concatenated 64-bit value once the 64-bit
timer is enabled. The MSS Timer generates an interrupt when the counter
reaches zero if 64-bit timer interrupts are enabled. This function is intended
to be used when the 64-bit timer is configured for One-shot mode to time a
single delay. MSS_TIM64_start โ MSS_TIM64_start() enables the 64-bit timer and starts its down-counter,
decrementing from the load_value specified in previous calls to
MSS_TIM64_load_immediate() or MSS_TIM64_load_background(). MSS_TIM64_stop โ MSS_TIM64_stop() disables the 64-bit timer and stops its down-counter. MSS_UART_clear_break โ / /**
The MSS_UART_clear_break() function removes the break signal on the
Tx line. This function can be used only when the MSS UART is initialized in
LIN mode by using MSS_UART_lin_init(). MSS_UART_disable_afclear โ / /**
The MSS_UART_disable_afclear() function disables address flag
clear of the MSS UART. This should be used in conjunction with address flag
detection mode (AFM). MSS_UART_disable_afm โ / /**
The MSS_UART_disable_afm() function disables address flag detection
mode of the MSS UART. MSS_UART_disable_half_duplex โ / /**
The MSS_UART_disable_half_duplex() function disables the half-duplex
(single wire) mode for the MSS UART. Though it finds application in Smartcard
mode, half-duplex mode can be used in other modes as well. MSS_UART_disable_irq โ / /**
The MSS_UART_disable_irq() function disables the MSS UART interrupts specified
by the irq_mask parameter. The irq_mask parameter identifies the MSS UART
interrupts by bit position, as defined in the interrupt enable register (IER)
of MSS UART. The MSS UART interrupts and their identifying bit positions are
as follows: when an irq_mask bit position is set to 1, this function disables
the corresponding MSS UART interrupt in the IER register. When an irq_mask bit
position is set to 0, the state of the corresponding interrupt remains
unchanged in the IER register. MSS_UART_disable_rx_timeout โ / /**
The MSS_UART_disable_rx_timeout() function disables the receiver
timeout functionality of MSS UART. MSS_UART_disable_tx_time_guard โ / /**
The MSS_UART_disable_tx_time_guard() function disables the
transmitter timeguard functionality of MSS UART. MSS_UART_enable_afclear โ / /**
The MSS_UART_enable_afclear() function enables address flag clear
of the MSS UART. This should be used in conjunction with address flag
detection mode (AFM). MSS_UART_enable_afm โ / /**
The MSS_UART_enable_afm() function enables address flag detection
mode of the MSS UART. MSS_UART_enable_half_duplex โ / /**
The MSS_UART_enable_half_duplex() function enables the half-duplex
(single wire) mode for the MSS UART. Though it finds application in Smartcard
mode, half-duplex mode can be used in other modes as well. MSS_UART_enable_irq โ / /**
The MSS_UART_enable_irq() function enables the MSS UART interrupts specified
by the irq_mask parameter. The irq_mask parameter identifies the MSS UART
interrupts by bit position, as defined in the interrupt enable register (IER)
of MSS UART. The MSS UART interrupts and their identifying irq_mask bit
positions are as follows: when an irq_mask bit position is set to 1, this
function enables the corresponding MSS UART interrupt in the IER register. MSS_UART_enable_local_irq โ / /**
The MSS_UART_enable_local_irq() function enables the MMUART
interrupt as a local interrupt to the hart rather than as a PLIC interrupt.
MMUART interrupt can be configured to trigger a PLIC interrupt or it
can be configured to trigger a local interrupt. The arrangement is such that
the UART0 interrupt can appear as local interrupt on E51. The UART1 to UART4
interrupts can appear as local interrupt to U51_1 to U54_4, respectively.
The UART0 to UART4 can appear as PLIC interrupt. Multiple harts can enable
and receive the PLIC interrupt, the hart that claims the interrupt processes
it. For rest of the harts, the IRQ gets silently skipped as the interrupt
claim has already been taken.
To enable the local interrupt, application must explicitly call
MSS_UART_enable_local_irq() function. Note that this function disables the
interrupt over PLIC if it was previously enabled.
This function must be called after the MMUART is initialized, the required
interrupt handler functions are set and before initiating any data transfers.
If you want to register multiple interrupt handlers such as Tx handler, rx
handler and so on, then this function must be called after all such handlers
are set.
Call to this function is treated as one time activity. The driver gives no
option to disable the local interrupt and enable the PLIC interrupt again at
runtime. MSS_UART_enable_rx_timeout โ / /**
The MSS_UART_enable_rx_timeout() function enables and configures
the receiver timeout functionality of MSS UART. This function accepts the
timeout parameter and applies the timeout based up on the baud rate as per
the formula 4 x timeout x bit time. MSS_UART_enable_tx_time_guard โ / /**
The MSS_UART_enable_tx_time_guard() function enables and configures
the transmitter timeguard functionality of MSS UART. This function accepts
the timeguard parameter and applies the timeguard based on the baud rate
as per the formula timeguard x bit time. MSS_UART_fill_tx_fifo โ / /**
The MSS_UART_fill_tx_fifo() function fills the UARTโs hardware transmitter
FIFO with the data found in the transmitter buffer that is passed using the
tx_buffer function parameter. If the transmitter FIFO is not empty when
the function is called, the function returns immediately without transferring
any data to the FIFO; otherwise, the function transfers data from the
transmitter buffer to the FIFO until it is filled or until the full
content of the transmitter buffer is copied into the FIFO. The
function returns the number of bytes copied into the UARTโs transmitter FIFO. MSS_UART_get_modem_status โ / /**
The MSS_UART_get_modem_status() function returns the modem status of the
MSS UART instance. It reads the modem status register (MSR) and returns
the 8-bit value. The bit encoding of the returned value is exactly the
same as the definition of the bits in the MSR. MSS_UART_get_rx โ / /**
The MSS_UART_get_rx() function reads the content of the UART receiverโs FIFO
and stores it in the receive buffer that is passed using the rx_buff
parameter. It copies either the full content of the FIFO into the receive
buffer, or just enough data from the FIFO to fill the receive buffer,
depending on the size of the receive buffer passed by the buff_size
parameter. The MSS_UART_get_rx() function returns the number of bytes copied
into the receive buffer. This function is non-blocking and returns 0
immediately if no data is received. MSS_UART_get_rx_status โ / /**
The MSS_UART_get_rx_status() function returns the receiver error status of the
MSS UART instance. It reads both the current error status of the receiver from
the UARTโs line status register (LSR) and the accumulated error status from
preceding calls to the MSS_UART_get_rx() function, and it combines them using
a bitwise OR. It returns the cumulative overrun, parity, framing, break and
FIFO error status of the receiver, since the previous call to
MSS_UART_get_rx_status(), as an 8-bit encoded value. MSS_UART_get_tx_status โ / /**
The MSS_UART_get_tx_status() function returns the transmitter status of the
MSS UART instance. It reads both the UARTโs line status register (LSR) and
returns the status of the transmit holding register empty (THRE) and
transmitter empty (TEMT) bits. MSS_UART_init โ / /**
The MSS_UART_init() function initializes and configures one of the PolarFireยฎ
SoC MSS UARTs with the configuration passed as parameters. The configuration
parameters are the baud_rate, which generates the baud value, and
the line_config, which specifies the line configuration (bit length,
Stop bits, and parity). MSS_UART_irda_init โ / /**
The MSS_UART_irda_init() function initializes the MSS UART instance
referenced by the this_uart parameter for IrDA mode of operation. This
function must be called before calling any other IrDA specific functions. MSS_UART_irq_tx โ / /**
The function MSS_UART_irq_tx() initiates an interrupt-driven
transmit. It returns immediately after passing the transmit buffer location
to the MMUART instance and enabling transmit interrupts both at the UART and
the PolarFireยฎ SoC Core Complex PLIC level. This function takes a pointer,
the pbuff parameter, to a memory buffer containing the data to transmit. The
memory buffer specified through this pointer must remain allocated and contain
the data to transmit until the transmit completion is detected through calling
the MSS_UART_tx_complete() function. The actual transmission over the serial
connection is still in progress until calls to the MSS_UART_tx_complete()
function indicate transmit completion. MSS_UART_lin_init โ / /**
The MSS_UART_lin_init() function initializes the MSS UART for
LIN mode of operation. The configuration parameters are the baud_rate, which is
used to generate the baud value, and the line_config, which specifies
the line configuration (bit length, Stop bits and parity). MSS_UART_polled_tx โ / /**
The function MSS_UART_polled_tx() transmits data. It transfers the
content of the transmitter data buffer, passed as a function parameter, into
the UARTโs hardware transmitter FIFO. It returns when the full content of the
transmit data buffer is transferred to the UARTโs transmit FIFO. It is
safe to release or reuse the memory used as the transmitter data buffer once
this function returns. MSS_UART_polled_tx_string โ / /**
The function MSS_UART_polled_tx_string() transmits a NULL (โ\0โ)
terminated string. It transfers the text string, located at
the address pointed to by p_sz_string, to the UARTโs hardware transmitter
FIFO. It returns when the complete string is transferred to the UARTโs
transmit FIFO. It is safe to release or reuse the memory used as the string
buffer once this function returns. MSS_UART_set_address โ / /**
The MSS_UART_set_address() function sets the 8-bit address for
the MSS UART, which is referenced by this_uart parameter. MSS_UART_set_break โ / /**
The MSS_UART_set_break() function sends the break
(9 zeros after Stop bit) signal on the Tx line. This function can be used
only when the MSS UART is initialized in LIN mode by using MSS_UART_lin_init(). MSS_UART_set_filter_length โ / /**
The MSS_UART_set_filter_length() function configures the glitch
filter length of the MSS UART. This should be configured in accordance with
the chosen baud rate. MSS_UART_set_linbreak_handler โ / /**
The MSS_UART_set_linbreak_handler () function assigns a custom
interrupt handler for the LIN Break detection interrupt when the MSS UART
is operating in LIN mode. MSS_UART_set_linsync_handler โ / /**
The MSS_UART_set_linsync_handler() function assigns a custom
interrupt handler for the LIN Sync character detection interrupt when the
MSS UART is operating in LIN mode. MSS_UART_set_loopback โ / /**
The MSS_UART_set_loopback() function is used to locally loop-back the Tx and
Rx lines of a UART. This is not to be confused with the loop-back of UART0
to UART1, which can be achieved through the microprocessor subsystemโs
system registers. MSS_UART_set_modemstatus_handler โ / /**
The MSS_UART_set_modemstatus_handler() function registers a modem
status handler function that is called by the driver when a UART modem status
(MS) interrupt occurs. You must create and register the handler function to
suit your application. MSS_UART_set_nack_handler โ / /**
The MSS_UART_set_nack_handler() function assigns a custom interrupt
handler for the NACK character detection interrupt when the MSS UART
is operating in Smartcard mode. MSS_UART_set_pidpei_handler โ / /**
The MSS_UART_set_pidpei_handler() function assigns a custom
interrupt handler for the PIDPEI (PID parity error interrupt) when the MSS
UART is operating in LIN mode. MSS_UART_set_ready_mode โ / /**
The MSS_UART_set_ready_mode() function configures the MODE0 or MODE1
to the TXRDY and RXRDY signals of the MSS UART, which is referenced by
this_uart parameter. The mode parameter is used to provide the mode to be
configured. See the following details for the MODE0 and MODE1 description. MSS_UART_set_rx_endian โ / /**
The MSS_UART_set_rx_endian() function configures the LSB first or
MSB first setting for MSS UART receiver. MSS_UART_set_rx_handler โ / /**
The MSS_UART_set_rx_handler() function registers a receive handler
function that is called by the driver when a UART receive data available (RDA)
interrupt occurs. You must create and register the receive handler function
to suit your application and it must call the MSS_UART_get_rx()
function to actually read the received data. MSS_UART_set_rx_timeout_handler โ / /**
The MSS_UART_set_rx_timeout_handler() function assigns a custom
interrupt handler for the receiver timeout interrupt when the MSS UART is
operating in IrDA mode of operation. MSS_UART_set_rxstatus_handler โ / /**
The MSS_UART_set_rxstatus_handler() function registers a receiver
status handler function that is called by the driver when a UART receiver
line status (RLS) interrupt occurs. You must create and register the handler
function to suit your application. MSS_UART_set_tx_endian โ / /**
The MSS_UART_set_tx_endian() function configures the LSB first or
MSB first setting for MSS UART transmitter. MSS_UART_set_tx_handler โ / /**
The MSS_UART_set_tx_handler() function registers a transmit handler
function that is called by the driver when a UART transmit holding register
empty (THRE) interrupt occurs. You must create and register the transmit
handler function to suit your application. You can then use MSS_UART_irq_tx()
to trigger the interrupt and pass the data you want to transmit. MSS_UART_set_usart_mode โ / /**
The MSS_UART_set_usart_mode() function configures the MSS UART, which is
referenced by the this_uart parameter in USART mode. Various USART modes
are supported which can be configured by the parameter mode of
mss_uart_usart_mode_t type. MSS_UART_smartcard_init โ / /**
The MSS_UART_smartcard_init() function initializes the MSS UART
for ISO 7816 (smartcard) mode of operation. The configuration parameters are
the baud_rate, which generates the baud value, and the line_config,
which specifies the line configuration (bit length, Stop bits and
parity). This function disables all other modes of the MSS UART instance
pointed by the this_uart parameter. MSS_UART_tx_complete โ / /**
The MSS_UART_tx_complete() function is used to find out if the
interrupt-driven transmit previously initiated through a call to
MSS_UART_irq_tx() is complete. This is typically used to find out when it is
safe to reuse or release the memory buffer holding transmit data. MSS_USBD_CIF_cep_configure โ / /** MSS_USBD_CIF_cep_read_pkt โ / /** MSS_USBD_CIF_cep_rx_prepare โ / /** MSS_USBD_CIF_cep_write_pkt โ / /** MSS_USBD_CIF_get_hwcore_info โ Exported APIs from USBD-CIF MSS_USBD_CIF_init โ / /** MSS_USBD_CIF_rx_ep_configure โ MSS_USBD_CIF_rx_ep_read_prepare โ MSS_USBD_CIF_tx_ep_configure โ / /** MSS_USBH_1ms_tick โ The MSS_USBH_1ms_tick() function must be used to provide the 1ms time tick to
the USBH driver. This time reference is used by the USBH driver to keep track
of different time delays required during enumeration process. This way the
application need not wait for the enumeration to complete which may take long
time. MSS_USBH_CIF_bus_resume โ MSS_USBH_CIF_bus_resume() MSS_USBH_CIF_bus_suspend โ MSS_USBH_CIF_bus_suspend() MSS_USBH_CIF_cep_abort_xfr โ MSS_USBH_CIF_cep_abort_xfr() MSS_USBH_CIF_cep_configure โ MSS_USBH_CIF_cep_configure() MSS_USBH_CIF_cep_read_pkt โ MSS_USBH_CIF_cep_read_pkt() MSS_USBH_CIF_cep_start_xfr โ MSS_USBH_CIF_cep_start_xfr() MSS_USBH_CIF_cep_write_pkt โ MSS_USBH_CIF_cep_write_pkt() MSS_USBH_CIF_ep_tx_start โ MSS_USBH_CIF_ep_tx_start() MSS_USBH_CIF_handle_connect_irq โ MSS_USBH_CIF_handle_connect_irq() MSS_USBH_CIF_init โ MSS_USBH_CIF_init() MSS_USBH_CIF_read_vbus_level โ MSS_USBH_CIF_read_vbus_level() MSS_USBH_CIF_rx_ep_configure โ MSS_USBH_CIF_rx_ep_configure() MSS_USBH_CIF_rx_ep_mp_configure โ MSS_USBH_CIF_rx_ep_mp_configure() MSS_USBH_CIF_tx_ep_configure โ MSS_USBH_CIF_tx_ep_configure() MSS_USBH_CIF_tx_ep_mp_configure โ MSS_USBH_CIF_tx_ep_mp_configure() MSS_USBH_abort_in_pipe โ MSS_USBH_abort_out_pipe โ MSS_USBH_configure_control_pipe โ The MSS_USBH_configure_control_pipe() function is used to configure the
control pipe for the control transactions with attached device with the
address provided in target_addr parameter. This function also enables the
control pipe interrupt. MSS_USBH_configure_in_pipe โ The MSS_USBH_configure_in_pipe() function is used to configure the IN pipe
for the IN transactions with the attached device with the address provided in
the target_addr parameter. This function also enables the IN pipe interrupt. MSS_USBH_configure_out_pipe โ The MSS_USBH_configure_out_pipe() function is used to configure the OUT pipe
for the OUT transactions with attached device with the address provided in the
target_addr parameter. This function also enables the OUT pipe interrupt. MSS_USBH_construct_get_descr_command โ The MSS_USBH_construct_get_descr_command() function is be used to construct
the setup packet which is to be sent on the USB bus. This function formats the
provided parameters into a USB standard format GET_DESCRIPTOR request and
stores it in the location provided by the buf parameter. MSS_USBH_get_cep_state โ The MSS_USBH_get_cep_state() function can be used to find out the current
state of the control pipe. A new control transfer can be started when the
control pipe is in the MSS_USB_CEP_IDLE state. MSS_USBH_get_milis โ The MSS_USBH_get_milis() function is used to find out the number of
milliseconds elapsed from the time when last reset occurred. MSS_USBH_get_std_dev_descr โ The MSS_USBH_get_std_dev_descr() function can be used to get the 8 byte USB
standard device descriptor from the attached device. This function is provided
specifically for the ๏ฟฝStandard Descriptor๏ฟฝ test case of USB-IF compliance
procedure. This function might not be useful In general scenarios. MSS_USBH_get_tdev_state โ The MSS_USBH_get_tdev_state() function can be used to find out the current
state of the attached device. E.g. ADDRESS, CONFIGURED etc. (as defined by
USB2.0). MSS_USBH_init โ The MSS_USBH_init() function initializes the MSS USB driver in the USB host
mode. This function initializes the internal data structures and readies the
MSS USB hardware block to detect the device attachment event. This function
also configures the control endpoint to keep it ready for communicating with
the detected device on the USB port. The parameter app_cb provided with this
function must be implemented by the application. This driver uses the app_cb
to inform the application about the events on the USB bus by calling the
appropriate callback element. MSS_USBH_read_in_pipe โ The MSS_USBH_read_in_pipe() function writes the data provided by the user into
the previously configured out pipe FIFO. The data is ready to be transferred
after calling this function. The data will be transferred by the MSS USB
according to the transfer type and the interval parameter set for this OUT
pipe using theMSS_USBH_configure_in_pipe() function. This function is
non-blocking. A call-back function will be called to indicate the status of
this transfer after the status phase of the current IN transaction is
complete. MSS_USBH_register_class_driver โ The MSS_USBH_register_class_driver() function must be used by the application
to register a USBH-Class driver with the USBH driver. The application must
first get the handle from the USBH-Class driver before assigning it to the
USBH driver. Refer the USBH-Class section to know how to get a handle from the
USBH-Class driver. This handle is used by the USBH driver to communicate with
the USBH-Class driver. MSS_USBH_resume โ The MSS_USBH_resume() function can be used to resume the previously suspended
MSS USB. If the MSS USB was in suspend mode then it will start the transaction
scheduler and frame counter after calling this function. MSS_USBH_start_control_xfr โ The MSS_USBH_start_control_xfr() function must be used to start a control
transfer with the attached USB device. This is a non-blocking function.
This function prepares the control pipe for the control transfer. A call-back
function will be called to indicate the status of the transfer after the
status phase of the control transfer is complete. MSS_USBH_suspend โ The MSS_USBH_suspend() function can be used to suspend the MSS USB. The MSS
USB will complete the current transaction then stop the transaction scheduler
and frame counter. No further transactions will be started and no SOF packets
will be generated. MSS_USBH_task โ The MSS_USBH_task() function is the main task of the USBH driver. This
function must be called repeatedly by the application to allow the USBH driver
to perform the housekeeping tasks. A timer/scheduler can be used to call this
function at regular intervals or it can be called from the main continuous
foreground loop of the application. MSS_USBH_test_mode โ The MSS_USBH_test_mode() function can be used to initiate one of the
compliance test modes in the MSS USB. This function is useful only for
compliance test procedures. The MSS USB goes into the specified test mode once
this function is executed. A hard reset is required to resume normal
operations. MSS_USBH_write_out_pipe โ The MSS_USBH_write_out_pipe() function writes the data provided by the user
into the previously configured out pipe FIFO. The data is ready to be
transferred after calling this function. The Data will be transferred by the
MSS USB according to the transfer type and interval parameter set for this
OUT pipe using MSS_USBH_configure_out_pipe() function. This function is
non-blocking.A call-back function will be called to indicate the status of
this transfer after the status phase of the current OUT transaction is
complete. MSS_USB_CIF_cep_is_rxpktrdy โ CSR0L register related APIs MSS_USB_CIF_configure_ep_dma โ MSS_USB_CIF_ep_write_pkt โ MSS_USB_CIF_read_rx_fifo โ MSS_USB_CIF_rx_ep_clr_autoclr โ MSS_USB_CIF_rx_ep_configure โ MSS_USB_CIF_rx_ep_read_prepare โ Prepares the RX EP for receiving data as per parameters provided by upper
layer MSS_USB_CIF_soft_reset โ SOFT_RST register related APIs MSS_USB_CIF_start_testpacket โ USB2.0 test mode functions MSS_USB_CIF_tx_ep_configure โ MSS_WD_configure โ //**
The MSS_WD_configure() function configures the desired watchdog module. The
watchdog module is pre-initialized by the flash bits at the design time to the
default values. You can reconfigure the watchdog module using
MSS_WD_configure() function. MSS_WD_get_config โ The MSS_WD_get_config() function returns the current configuration of the
PolarFire SoC MSS Watchdog. The MSS Watchdog is pre-initialized by the flash
bits at the design time. When used for the first time before calling the
MSS_WD_configure() function, this function returns the default
configuration as configured at the design time. You can reconfigure the
MSS Watchdog using MSS_WD_configure() function. Calling the
MSS_WD_get_config() function will then return the current configuration values
set by a previous call to MSS_WD_configure() function. You may not need to use
this function if you do not want to know the current configuration. In that
case, you can directly use the MSS_WD_configure() function to configure the
MSS Watchdog to the values of your choice. NULL_mmd_read_extended_regs โ NULL_mmd_write_extended_regs โ PF_PCIE_allocate_memory โ The PF_PCIE_allocate_memory() function allocates memory on the PCIe root
port host processor for the PCIe endpoint BARs. This function must be called
after the PF_PCIE_enumeration() function. PF_PCIE_config_space_atr_table_init โ The PF_PCIE_config_space_atr_table_init() function initializes the PCIe AXI4
slave address translation table using the ecam_addr parameter, and enables
the PCIe configuration interface to read or write data to the configuration
space registers. PF_PCIE_config_space_atr_table_terminate โ The PF_PCIE_config_space_atr_table_terminate() function disables the PCIe
configuration interface in the address translation table and enables the PCIe
Tx/Rx interface for PCIe transactions. PF_PCIE_config_space_read โ The PF_PCIE_config_space_read() function reads the data from configuration
space of PCIe device register, bridge/switch register. PF_PCIE_config_space_write โ The PF_PCIE_config_space_write() function writes the data on configuration
space of PCIe device, bridge/switch register. PF_PCIE_disable_interrupts โ The PF_pcie_disable_interrupts() function disables the local interrupts
on the PCIe RootPort. PF_PCIE_dma_abort โ The PF_PCIE_dma_abort() function aborts a PCIe DMA transfer that is in progress. PF_PCIE_dma_get_transfer_status โ The PF_PCIE_dma_get_transfer_status() function indicates the status of a PCIe
endpoint DMA transfer initiated by a call to the PF_PCIE_dma_write() or
PF_PCIE_dma_read() function. PF_PCIE_dma_init โ The PF_PCIE_dma_init() function initializes the PCIe endpoint DMA from the
PCIe root port host processor. PF_PCIE_dma_read โ The PF_PCIE_dma_read() function initiates PCIe endpoint DMA data transfer
from the PCIe root port host processor. Its parameters specify the source and
destination addresses of the transfer, as well as its size. The PCIe DMA data
transfers for read operations always use the PCIe endpoint memory as the
source and the PCIe root port memory as the destination for the transfer. PF_PCIE_dma_write โ The PF_PCIE_dma_write() function initiates PCIe endpoint DMA data transfer
from the PCIe root port host processor. Its parameters specify the source and
destination addresses of the transfer as well as its size. The PCIe DMA data
transfers for write operations always use the PCIe root port memory as the
source and the PCIe endpoint memory as the destination for the transfer. PF_PCIE_enable_config_space_msi โ The PF_PCIE_enable_config_space_msi() function enables the PCIe root port or
endpoint MSI in the PCIe configuration space. It also sets up the message
address and other data required to generate MSI. PF_PCIE_enable_interrupts โ The PF_pcie_enable_interrupts() function enables local interrupts(MSI, INTx,
DMAx) on the PCIe RootPort. PF_PCIE_enumeration โ The PF_PCIE_enumeration() function enumerates all the components in a PCIe
system, including endpoints, bridges, and switches connected to the system. PF_PCIE_isr โ The PF_PCIE_isr() function is a PCIe root port local interrupt handler. The
PF_PCIE_isr() function is the top level interrupt handler function for the
PolarFire PCIe driver. The user must call the PF_PCIE_isr() function from
the system level interrupt handler assigned to the interrupt triggered by
the PF_PCIE/PCIE_#_INTERRUPT_OUT signal. PF_PCIE_master_atr_table_init โ The PF_PCIE_master_atr_table_init() function sets up the address translation
table for the PCIe AXI4 master. PF_PCIE_set_dma_read_callback โ The PF_PCIE_set_dma_read_callback() function registers the function called by
the PCIe driver when the data has been read. PF_PCIE_set_dma_write_callback โ The PF_pcie_set_dma_write_callback() function registers the function called by
the PCIe driver when the data has been written. PF_PCIE_slave_atr_table_init โ The PF_PCIE_slave_atr_table_init() function sets up the address translation table
for the PCIe AXI4 slave. PF_PCIE_type1_header_read โ The PF_PCIE_type1_header_read() function reads the PCIe type1 (bridge or switch)
configuration space header information. PLIC_ClaimIRQ โ /
/**
The function PLIC_ClaimIRQ() claims the interrupt from the PLIC controller. PLIC_ClearPendingIRQ โ /
/**
PLIC_ClearPendingIRQ(void)
This is only called by the startup hart and only once
Clears any pending interrupts as PLIC can be in unknown state on startup PLIC_CompleteIRQ โ /
/**
The function PLIC_CompleteIRQ() indicates to the PLIC controller the
interrupt is processed and claim is complete. PLIC_DisableIRQ โ / /**
The function PLIC_DisableIRQ() disables the external interrupt for the
interrupt number indicated by the parameter IRQn. PLIC_E51_Maintence_IRQHandler โ PLIC_E51_bus_error_unit_IRQHandler โ PLIC_EnableIRQ โ PLIC_EnableIRQ_for_hart โ /
/**
The function PLIC_EnableIRQ() enables the external interrupt for the
interrupt number indicated by the parameter IRQn. PLIC_External_i2c0_alert_IRQHandler โ PLIC_External_i2c0_main_IRQHandler โ PLIC_GetPriority โ /
/**
The function PLIC_GetPriority() returns the priority for the external
interrupt for the interrupt number indicated by the parameter IRQn. PLIC_Invalid_IRQHandler โ PLIC_SetPriority โ /
/**
The function PLIC_SetPriority() sets the priority for the external interrupt
for the interrupt number indicated by the parameter IRQn. PLIC_SetPriority_Threshold โ /
/** PLIC_U54_1_bus_error_unit_IRQHandler โ PLIC_U54_2_bus_error_unit_IRQHandler โ PLIC_U54_3_bus_error_unit_IRQHandler โ PLIC_U54_4_bus_error_unit_IRQHandler โ PLIC_athena_alarm_IRQHandler โ PLIC_athena_bus_error_IRQHandler โ PLIC_athena_complete_IRQHandler โ PLIC_can1_IRQHandler โ PLIC_ddrc_train_IRQHandler โ PLIC_devrst_IRQHandler โ PLIC_dma_ch0_DONE_IRQHandler โ PLIC_dma_ch0_ERR_IRQHandler โ PLIC_dma_ch1_DONE_IRQHandler โ PLIC_dma_ch1_ERR_IRQHandler โ PLIC_dma_ch2_DONE_IRQHandler โ PLIC_dma_ch2_ERR_IRQHandler โ PLIC_dma_ch3_DONE_IRQHandler โ PLIC_dma_ch3_ERR_IRQHandler โ PLIC_ecc_correct_IRQHandler โ PLIC_ecc_error_IRQHandler โ PLIC_envm_IRQHandler โ PLIC_external_can0_IRQHandler โ PLIC_f2m_0_IRQHandler โ PLIC_f2m_1_IRQHandler โ PLIC_f2m_2_IRQHandler โ PLIC_f2m_3_IRQHandler โ PLIC_f2m_4_IRQHandler โ PLIC_f2m_5_IRQHandler โ PLIC_f2m_6_IRQHandler โ PLIC_f2m_7_IRQHandler โ PLIC_f2m_8_IRQHandler โ PLIC_f2m_9_IRQHandler โ PLIC_f2m_10_IRQHandler โ PLIC_f2m_11_IRQHandler โ PLIC_f2m_12_IRQHandler โ PLIC_f2m_13_IRQHandler โ PLIC_f2m_14_IRQHandler โ PLIC_f2m_15_IRQHandler โ PLIC_f2m_16_IRQHandler โ PLIC_f2m_17_IRQHandler โ PLIC_f2m_18_IRQHandler โ PLIC_f2m_19_IRQHandler โ PLIC_f2m_20_IRQHandler โ PLIC_f2m_21_IRQHandler โ PLIC_f2m_22_IRQHandler โ PLIC_f2m_23_IRQHandler โ PLIC_f2m_24_IRQHandler โ PLIC_f2m_25_IRQHandler โ PLIC_f2m_26_IRQHandler โ PLIC_f2m_27_IRQHandler โ PLIC_f2m_28_IRQHandler โ PLIC_f2m_29_IRQHandler โ PLIC_f2m_30_IRQHandler โ PLIC_f2m_31_IRQHandler โ PLIC_f2m_32_IRQHandler โ PLIC_f2m_33_IRQHandler โ PLIC_f2m_34_IRQHandler โ PLIC_f2m_35_IRQHandler โ PLIC_f2m_36_IRQHandler โ PLIC_f2m_37_IRQHandler โ PLIC_f2m_38_IRQHandler โ PLIC_f2m_39_IRQHandler โ PLIC_f2m_40_IRQHandler โ PLIC_f2m_41_IRQHandler โ PLIC_f2m_42_IRQHandler โ PLIC_f2m_43_IRQHandler โ PLIC_f2m_44_IRQHandler โ PLIC_f2m_45_IRQHandler โ PLIC_f2m_46_IRQHandler โ PLIC_f2m_47_IRQHandler โ PLIC_f2m_48_IRQHandler โ PLIC_f2m_49_IRQHandler โ PLIC_f2m_50_IRQHandler โ PLIC_f2m_51_IRQHandler โ PLIC_f2m_52_IRQHandler โ PLIC_f2m_53_IRQHandler โ PLIC_f2m_54_IRQHandler โ PLIC_f2m_55_IRQHandler โ PLIC_f2m_56_IRQHandler โ PLIC_f2m_57_IRQHandler โ PLIC_f2m_58_IRQHandler โ PLIC_f2m_59_IRQHandler โ PLIC_f2m_60_IRQHandler โ PLIC_f2m_61_IRQHandler โ PLIC_f2m_62_IRQHandler โ PLIC_f2m_63_IRQHandler โ PLIC_g5c_message_IRQHandler โ PLIC_g5c_mss_spi_IRQHandler โ PLIC_gpio0_bit0_or_gpio2_bit13_IRQHandler โ PLIC_gpio0_bit1_or_gpio2_bit13_IRQHandler โ PLIC_gpio0_bit2_or_gpio2_bit13_IRQHandler โ PLIC_gpio0_bit3_or_gpio2_bit13_IRQHandler โ PLIC_gpio0_bit4_or_gpio2_bit13_IRQHandler โ PLIC_gpio0_bit5_or_gpio2_bit13_IRQHandler โ PLIC_gpio0_bit6_or_gpio2_bit13_IRQHandler โ PLIC_gpio0_bit7_or_gpio2_bit13_IRQHandler โ PLIC_gpio0_bit8_or_gpio2_bit13_IRQHandler โ PLIC_gpio0_bit9_or_gpio2_bit13_IRQHandler โ PLIC_gpio0_bit10_or_gpio2_bit13_IRQHandler โ PLIC_gpio0_bit11_or_gpio2_bit13_IRQHandler โ PLIC_gpio0_bit12_or_gpio2_bit13_IRQHandler โ PLIC_gpio0_bit13_or_gpio2_bit13_IRQHandler โ PLIC_gpio0_non_direct_IRQHandler โ PLIC_gpio1_bit0_or_gpio2_bit14_IRQHandler โ PLIC_gpio1_bit1_or_gpio2_bit15_IRQHandler โ PLIC_gpio1_bit2_or_gpio2_bit16_IRQHandler โ PLIC_gpio1_bit3_or_gpio2_bit17_IRQHandler โ PLIC_gpio1_bit4_or_gpio2_bit18_IRQHandler โ PLIC_gpio1_bit5_or_gpio2_bit19_IRQHandler โ PLIC_gpio1_bit6_or_gpio2_bit20_IRQHandler โ PLIC_gpio1_bit7_or_gpio2_bit21_IRQHandler โ PLIC_gpio1_bit8_or_gpio2_bit22_IRQHandler โ PLIC_gpio1_bit9_or_gpio2_bit23_IRQHandler โ PLIC_gpio1_bit10_or_gpio2_bit24_IRQHandler โ PLIC_gpio1_bit11_or_gpio2_bit25_IRQHandler โ PLIC_gpio1_bit12_or_gpio2_bit26_IRQHandler โ PLIC_gpio1_bit13_or_gpio2_bit27_IRQHandler โ PLIC_gpio1_bit14_or_gpio2_bit28_IRQHandler โ PLIC_gpio1_bit15_or_gpio2_bit29_IRQHandler โ PLIC_gpio1_bit16_or_gpio2_bit30_IRQHandler โ PLIC_gpio1_bit17_or_gpio2_bit31_IRQHandler โ PLIC_gpio1_bit18_IRQHandler โ PLIC_gpio1_bit19_IRQHandler โ PLIC_gpio1_bit20_IRQHandler โ PLIC_gpio1_bit21_IRQHandler โ PLIC_gpio1_bit22_IRQHandler โ PLIC_gpio1_bit23_IRQHandler โ PLIC_gpio1_non_direct_IRQHandler โ PLIC_gpio2_non_direct_IRQHandler โ PLIC_i2c0_sus_IRQHandler โ PLIC_i2c1_alert_IRQHandler โ PLIC_i2c1_main_IRQHandler โ PLIC_i2c1_sus_IRQHandler โ PLIC_init โ The function PLIC_init() initializes the PLIC controller and enables the
global external interrupt bit. PLIC_init_on_reset โ /
/**
This function is only called from one hart on startup PLIC_l2_data_corr_IRQHandler โ PLIC_l2_data_uncorr_IRQHandler โ PLIC_l2_metadata_corr_IRQHandler โ PLIC_l2_metadata_uncorr_IRQHandler โ PLIC_mac0_emac_IRQHandler โ PLIC_mac0_int_IRQHandler โ PLIC_mac0_mmsl_IRQHandler โ PLIC_mac0_queue1_IRQHandler โ PLIC_mac0_queue2_IRQHandler โ PLIC_mac0_queue3_IRQHandler โ PLIC_mac1_emac_IRQHandler โ PLIC_mac1_int_IRQHandler โ PLIC_mac1_mmsl_IRQHandler โ PLIC_mac1_queue1_IRQHandler โ PLIC_mac1_queue2_IRQHandler โ PLIC_mac1_queue3_IRQHandler โ PLIC_mmc_main_IRQHandler โ PLIC_mmc_wakeup_IRQHandler โ PLIC_mmuart0_IRQHandler โ PLIC_mmuart1_IRQHandler โ PLIC_mmuart2_IRQHandler โ PLIC_mmuart3_IRQHandler โ PLIC_mmuart4_IRQHandler โ PLIC_pending โ PLIC_qspi_IRQHandler โ PLIC_reserved_104_IRQHandler โ PLIC_rtc_match_IRQHandler โ PLIC_rtc_wakeup_IRQHandler โ PLIC_scb_interrupt_IRQHandler โ PLIC_spi0_IRQHandler โ PLIC_spi1_IRQHandler โ PLIC_timer1_IRQHandler โ PLIC_timer2_IRQHandler โ PLIC_usb_dma_IRQHandler โ PLIC_usb_mc_IRQHandler โ PLIC_usoc_axic_ds_IRQHandler โ PLIC_usoc_axic_us_IRQHandler โ PLIC_usoc_smb_interrupt_IRQHandler โ PLIC_usoc_vc_interrupt_IRQHandler โ PLIC_volt_temp_alarm_IRQHandler โ PLIC_wdog0_mvrp_IRQHandler โ PLIC_wdog0_tout_IRQHandler โ PLIC_wdog1_mvrp_IRQHandler โ PLIC_wdog1_tout_IRQHandler โ PLIC_wdog2_mvrp_IRQHandler โ PLIC_wdog2_tout_IRQHandler โ PLIC_wdog3_mvrp_IRQHandler โ PLIC_wdog3_tout_IRQHandler โ PLIC_wdog4_mvrp_IRQHandler โ PLIC_wdog4_tout_IRQHandler โ SysTick_Config โ Configure system tick
@return SUCCESS or FAIL U54_1_mac0_emac_local_IRQHandler โ U54_1_mac0_int_local_IRQHandler โ U54_1_mac0_mmsl_local_IRQHandler โ U54_1_mac0_queue1_local_IRQHandler โ U54_1_mac0_queue2_local_IRQHandler โ U54_1_mac0_queue3_local_IRQHandler โ U54_1_mmuart1_local_IRQHandler โ U54_1_software_IRQHandler โ U54_1_sysTick_IRQHandler โ U54_1_wdog_mvrp_local_IRQHandler โ U54_1_wdog_tout_local_IRQHandler โ U54_2_mac0_emac_local_IRQHandler โ U54_2_mac0_int_local_IRQHandler โ U54_2_mac0_mmsl_local_IRQHandler โ U54_2_mac0_queue1_local_IRQHandler โ U54_2_mac0_queue2_local_IRQHandler โ U54_2_mac0_queue3_local_IRQHandler โ U54_2_mmuart2_local_IRQHandler โ U54_2_software_IRQHandler โ U54_2_sysTick_IRQHandler โ U54_2_wdog_mvrp_local_IRQHandler โ U54_2_wdog_tout_local_IRQHandler โ U54_3_mac1_emac_local_IRQHandler โ U54_3_mac1_int_local_IRQHandler โ U54_3_mac1_mmsl_local_IRQHandler โ U54_3_mac1_queue1_local_IRQHandler โ U54_3_mac1_queue2_local_IRQHandler โ U54_3_mac1_queue3_local_IRQHandler โ U54_3_mmuart3_local_IRQHandler โ U54_3_software_IRQHandler โ U54_3_sysTick_IRQHandler โ U54_3_wdog_mvrp_local_IRQHandler โ U54_3_wdog_tout_local_IRQHandler โ U54_4_mac1_emac_local_IRQHandler โ U54_4_mac1_int_local_IRQHandler โ U54_4_mac1_mmsl_local_IRQHandler โ U54_4_mac1_queue1_local_IRQHandler โ U54_4_mac1_queue2_local_IRQHandler โ U54_4_mac1_queue3_local_IRQHandler โ U54_4_mmuart4_local_IRQHandler โ U54_4_software_IRQHandler โ U54_4_sysTick_IRQHandler โ U54_4_wdog_mvrp_local_IRQHandler โ U54_4_wdog_tout_local_IRQHandler โ U54_f2m_0_local_IRQHandler โ U54_f2m_1_local_IRQHandler โ U54_f2m_2_local_IRQHandler โ U54_f2m_3_local_IRQHandler โ U54_f2m_4_local_IRQHandler โ U54_f2m_5_local_IRQHandler โ U54_f2m_6_local_IRQHandler โ U54_f2m_7_local_IRQHandler โ U54_f2m_8_local_IRQHandler โ U54_f2m_9_local_IRQHandler โ U54_f2m_10_local_IRQHandler โ U54_f2m_11_local_IRQHandler โ U54_f2m_12_local_IRQHandler โ U54_f2m_13_local_IRQHandler โ U54_f2m_14_local_IRQHandler โ U54_f2m_15_local_IRQHandler โ U54_f2m_16_local_IRQHandler โ U54_f2m_17_local_IRQHandler โ U54_f2m_18_local_IRQHandler โ U54_f2m_19_local_IRQHandler โ U54_f2m_20_local_IRQHandler โ U54_f2m_21_local_IRQHandler โ U54_f2m_22_local_IRQHandler โ U54_f2m_23_local_IRQHandler โ U54_f2m_24_local_IRQHandler โ U54_f2m_25_local_IRQHandler โ U54_f2m_26_local_IRQHandler โ U54_f2m_27_local_IRQHandler โ U54_f2m_28_local_IRQHandler โ U54_f2m_29_local_IRQHandler โ U54_f2m_30_local_IRQHandler โ U54_f2m_31_local_IRQHandler โ U54_spare_0_local_IRQHandler โ U54_spare_1_local_IRQHandler โ U54_spare_2_local_IRQHandler โ U54_spare_3_local_IRQHandler โ U54_spare_4_local_IRQHandler โ U54_spare_5_local_IRQHandler โ U54_spare_6_local_IRQHandler โ __disable_all_irqs โ __disable_irq โ __disable_local_irq โ __enable_irq โ __enable_local_irq โ check_num_scratch_ways โ //**
The check_num_scratch_ways() function is used tocheck that the linker script
has not allocated more ways than has been allocated by the MSS Configurator. clear_bootup_cache_ways โ //**
The clear_bootup_cache_ways() sets up seg regs clear_soft_interrupt โ Clears a synchronous software interrupt by clearing the MSIP register. config_16_copy โ config_64_copy โ config_copy โ config_l2_cache โ //**
The config_l2_cache() function is used to setup scratchpad. It will be used by
bootloader. e.g. Hart Software Services (HSS)
This code should only be executed from E51 to be functional.
Configure the L2 cache memory: copy_section โ count_section โ ddr_pll_config โ //**
ddr_pll_config() configure DDR PLL ddr_pll_config_scb_turn_off โ //**
ddr_pll_config_scb_turn_off() Puts PLL in reset ddr_pll_lock_scb โ //**
ddr_pll_lock_scb() Checks if PLL locked ddr_pvt_calibration โ //**
ddr_pvt_calibration() calibrates DDR I/O using the hardware function ddr_pvt_recalibration โ //**
ddr_pvt_recalibration() recalibrates DDR I/O using the hardware function ddr_read_write_fn โ //**
The ddr_read_write_fn function is used to write/read test patterns to the DDR ddr_state_machine โ //**
The ddr_state_machine() function runs a state machine which initializes and
monitors the DDR disable_branch_prediction โ disable_interrupts โ disable_m2f_int_output โ disable_systick โ Disable system tick interrupt e51 โ ecam_address_calc โ enable_branch_prediction โ enable_interrupts โ enable_m2f_int_output โ end_l2_scratchpad_address โ //**
The end_l2_scratchpad_address() function is used to return the end address of
the initialised scratchpad. It is used in the startup code. execute_ddr_pattern โ //** exit_simulation โ fabric_sd_emmc_demux_address โ / /**
fabric_sd_emmc_demux_address() fabric_sd_emmc_demux_present โ / /**
fabric_sd_emmc_demux_present() fill_cache_new_seg_address โ //**
The fill_cache_new_seg_address() flag_mss_pll_lock_error โ flush_l2_cache โ //**
Flushes the L2 cache get_program_counter โ get_stack_pointer โ get_tp_reg โ gpio_toggle_test โ / /**
The gpio_toggle_test(void)() handle_local_beu_interrupt โ //**
The handle_local_beu_interrupt() function is used to handle local interrupts
generated by the Bus Error Unit (BEU) handle_m_ext_interrupt โ handle_m_soft_interrupt โ handle_m_timer_interrupt โ hart_id init_bus_error_unit โ //**
The init_bus_error_unit() function is used to setup the Bus Error Unit (BEU)
for all the harts used in the system. Define the defines
(LIBERO_SETTING_BEU_ENABLE_HART0 etc) in mss_sw_config.h if you want to use
non default values.
Example:
@code
when all mem init, call the setup function
init_bus_error_unit();
@endcode init_ddr โ init_mem_protection_unit โ init_memory โ init_pmp โ init_usb_dma_upper_address Set the upper address bits of the address of the USB DMA last_address last_linked_address load_ddr_pattern โ //** load_virtual_rom โ main_first_hart โ main_first_hart_app โ main_other_hart โ memfill โ memset โ mpfs_hal_ddr_selfrefresh_status โ //**
The mpfs_hal_ddr_selfrefresh_status() mpfs_hal_turn_ddr_selfrefresh_off โ //**
The mpfs_hal_turn_ddr_selfrefresh_off() mpfs_hal_turn_ddr_selfrefresh_on โ //**
The mpfs_hal_turn_ddr_selfrefresh_on(void) flushes cache and turns on self
refresh. When DDR is in self refresh mode, less power is consumed by the
memory. Data is retained. You can not write or read from the DDR when
self-refresh is on. mpu_configure โ mss_config_clk_rst โ //**
This function is used to turn on or off a peripheral. If contexts have been
configured, these will be checked to see if peripheral should be controlled
from a particular context. mss_current_axi_freq โ mss_current_mss_freq โ mss_current_pclk_freq โ mss_disable_fabric โ //**
This function is used to turn on the fabric enable mss_does_xml_ver_support_switch โ / /**
mss_does_xml_ver_support_switch()
Sets bank 2 and 4 voltages, with Values coming from Libero mss_enable_fabric โ //**
This function is used to turn on the fabric enable mss_freq_scaling โ mss_get_apb_bus_cr โ //**
This function is used to get the apb_bus_cr register value mss_get_gpio_interrupt_fab_cr โ / /**
This function is used to get the gpio_interrupt_fab_cr register value mss_io_default_setting โ / /**
mss_io_default_setting()
This helper function may be useful, e.g. print a message on start-up
explaining configuration. mss_is_alternate_io_configured โ / /**
mss_is_alternate_io_configured() mss_is_alternate_io_setting_emmc โ / /**
mss_is_alternate_io_setting_emmc() mss_is_alternate_io_setting_sd โ / /**
mss_is_alternate_io_setting_sd() mss_pll_config โ //**
mss_pll_config() mss_set_apb_bus_cr โ //**
This function is used to set the apb_bus_cr register value mss_set_gpio_interrupt_fab_cr โ / /**
This function is used to set the apb_bus_cr register value mss_turn_off_unused_ram_clks โ //**
This function is used to turn off RAM associated with peripherals that are
marked as unused in the MSS Configurator. mssio_setup โ / /**
The int32_t mssio_setup(void)() mvrp_u54_local_IRQHandler_10 โ my_num_dcache_ways โ num_cache_ways โ //**
Returns the number of cache ways pmp_configure โ pmp_master_configs โ pre_configure_sgmii_and_ddr_pll_via_scb โ //**
pre_configure_sgmii_and_ddr_pll_via_scb() raise_soft_interrupt โ Raises a synchronous software interrupt by writing into the MSIP register. readmcycle โ readmtime โ reset_m2f โ reset_mtime โ call once at startup
@return restore_interrupts โ set_RTC_divisor โ //**
set_RTC_divisor() Sets the RTC divisor based on values from Libero
It is assumed the RTC clock is set to 1MHz
Example:
@code set_bank2_and_bank4_volts โ / /**
set_bank2_and_bank4_volts()
Sets bank 2 and 4 voltages, with Values coming from Libero set_usb_dma_upper_address setup_ddr_segments โ //**
The setup_ddr_segments() sets up seg regs sgmii_mux_config_via_scb โ //**
sgmii_mux_config_via_scb() configures mux for SGMii sgmii_off_mode โ //**
sgmii_off_mode() called in sgmii channels are not being used. sgmii_pll_config_scb โ //**
sgmii_pll_config_scb() configure sgmii PLL sgmii_pll_lock_scb โ //**
sgmii_pll_lock_scb() Checks if PLL is locked sgmii_setup โ //**
sgmii_setup() sets up the SGMII using settings from Libero sleep_cycles โ sleep_ms โ switch_demux_using_fabric_ip โ / /**
switch_demux_using_fabric_ip()
This is a function used to switch external mux.
It requires fpga switch IP in the fabric. This comes with reference icicle
kit design.
You will need to create your own or copy when creating your own fpga design
along with an external mux in your board design if you wish to use SD/eMMC
muxing in your hardware design. switch_mssio_config โ / /**
switch_mssio_config()
switches as instructed SD/eMMC test_ddr โ //** turn_off_fpu โ turn_off_power_to_parked_harts_ram โ turn_on_fpu โ turn_on_power_to_hart_ram โ u54_1 โ u54_2 โ u54_3 โ u54_4 โ u54_single_hart โ zero_section โ BEU_Type BEU_Types BEU_event_cause CAN_DEVICE CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_BLOCKID_BANK_CTRL_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_NV_MAP_BANK_CTRL_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_PERIPH_BANK_CTRL_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_V_MAP_BANK_CTRL_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_BLOCKID_CFM_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_NV_MAP_CFM_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_PERIPH_CFM_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_V_MAP_CFM_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_NV_MAP_DDR_PHY_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_PERIPH_DDR_PHY_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_V_MAP_DDR_PHY_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_BLOCKID_DECODER_DRIVER_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_NV_MAP_DECODER_DRIVER_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_PERIPH_DECODER_DRIVER_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_V_MAP_DECODER_DRIVER_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_BLOCKID_DECODER_IO_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_NV_MAP_DECODER_IO_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_PERIPH_DECODER_IO_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_V_MAP_DECODER_IO_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_BLOCKID_DECODER_ODT_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_NV_MAP_DECODER_ODT_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_PERIPH_DECODER_ODT_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_V_MAP_DECODER_ODT_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_BLOCKID_IOCALIB_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_NV_MAP_IOCALIB_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_PERIPH_IOCALIB_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_V_MAP_IOCALIB_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_BLOCKID_IOSCB_PLL_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_NV_MAP_IOSCB_PLL_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_PERIPH_IOSCB_PLL_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_V_MAP_IOSCB_PLL_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_BLOCKID_MAIN_PLL_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_NV_MAP_MAIN_PLL_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_PERIPH_MAIN_PLL_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_V_MAP_MAIN_PLL_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_NV_MAP_TIP_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_PERIPH_TIP_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_V_MAP_TIP_TypeDef CFM CLINT_Type DDR_ACCESS_SIZE DDR_ACCESS_SIZE_ DDR_FILL_TYPE DDR_FILL_TYPE_ DDR_MEMORY_ACCESS DDR_MEMORY_ACCESS_ DDR_SM_STATES //**
//** DDR_SM_STATES_ //** DDR_SS_COMMAND //**
//** DDR_SS_COMMAND_ //** DDR_SS_STATUS //**
//** DDR_SS_STATUS_ //** DDR_TRAINING_SM //**
//** DDR_TRAINING_SM_ //** DDR_TYPE //**
//** DDR_TYPE_ //** DDR_USER_GET_COMMANDS_t //** DDR_USER_SET_COMMANDS_t //** HLS_DATA IOMUX_CONFIG \brief IOMUX configuration IOSCB_BANKCONT_DDR_STRUCT \brief dll sgmii SCB regs IOSCB_BANK_CNTL_SGMII_STRUCT \brief bank control sgmii SCB regs IOSCB_DLL_SGMII_STRUCT \brief dll sgmii SCB regs IOSCB_GEM_X_LO_STRUCT \brief GEM_A_LO GEM_B_LO IOSCB_SGMIIPHY_LANE01_STRUCT \brief gmiiphy_lanexx MSSIO_BANK2_CONFIG \brief MSS IO Bank 2 configuration MSSIO_BANK4_CONFIG \brief MSS IO Bank 4 configuration MSSIO_BANK_CONFIG \brief Bank 2 and 4 voltage settings MSSIO_CONFIG_OPTION MSSIO_CONFIG_OPTION_ MSS_FREQ_SCALING_OPTION MSS_FREQ_SCALING_OPTION_ MSS_IO_OPTIONS MSS_IO_OPTIONS_ MTC_ADD_PATTERN MTC_ADD_PATTERN_ MTC_PATTERN //**
//** MTC_PATTERN_ //** PART_TYPE PART_TYPE_ PATTERN_TEST_PARAMS PCAN_DEVICE PERIPH_RESET_STATE //**
//** PERIPH_RESET_STATE_ //** PLIC_IRQn_Type REG_LOAD_METHOD REG_LOAD_METHOD_ RTC_CLK_SOURCE RTC_CLK_SOURCE_ SEG_SETUP //**
//** SEG_SETUP_ //** SGMII_TRAINING_SM //**
//** SGMII_TRAINING_SM_ //** SWEEP_STATES //**
//** SWEEP_STATES_ //** USR_STATUS_OPTION_t //** WFI_SM WFI_SM_ __cfm_channel_mode //**
The cfm_channel_mode enumeration is used to specify the channel mode. __cfm_count_id //**
The __cfm_count_id_t enumeration is used to identify the channel used. __cfm_error_id_t __gpio_apb_width_t Possible width of the APB bus __gpio_id_t The gpio_id_t enumeration is used to identify GPIOs as part of the
parameter to functions: __mss_mac_frag_size_t //**
This enumeration indicates the pre-emption minimum fragment size which
also determines the minimum number of bytes which the pMAC sends before
pre-emption is allowed. __mss_mac_hash_mode_t //**
This enumeration indicates hash matching modes for accepting received frames.
This value is used with the MSS_MAC_set_hash_mode() and
MSS_MAC_get_hash_mode() functions. __mss_mac_oss_mode_t //**
This enumeration indicates sync time stamp adjust modes to use for One Step
Synce operation (OSS). This value is used with the
MSS_MAC_set_TSU_oss_mode() and MSS_MAC_get_TSU_oss_mode() functions. __mss_mac_phy_reset_t //**
MAC PHY Reset type __mss_mac_rx_int_ctrl_t //**
MAC RX interrupt control __mss_mac_speed_mode_t //**
MAC interface speed mode selector __mss_mac_speed_t //**
MAC interface speed indicator __mss_mac_stat_t //**
This enumeration is used for accessing Transmit and Receive statistics. The
statistic which is desired to be read is passed to MSS_MAC_read_stat() . The
width of the returned statistic value is indicated in the comment against the
statistic. __mss_mac_tsu_addr_t //**
This enumeration indicates which direction unicast packet is being
referenced. This is used with the MSS_MAC_set_TSU_unicast_addr() and
MSS_MAC_get_TSU_unicast_addr() functions. __mss_mac_tsu_mode_t //**
This enumeration indicates DMA descriptor time stamp insertion modes. This
indicates which types of packets should have their IEEE 1588 timestamps
recorded in the transmit or receive descriptors. __mss_timer_mode This enumeration selects between the two possible timer modes of operation:
Periodic and One-shot mode. It is used as an argument to the MSS_TIM1_init(),
MSS_TIM2_init(), and MSS_TIM64_init() function. __pdma_channel_id __pdma_error_id_t The mss_pdma_error_id_t enumeration is used to specify the error status from
MSS PDMA transfer / transaction functions. addr_t cfmChannelMode cfm_channel_mode //**
The cfm_channel_mode enumeration is used to specify the channel mode.
//**
The cfm_channel_mode enumeration is used to specify the channel mode. cfm_count_id_t //**
The __cfm_count_id_t enumeration is used to identify the channel used.
//**
The __cfm_count_id_t enumeration is used to identify the channel used. cfm_error_id_t gpio_apb_width_t Possible width of the APB bus
Possible width of the APB bus gpio_id_t The gpio_id_t enumeration is used to identify GPIOs as part of the
parameter to functions: gpio_inout_state Possible states for GPIO configured as INOUT gpio_inout_state_t Possible states for GPIO configured as INOUT
Possible states for GPIO configured as INOUT gpio_instance_t Structure instance holding all data regarding the CoreGPIO int_fast8_t int_fast16_t int_fast32_t int_fast64_t int_least8_t int_least16_t int_least32_t int_least64_t intmax_t mss_axisw_cmd_t mss_axisw_mchan_t mss_axisw_mport_t //** mss_axisw_rate_t mss_can_buffer_status mss_can_command_reg mss_can_config_reg mss_can_error_status mss_can_filterobject mss_can_instance_t The structure mss_can_instance_t is used by the driver to manage the
configuration and operation of each MSS CAN peripheral. The instance content
should only be accessed by using the respective API functions. mss_can_int_enable mss_can_int_status mss_can_mode The mss_can_mode_t enumeration specifies the possible operating modes of CAN
controller. The meaning of the constants is as described below mss_can_mode_t The mss_can_mode_t enumeration specifies the possible operating modes of CAN
controller. The meaning of the constants is as described below mss_can_msgobject mss_can_rxmsgobject mss_can_txmsgobject mss_ddr_calibration //**
Calibration settings derived during write training mss_ddr_diag //** mss_ddr_vref //** mss_ddr_write_calibration //** mss_gpio_byte_num The mss_gpio_byte_num_t enumeration specifies the set of the eight consecutive
GPIO ports that are to be configured. It is passed as an argument to the
MSS_GPIO_config_byte() function. mss_gpio_byte_num_t The mss_gpio_byte_num_t enumeration specifies the set of the eight consecutive
GPIO ports that are to be configured. It is passed as an argument to the
MSS_GPIO_config_byte() function.
The mss_gpio_byte_num_t enumeration specifies the set of the eight consecutive
GPIO ports that are to be configured. It is passed as an argument to the
MSS_GPIO_config_byte() function. mss_gpio_id The mss_gpio_id_t enumeration identifies individual GPIO ports as an
argument to the following functions: mss_gpio_id_t The mss_gpio_id_t enumeration identifies individual GPIO ports as an
argument to the following functions: mss_gpio_inout_state The mss_gpio_inout_state_t enumeration specifies the output state of an INOUT
GPIO. It is passed as an argument to the MSS_GPIO_drive_inout() function. mss_gpio_inout_state_t The mss_gpio_inout_state_t enumeration specifies the output state of an INOUT
GPIO. It is passed as an argument to the MSS_GPIO_drive_inout() function.
The mss_gpio_inout_state_t enumeration specifies the output state of an INOUT
GPIO. It is passed as an argument to the MSS_GPIO_drive_inout() function. mss_i2c_clock_divider The mss_i2c_clock_divider_t type is used to specify the divider to be applied
to the MSS I2C PCLK or BCLK signal in order to generate the I2C clock.
The MSS_I2C_BCLK_DIV_8 value selects a clock frequency based on division of
BCLK, all other values select a clock frequency based on division of PCLK. mss_i2c_clock_divider_t The mss_i2c_clock_divider_t type is used to specify the divider to be applied
to the MSS I2C PCLK or BCLK signal in order to generate the I2C clock.
The MSS_I2C_BCLK_DIV_8 value selects a clock frequency based on division of
BCLK, all other values select a clock frequency based on division of PCLK.
The mss_i2c_clock_divider_t type is used to specify the divider to be applied
to the MSS I2C PCLK or BCLK signal in order to generate the I2C clock.
The MSS_I2C_BCLK_DIV_8 value selects a clock frequency based on division of
BCLK, all other values select a clock frequency based on division of PCLK. mss_i2c_instance_t mss_i2c_instance_t mss_i2c_slave_handler_ret The mss_i2c_slave_handler_ret_t type is used by slave write handler functions
to indicate whether or not the received data buffer should be released. mss_i2c_slave_handler_ret_t The mss_i2c_slave_handler_ret_t type is used by slave write handler functions
to indicate whether or not the received data buffer should be released.
The mss_i2c_slave_handler_ret_t type is used by slave write handler functions
to indicate whether or not the received data buffer should be released. mss_i2c_slave_wr_handler_t Slave write handler functions prototype. mss_i2c_status The mss_i2c_status_t type is used to report the status of I2C transactions. mss_i2c_status_t The mss_i2c_status_t type is used to report the status of I2C transactions.
The mss_i2c_status_t type is used to report the status of I2C transactions. mss_i2c_transfer_completion_t Transfer completion call back handler functions prototype.
This defines the function prototype that must be followed by MSS I2C master
and slave transfer completion handler functions. These functions are registered
with the MSS I2C driver through the MSS_I2C_register_transfer_completion_handler()
function. mss_lpddr4_dq_calibration //** mss_mac_cfg_t //**
PolarFire SoC MSS Ethernet MAC Configuration Structure. mss_mac_frag_size_t //**
This enumeration indicates the pre-emption minimum fragment size which
also determines the minimum number of bytes which the pMAC sends before
pre-emption is allowed. mss_mac_hash_mode_t //**
This enumeration indicates hash matching modes for accepting received frames.
This value is used with the MSS_MAC_set_hash_mode() and
MSS_MAC_get_hash_mode() functions.
//**
This enumeration indicates hash matching modes for accepting received frames.
This value is used with the MSS_MAC_set_hash_mode() and
MSS_MAC_get_hash_mode() functions. mss_mac_instance_t //**
G5SoC Ethernet MAC instance
A local record of this type will be created and maintained by the driver for
each pMAC and eMAC. mss_mac_mmsl_config_t //**
Media Merge Sublayer configuration structure. mss_mac_mmsl_stats_t //**
Media Merge Sublayer statistics structure. mss_mac_oss_mode_t //**
This enumeration indicates sync time stamp adjust modes to use for One Step
Synce operation (OSS). This value is used with the
MSS_MAC_set_TSU_oss_mode() and MSS_MAC_get_TSU_oss_mode() functions.
//**
This enumeration indicates sync time stamp adjust modes to use for One Step
Synce operation (OSS). This value is used with the
MSS_MAC_set_TSU_oss_mode() and MSS_MAC_get_TSU_oss_mode() functions. mss_mac_phy_autonegotiate_t //**
Pointer to PHY autonegotiate function mss_mac_phy_extended_read_t //**
Pointer to PHY extended read function. mss_mac_phy_extended_write_t //**
Pointer to PHY extended write function mss_mac_phy_get_link_status_t //**
Pointer to PHY get link status function mss_mac_phy_init_t //**
Pointer to PHY init function mss_mac_phy_reset_t //**
MAC PHY Reset type mss_mac_phy_set_speed_t //**
Pointer to PHY set link speed function mss_mac_queue_t //**
Per queue specific info for device management structure. mss_mac_receive_callback_t //**
Receive callback function. mss_mac_rx_desc_t //**
Receive DMA descriptor. mss_mac_rx_int_ctrl_t //**
MAC RX interrupt control mss_mac_speed_mode_t //**
MAC interface speed mode selector mss_mac_speed_t //**
MAC interface speed indicator mss_mac_stat_t //**
This enumeration is used for accessing Transmit and Receive statistics. The
statistic which is desired to be read is passed to MSS_MAC_read_stat() . The
width of the returned statistic value is indicated in the comment against the
statistic. mss_mac_transmit_callback_t //**
Transmit callback function. mss_mac_tsu_addr_t //**
This enumeration indicates which direction unicast packet is being
referenced. This is used with the MSS_MAC_set_TSU_unicast_addr() and
MSS_MAC_get_TSU_unicast_addr() functions.
//**
This enumeration indicates which direction unicast packet is being
referenced. This is used with the MSS_MAC_set_TSU_unicast_addr() and
MSS_MAC_get_TSU_unicast_addr() functions. mss_mac_tsu_config_t //**
TSU configuration structure. mss_mac_tsu_mode_t //**
This enumeration indicates DMA descriptor time stamp insertion modes. This
indicates which types of packets should have their IEEE 1588 timestamps
recorded in the transmit or receive descriptors. mss_mac_tsu_time_t //**
TSU timer time value. mss_mac_tx_desc_t //**
Transmit DMA descriptor. mss_mac_tx_pkt_info_t //**
Multi packet transmit structure mss_mac_type_1_filter_t //**
Type 1 filter structure. mss_mac_type_2_compare_t //**
Type 2 filter comparer structures. mss_mac_type_2_filter_t //**
Type 2 filter structure. mss_mmc_cfg_t The mss_mmc_cfg_t type provides the prototype for the configuration values of
the MSS eMMC SD driver. The application need to create a record of this type
to hold the configuration of the eMMC/SD/SDIO. The MSS_MMC_init() function
initializes the MSS eMMC SD using this structure. A pointer to an initialized
of this structure should be passed as the first parameter to the
MSS_MMC_init() function. mss_mmc_handler_t This type definition specifies the prototype of a function that can be
registered with this driver as a eMMC/SD transfer completion handler function
through a call to MSS_MMC_set_handler(). The eMMC/SD transfer completion
handler will be called by the driver when an eMMC/SD transfer completes. The
PolarFire SoC MSS eMMC SD driver passes the outcome of the transfer to the
completion handler in the form of a status parameter indicating if the
transfer is successful or the type of error that occurred during the transfer. mss_mmc_status The mss_mmc_status_t type is used to indicate the return status of the eMMC/SD
data transfer. A variable of this type is returned by the MSS_MMC_init(),
MSS_MMC_single_block_write(), MSS_MMC_single_block_read(), MSS_MMC_sdma_write(),
MSS_MMC_sdma_read(), MSS_MMC_adma2_write(), MSS_MMC_adma2_read(),
MSS_MMC_cq_init(), MSS_MMC_cq_write(), MSS_MMC_cq_read(),
MSS_MMC_sdio_single_block_read(), MSS_MMC_sdio_single_block_write() functions. mss_mmc_status_t The mss_mmc_status_t type is used to indicate the return status of the eMMC/SD
data transfer. A variable of this type is returned by the MSS_MMC_init(),
MSS_MMC_single_block_write(), MSS_MMC_single_block_read(), MSS_MMC_sdma_write(),
MSS_MMC_sdma_read(), MSS_MMC_adma2_write(), MSS_MMC_adma2_read(),
MSS_MMC_cq_init(), MSS_MMC_cq_write(), MSS_MMC_cq_read(),
MSS_MMC_sdio_single_block_read(), MSS_MMC_sdio_single_block_write() functions.
The mss_mmc_status_t type is used to indicate the return status of the eMMC/SD
data transfer. A variable of this type is returned by the MSS_MMC_init(),
MSS_MMC_single_block_write(), MSS_MMC_single_block_read(), MSS_MMC_sdma_write(),
MSS_MMC_sdma_read(), MSS_MMC_adma2_write(), MSS_MMC_adma2_read(),
MSS_MMC_cq_init(), MSS_MMC_cq_write(), MSS_MMC_cq_read(),
MSS_MMC_sdio_single_block_read(), MSS_MMC_sdio_single_block_write() functions. mss_mpu_addrm_t mss_mpu_mport_t mss_mpu_pmp_region_t mss_pdma_channel_config_t The mss_pdma_channel_config_t structure is used to configure the desired
Platform DMA channel. PDMA channel configuration includes configuration of
source, destination address and the number of bytes for the DMA transfer.
Single DMA transfer may require multiple DMA transactions, the size and
alignment of the individual DMA transaction can be forced. The PDMA can be
programmed to automatically repeat a transfer.
The MSS PDMA have two interrupts per channel, transfer complete interrupt and
transfer error interrupt. The two interrupts can be enabled by configuring
respective bits in the mss_pdma_channel_config_t structure. mss_pdma_channel_id_t mss_pdma_error_id_t The mss_pdma_error_id_t enumeration is used to specify the error status from
MSS PDMA transfer / transaction functions.
The mss_pdma_error_id_t enumeration is used to specify the error status from
MSS PDMA transfer / transaction functions. mss_pdma_int_handler_t mss_pdma_t The mss_pdma_t structure will describe the functionality of the memory mapped
registers in the Platform DMA Engine. mss_peripherals mss_peripherals_ mss_qspi_clk_div //**
These values are used to program the spi_mode parameter of the configuration
structure of this driver. For example:
@code
qspi_config.clk_div = MSS_QSPI_CLK_DIV_2;
MSS_QSPI_configure(&qspi_config);
@endcode mss_qspi_clk_div_t //**
These values are used to program the spi_mode parameter of the configuration
structure of this driver. For example:
@code
qspi_config.clk_div = MSS_QSPI_CLK_DIV_2;
MSS_QSPI_configure(&qspi_config);
@endcode mss_qspi_config_t //**
This is the structure definition for the MSS QSPI configuration instance. It
defines the configuration data that the application exchanges with the driver. mss_qspi_io_format //**
These values are used to program the io_format parameter of the configuration
structure of this driver, as shown below:
@code
qspi_config.io_format = MSS_QSPI_QUAD_FULL;
MSS_QSPI_configure(&qspi_config);
@endcode mss_qspi_io_format_t //**
These values are used to program the io_format parameter of the configuration
structure of this driver, as shown below:
@code
qspi_config.io_format = MSS_QSPI_QUAD_FULL;
MSS_QSPI_configure(&qspi_config);
@endcode mss_qspi_protocol_mode //**
These values are used to program the spi_mode parameter of the configuration
structure of this driver. For example:
@code
qspi_config.spi_mode = MSS_QSPI_MODE0;
MSS_QSPI_configure(&qspi_config);
@endcode mss_qspi_protocol_mode_t //**
These values are used to program the spi_mode parameter of the configuration
structure of this driver. For example:
@code
qspi_config.spi_mode = MSS_QSPI_MODE0;
MSS_QSPI_configure(&qspi_config);
@endcode mss_qspi_status_handler_t //**
This prototype defines the function prototype that must be followed by MSS QSPI
status handler functions. This function is registered with the MSS QSPI driver
through a call to the MSS_QSPI_set_status_handler() function. mss_sys_service_handler_t Callback function handler
The callback handler is used by the application to indicate the user about
the event of interrupt when the driver is configured to execute the system
services in interrupt mode.
The callback function handler is is registered to the MSS system service
driver through the call to MSS_SYS_select_service_mode() function.
The actual name of callback function handler is not important. User can select
any name. mss_sysreg_t TOP LEVEL REGISTER STRUCTURE*************************** mss_timer_mode_t This enumeration selects between the two possible timer modes of operation:
Periodic and One-shot mode. It is used as an argument to the MSS_TIM1_init(),
MSS_TIM2_init(), and MSS_TIM64_init() function. mss_uart_endian_t / /**
Tx / Rx endianess.
This enumeration specifies the MSB first or LSB first for MSS UART transmitter
and receiver. The parameter of this type shall be passed in
MSS_UART_set_rx_endian()and MSS_UART_set_tx_endian() functions. mss_uart_filter_length_t / /**
Glitch filter length.
This enumeration specifies the glitch filter length. The function
MSS_UART_set_filter_length() accepts the parameter of this type. mss_uart_instance_t / /**
This is the type definition for MSS UART instance. You need to create and
maintain a record of this type. This holds all data regarding the MSS UART
instance. mss_uart_irq_handler_t / /**
This typedef specifies the function prototype for MSS UART interrupt handlers.
All interrupt handlers registered with the MSS UART driver must be of this type.
The interrupt handlers are registered with the driver through the
MSS_UART_set_rx_handler(), MSS_UART_set_tx_handler(),
MSS_UART_set_rxstatus_handler(), and MSS_UART_set_modemstatus_handler()
functions.
The this_uart parameter is a pointer to the MMUART instance to
associate with the handler function. mss_uart_irq_t / /**
This typedef specifies the irq_mask parameter for the MSS_UART_enable_irq()
and MSS_UART_disable_irq() functions. The driver defines a set of bit masks
that are used to build the value of the irq_mask parameter. A bitwise OR of
these bit masks is used to enable or disable multiple MSS MMUART interrupts. mss_uart_loopback_t / /**
This enumeration specifies the loopback configuration of the UART. It provides
the allowed values for the MSS_UART_set_loopback() functionโs loopback
parameter. Use MSS_UART_LOCAL_LOOPBACK_ON to set up the UART to locally
loopback its Tx and Rx lines. Use MSS_UART_REMOTE_LOOPBACK_ON to set up the
UART in remote loopback mode. mss_uart_num_t mss_uart_ready_mode_t / /**
TXRDY and RXRDY mode.
This enumeration specifies the TXRDY and RXRDY signal modes. The function
MSS_UART_set_ready_mode() accepts the parameter of this type. mss_uart_rx_trig_level_t / /**
This enumeration specifies the receiver FIFO trigger level. This is the number
of bytes that must be received before the UART generates a receive data
available interrupt. It provides the allowed values for the
MSS_UART_set_rx_handler() function trigger_level parameter. mss_uart_rzi_polarity_t / /**
IrDA input / output polarity.
This enumeration specifies the RZI modem polarity for input and output signals.
This is passed as parameters in MSS_UART_irda_init() function. mss_uart_rzi_pulsewidth_t / /**
IrDA input / output pulse width.
This enumeration specifies the RZI modem pulse width for input and output
signals. This is passed as parameters in MSS_UART_irda_init() function. mss_uart_usart_mode_t / /**
USART mode of operation.
This enumeration specifies the mode of operation of MSS UART when operating
as USART. The function MSS_UART_set_usart_mode() accepts the parameter of this
type. mss_usb_core_mode_t mss_usb_device_role mss_usb_device_role_t mss_usb_device_speed_t mss_usb_dma_burst_mode_t mss_usb_dma_channel_t mss_usb_dma_dir_t mss_usb_dma_mode_t mss_usb_ep_num_t mss_usb_ep_state_t mss_usb_pkt_type mss_usb_pkt_type_t mss_usb_state_t Types which are used internally by the driver. mss_usb_vbus_level_t mss_usb_xfr_type_t Types which can be used by LDL layer or the application. mss_usbd_cep_state_t mss_usbh_class_cb_t The mss_usbh_class_cb_t provides the prototype of the structure that must be
implemented by the USBH-Class driver to provide the call-back functions which
will be called by the USBH driver to communicate events on the target device. mss_usbh_tdev_info_t The mss_usbh_tdev_info_t type provides the prototype for the detailed
information of the attached device. Some of the parameters are only applicable
when multi-point support is enabled on MSS USB. Multi-point support is
currently not enabled in the USBH driver. mss_usbh_user_cb_t The mss_usbh_user_cb_t provides the prototype of the structure that must be
implemented by the application to provide the call-back functions which will
be called by the USBH driver to communicate events on the target device. These
call-back functions can be used by the application to know the USBH driver
state and information about the attached device from the USBH driver.
These events are not specific to any USB class. mss_watchdog_config_t //**
The mss_watchdog_config_t type is for the watchdog configuration structure.
This type is used as a parameter for the MSS_WD_configure() and the
MSS_WD_get_config() functions. mss_watchdog_num //**
The mss_watchdog_num_t is the watchdog module number enumeration.
MSS_WDOG0_LO to MSS_WDOG4_LO correspond to the watchdog module number
0 to 4 when they appear on the AXI switch slave 5.
MSS_WDOG0_HI to MSS_WDOG4_HI correspond to the watchdog module number
0 to 4 when they appear on the AXI switch slave 6. mss_watchdog_num_t //**
The mss_watchdog_num_t is the watchdog module number enumeration.
MSS_WDOG0_LO to MSS_WDOG4_LO correspond to the watchdog module number
0 to 4 when they appear on the AXI switch slave 5.
MSS_WDOG0_HI to MSS_WDOG4_HI correspond to the watchdog module number
0 to 4 when they appear on the AXI switch slave 6.
//**
The mss_watchdog_num_t is the watchdog module number enumeration.
MSS_WDOG0_LO to MSS_WDOG4_LO correspond to the watchdog module number
0 to 4 when they appear on the AXI switch slave 5.
MSS_WDOG0_HI to MSS_WDOG4_HI correspond to the watchdog module number
0 to 4 when they appear on the AXI switch slave 6. pf_pcie_atr_size_t PCIe AXI master and slave table size enum i.e PCIe ATR_SIZE
PCIe ATR_SIZE is 6 bits long and defines the Address Translation Space Size.
This space size in bytes is equal to 2^(ATR_SIZE +1). pf_pcie_bar_type_t The pf_pcie_bar_type_t type specifies the bar types supported by the driver
for the initialization of the PCIe AXI4 master address translation table. pf_pcie_ep_dma_status_t The pf_pcie_ep_dma_status_t type communicates the status of the DMA transfer
initiated by the most recent call to the PF_PCIE_dma_write() or
PF_PCIE_dma_read() function. It indicates if a transfer is in progress, and
if this is not the case, indicates the outcome of the latest transfer. This
type is returned by the PF_PCIE_dma_get_transfer_status() function and used
as a parameter for the handler functions registered with the PCIe driver.
The following table shows the different statuses of an endpoint DMA transfer
indicated by the pf_pcie_ep_dma_status_t type. pf_pcie_read_callback_t //**
The pf_pcie_read_callback_t type defines the function prototype that must be
followed by PolarFire PCIe End Point DMA read completion handler function. pf_pcie_tlp_type_t The pf_pcie_tlp_type_t type specifies the transaction layer packet types
supported by the driver for the initialization of the PCIe AXI4 master and
slave address translation tables. pf_pcie_write_callback_t //**
The pf_pcie_write_callback_t type defines the function prototype that must be
followed by PolarFire PCIe End Point DMA write completion handler function. pmss_can_config_reg pmss_can_filterobject pmss_can_int_enable pmss_can_int_status pmss_can_msgobject pmss_can_rxmsgobject psr_t sweep_index //**
sweep indexโs uint_fast8_t uint_fast16_t uint_fast32_t uint_fast64_t uint_least8_t uint_least16_t uint_least32_t uint_least64_t uintmax_t wchar_t CFG_DDR_SGMII_PHY_BANK_STATUS_TypeDef CFG_DDR_SGMII_PHY_BCLKMUX_TypeDef CFG_DDR_SGMII_PHY_CH0_CNTL_TypeDef CFG_DDR_SGMII_PHY_CH1_CNTL_TypeDef CFG_DDR_SGMII_PHY_CLK_CNTL_TypeDef CFG_DDR_SGMII_PHY_DDRPHY_MODE_TypeDef CFG_DDR_SGMII_PHY_DDRPHY_STARTUP_TypeDef CFG_DDR_SGMII_PHY_DPC_BITS_TypeDef CFG_DDR_SGMII_PHY_DYN_CNTL_TypeDef CFG_DDR_SGMII_PHY_FMETER_ADDR_TypeDef CFG_DDR_SGMII_PHY_FMETER_DATAR_TypeDef CFG_DDR_SGMII_PHY_FMETER_DATAW_TypeDef CFG_DDR_SGMII_PHY_IOC_REG0_TypeDef CFG_DDR_SGMII_PHY_IOC_REG1_TypeDef CFG_DDR_SGMII_PHY_IOC_REG2_TypeDef CFG_DDR_SGMII_PHY_IOC_REG3_TypeDef CFG_DDR_SGMII_PHY_IOC_REG4_TypeDef CFG_DDR_SGMII_PHY_IOC_REG5_TypeDef CFG_DDR_SGMII_PHY_IOC_REG6_TypeDef CFG_DDR_SGMII_PHY_MSSCLKMUX_TypeDef CFG_DDR_SGMII_PHY_PLL_CAL_IOSCB_TypeDef CFG_DDR_SGMII_PHY_PLL_CAL_MAIN_TypeDef CFG_DDR_SGMII_PHY_PLL_CKMUX_TypeDef CFG_DDR_SGMII_PHY_PLL_CNTL_TypeDef CFG_DDR_SGMII_PHY_PLL_CTRL2_IOSCB_TypeDef CFG_DDR_SGMII_PHY_PLL_CTRL2_MAIN_TypeDef CFG_DDR_SGMII_PHY_PLL_CTRL_IOSCB_TypeDef CFG_DDR_SGMII_PHY_PLL_CTRL_MAIN_TypeDef CFG_DDR_SGMII_PHY_PLL_DIV_0_1_IOSCB_TypeDef CFG_DDR_SGMII_PHY_PLL_DIV_0_1_MAIN_TypeDef CFG_DDR_SGMII_PHY_PLL_DIV_2_3_IOSCB_TypeDef CFG_DDR_SGMII_PHY_PLL_DIV_2_3_MAIN_TypeDef CFG_DDR_SGMII_PHY_PLL_FRACN_IOSCB_TypeDef CFG_DDR_SGMII_PHY_PLL_FRACN_MAIN_TypeDef CFG_DDR_SGMII_PHY_PLL_PHADJ_IOSCB_TypeDef CFG_DDR_SGMII_PHY_PLL_PHADJ_MAIN_TypeDef CFG_DDR_SGMII_PHY_PLL_REF_FB_IOSCB_TypeDef CFG_DDR_SGMII_PHY_PLL_REF_FB_MAIN_TypeDef CFG_DDR_SGMII_PHY_PVT_STAT_TypeDef CFG_DDR_SGMII_PHY_RECAL_CNTL_TypeDef CFG_DDR_SGMII_PHY_RPC_RESET_BANK_CTRL_TypeDef CFG_DDR_SGMII_PHY_RPC_RESET_CFM_TypeDef CFG_DDR_SGMII_PHY_RPC_RESET_IOCALIB_TypeDef CFG_DDR_SGMII_PHY_RPC_RESET_IOSCB_TypeDef CFG_DDR_SGMII_PHY_RPC_RESET_MAIN_PLL_TypeDef CFG_DDR_SGMII_PHY_SGMII_MODE_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_BANK_CTRL_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_CFM_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DDR_PHY_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_DRIVER_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_IO_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_DECODER_ODT_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_IOCALIB_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_IOSCB_PLL_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_MAIN_PLL_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_SGMII_TypeDef CFG_DDR_SGMII_PHY_SOFT_RESET_TIP_TypeDef CFG_DDR_SGMII_PHY_SPARE0_TypeDef CFG_DDR_SGMII_PHY_SPARE_CNTL_TypeDef CFG_DDR_SGMII_PHY_SPARE_STAT_TypeDef CFG_DDR_SGMII_PHY_SSCG_REG_0_IOSCB_TypeDef CFG_DDR_SGMII_PHY_SSCG_REG_0_MAIN_TypeDef CFG_DDR_SGMII_PHY_SSCG_REG_1_IOSCB_TypeDef CFG_DDR_SGMII_PHY_SSCG_REG_1_MAIN_TypeDef CFG_DDR_SGMII_PHY_SSCG_REG_2_IOSCB_TypeDef CFG_DDR_SGMII_PHY_SSCG_REG_2_MAIN_TypeDef CFG_DDR_SGMII_PHY_SSCG_REG_3_IOSCB_TypeDef CFG_DDR_SGMII_PHY_SSCG_REG_3_MAIN_TypeDef CFG_DDR_SGMII_PHY_TEST_CTRL_TypeDef CFG_DDR_SGMII_PHY_addcmd_answer_TypeDef CFG_DDR_SGMII_PHY_addcmd_status0_TypeDef CFG_DDR_SGMII_PHY_addcmd_status1_TypeDef CFG_DDR_SGMII_PHY_bclksclk_answer_TypeDef CFG_DDR_SGMII_PHY_delta0_TypeDef CFG_DDR_SGMII_PHY_delta1_TypeDef CFG_DDR_SGMII_PHY_dq_dqs_err_done_TypeDef CFG_DDR_SGMII_PHY_dqdqs_state_TypeDef CFG_DDR_SGMII_PHY_dqdqs_status0_TypeDef CFG_DDR_SGMII_PHY_dqdqs_status1_TypeDef CFG_DDR_SGMII_PHY_dqdqs_status2_TypeDef CFG_DDR_SGMII_PHY_dqdqs_status3_TypeDef CFG_DDR_SGMII_PHY_dqdqs_status4_TypeDef CFG_DDR_SGMII_PHY_dqdqs_status5_TypeDef CFG_DDR_SGMII_PHY_dqdqs_status6_TypeDef CFG_DDR_SGMII_PHY_dqdqs_window_TypeDef CFG_DDR_SGMII_PHY_dqdqs_wrcalib_offset_TypeDef CFG_DDR_SGMII_PHY_expert_addcmd_ln_readback_TypeDef CFG_DDR_SGMII_PHY_expert_calif_TypeDef CFG_DDR_SGMII_PHY_expert_calif_readback1_TypeDef CFG_DDR_SGMII_PHY_expert_calif_readback_TypeDef CFG_DDR_SGMII_PHY_expert_dfi_status_override_to_shim_TypeDef CFG_DDR_SGMII_PHY_expert_dlycnt_direction_reg0_TypeDef CFG_DDR_SGMII_PHY_expert_dlycnt_direction_reg1_TypeDef CFG_DDR_SGMII_PHY_expert_dlycnt_load_reg0_TypeDef CFG_DDR_SGMII_PHY_expert_dlycnt_load_reg1_TypeDef CFG_DDR_SGMII_PHY_expert_dlycnt_move_reg0_TypeDef CFG_DDR_SGMII_PHY_expert_dlycnt_move_reg1_TypeDef CFG_DDR_SGMII_PHY_expert_dlycnt_mv_rd_dly_reg_TypeDef CFG_DDR_SGMII_PHY_expert_dlycnt_oor_reg0_TypeDef CFG_DDR_SGMII_PHY_expert_dlycnt_oor_reg1_TypeDef CFG_DDR_SGMII_PHY_expert_dlycnt_pause_TypeDef CFG_DDR_SGMII_PHY_expert_dq_dqs_optimization0_TypeDef CFG_DDR_SGMII_PHY_expert_dq_dqs_optimization1_TypeDef CFG_DDR_SGMII_PHY_expert_dqlane_readback_TypeDef CFG_DDR_SGMII_PHY_expert_mode_en_TypeDef CFG_DDR_SGMII_PHY_expert_pllcnt_TypeDef CFG_DDR_SGMII_PHY_expert_read_gate_controls_TypeDef CFG_DDR_SGMII_PHY_expert_wrcalib_TypeDef CFG_DDR_SGMII_PHY_gt_clk_sel_TypeDef CFG_DDR_SGMII_PHY_gt_err_comb_TypeDef CFG_DDR_SGMII_PHY_gt_state_TypeDef CFG_DDR_SGMII_PHY_gt_steps_180_TypeDef CFG_DDR_SGMII_PHY_gt_txdly_TypeDef CFG_DDR_SGMII_PHY_lane_alignment_fifo_control_TypeDef CFG_DDR_SGMII_PHY_lane_select_TypeDef CFG_DDR_SGMII_PHY_ovrt1_TypeDef CFG_DDR_SGMII_PHY_ovrt2_TypeDef CFG_DDR_SGMII_PHY_ovrt3_TypeDef CFG_DDR_SGMII_PHY_ovrt4_TypeDef CFG_DDR_SGMII_PHY_ovrt5_TypeDef CFG_DDR_SGMII_PHY_ovrt6_TypeDef CFG_DDR_SGMII_PHY_ovrt7_TypeDef CFG_DDR_SGMII_PHY_ovrt8_TypeDef CFG_DDR_SGMII_PHY_ovrt9_TypeDef CFG_DDR_SGMII_PHY_ovrt10_TypeDef CFG_DDR_SGMII_PHY_ovrt11_TypeDef CFG_DDR_SGMII_PHY_ovrt12_TypeDef CFG_DDR_SGMII_PHY_ovrt13_TypeDef CFG_DDR_SGMII_PHY_ovrt14_TypeDef CFG_DDR_SGMII_PHY_ovrt15_TypeDef CFG_DDR_SGMII_PHY_ovrt16_TypeDef CFG_DDR_SGMII_PHY_rank_select_TypeDef CFG_DDR_SGMII_PHY_rpc1_DRV_TypeDef CFG_DDR_SGMII_PHY_rpc1_ODT_TypeDef CFG_DDR_SGMII_PHY_rpc2_DRV_TypeDef CFG_DDR_SGMII_PHY_rpc2_ODT_TypeDef CFG_DDR_SGMII_PHY_rpc3_DRV_TypeDef CFG_DDR_SGMII_PHY_rpc3_ODT_TypeDef CFG_DDR_SGMII_PHY_rpc4_DRV_TypeDef CFG_DDR_SGMII_PHY_rpc4_ODT_TypeDef CFG_DDR_SGMII_PHY_rpc5_ODT_TypeDef CFG_DDR_SGMII_PHY_rpc6_ODT_TypeDef CFG_DDR_SGMII_PHY_rpc7_ODT_TypeDef CFG_DDR_SGMII_PHY_rpc8_ODT_TypeDef CFG_DDR_SGMII_PHY_rpc9_ODT_TypeDef CFG_DDR_SGMII_PHY_rpc10_ODT_TypeDef CFG_DDR_SGMII_PHY_rpc11_ODT_TypeDef CFG_DDR_SGMII_PHY_rpc17_TypeDef CFG_DDR_SGMII_PHY_rpc18_TypeDef CFG_DDR_SGMII_PHY_rpc19_TypeDef CFG_DDR_SGMII_PHY_rpc20_TypeDef CFG_DDR_SGMII_PHY_rpc21_TypeDef CFG_DDR_SGMII_PHY_rpc22_TypeDef CFG_DDR_SGMII_PHY_rpc23_TypeDef CFG_DDR_SGMII_PHY_rpc24_TypeDef CFG_DDR_SGMII_PHY_rpc25_TypeDef CFG_DDR_SGMII_PHY_rpc26_TypeDef CFG_DDR_SGMII_PHY_rpc27_TypeDef CFG_DDR_SGMII_PHY_rpc28_TypeDef CFG_DDR_SGMII_PHY_rpc29_TypeDef CFG_DDR_SGMII_PHY_rpc30_TypeDef CFG_DDR_SGMII_PHY_rpc31_TypeDef CFG_DDR_SGMII_PHY_rpc32_TypeDef CFG_DDR_SGMII_PHY_rpc33_TypeDef CFG_DDR_SGMII_PHY_rpc34_TypeDef CFG_DDR_SGMII_PHY_rpc35_TypeDef CFG_DDR_SGMII_PHY_rpc36_TypeDef CFG_DDR_SGMII_PHY_rpc37_TypeDef CFG_DDR_SGMII_PHY_rpc38_TypeDef CFG_DDR_SGMII_PHY_rpc39_TypeDef CFG_DDR_SGMII_PHY_rpc40_TypeDef CFG_DDR_SGMII_PHY_rpc41_TypeDef CFG_DDR_SGMII_PHY_rpc42_TypeDef CFG_DDR_SGMII_PHY_rpc43_TypeDef CFG_DDR_SGMII_PHY_rpc44_TypeDef CFG_DDR_SGMII_PHY_rpc45_TypeDef CFG_DDR_SGMII_PHY_rpc46_TypeDef CFG_DDR_SGMII_PHY_rpc47_TypeDef CFG_DDR_SGMII_PHY_rpc48_TypeDef CFG_DDR_SGMII_PHY_rpc49_TypeDef CFG_DDR_SGMII_PHY_rpc50_TypeDef CFG_DDR_SGMII_PHY_rpc51_TypeDef CFG_DDR_SGMII_PHY_rpc52_TypeDef CFG_DDR_SGMII_PHY_rpc53_TypeDef CFG_DDR_SGMII_PHY_rpc54_TypeDef CFG_DDR_SGMII_PHY_rpc55_TypeDef CFG_DDR_SGMII_PHY_rpc56_TypeDef CFG_DDR_SGMII_PHY_rpc57_TypeDef CFG_DDR_SGMII_PHY_rpc58_TypeDef CFG_DDR_SGMII_PHY_rpc59_TypeDef CFG_DDR_SGMII_PHY_rpc60_TypeDef CFG_DDR_SGMII_PHY_rpc61_TypeDef CFG_DDR_SGMII_PHY_rpc62_TypeDef CFG_DDR_SGMII_PHY_rpc63_TypeDef CFG_DDR_SGMII_PHY_rpc64_TypeDef CFG_DDR_SGMII_PHY_rpc65_TypeDef CFG_DDR_SGMII_PHY_rpc66_TypeDef CFG_DDR_SGMII_PHY_rpc67_TypeDef CFG_DDR_SGMII_PHY_rpc68_TypeDef CFG_DDR_SGMII_PHY_rpc69_TypeDef CFG_DDR_SGMII_PHY_rpc70_TypeDef CFG_DDR_SGMII_PHY_rpc71_TypeDef CFG_DDR_SGMII_PHY_rpc72_TypeDef CFG_DDR_SGMII_PHY_rpc73_TypeDef CFG_DDR_SGMII_PHY_rpc74_TypeDef CFG_DDR_SGMII_PHY_rpc75_TypeDef CFG_DDR_SGMII_PHY_rpc76_TypeDef CFG_DDR_SGMII_PHY_rpc77_TypeDef CFG_DDR_SGMII_PHY_rpc78_TypeDef CFG_DDR_SGMII_PHY_rpc79_TypeDef CFG_DDR_SGMII_PHY_rpc80_TypeDef CFG_DDR_SGMII_PHY_rpc81_TypeDef CFG_DDR_SGMII_PHY_rpc82_TypeDef CFG_DDR_SGMII_PHY_rpc83_TypeDef CFG_DDR_SGMII_PHY_rpc84_TypeDef CFG_DDR_SGMII_PHY_rpc85_TypeDef CFG_DDR_SGMII_PHY_rpc86_TypeDef CFG_DDR_SGMII_PHY_rpc87_TypeDef CFG_DDR_SGMII_PHY_rpc88_TypeDef CFG_DDR_SGMII_PHY_rpc89_TypeDef CFG_DDR_SGMII_PHY_rpc90_TypeDef CFG_DDR_SGMII_PHY_rpc91_TypeDef CFG_DDR_SGMII_PHY_rpc92_TypeDef CFG_DDR_SGMII_PHY_rpc93_TypeDef CFG_DDR_SGMII_PHY_rpc94_TypeDef CFG_DDR_SGMII_PHY_rpc95_TypeDef CFG_DDR_SGMII_PHY_rpc96_TypeDef CFG_DDR_SGMII_PHY_rpc97_TypeDef CFG_DDR_SGMII_PHY_rpc98_TypeDef CFG_DDR_SGMII_PHY_rpc99_TypeDef CFG_DDR_SGMII_PHY_rpc100_TypeDef CFG_DDR_SGMII_PHY_rpc101_TypeDef CFG_DDR_SGMII_PHY_rpc102_TypeDef CFG_DDR_SGMII_PHY_rpc103_TypeDef CFG_DDR_SGMII_PHY_rpc104_TypeDef CFG_DDR_SGMII_PHY_rpc105_TypeDef CFG_DDR_SGMII_PHY_rpc106_TypeDef CFG_DDR_SGMII_PHY_rpc107_TypeDef CFG_DDR_SGMII_PHY_rpc108_TypeDef CFG_DDR_SGMII_PHY_rpc109_TypeDef CFG_DDR_SGMII_PHY_rpc110_TypeDef CFG_DDR_SGMII_PHY_rpc111_TypeDef CFG_DDR_SGMII_PHY_rpc112_TypeDef CFG_DDR_SGMII_PHY_rpc113_TypeDef CFG_DDR_SGMII_PHY_rpc114_TypeDef CFG_DDR_SGMII_PHY_rpc115_TypeDef CFG_DDR_SGMII_PHY_rpc116_TypeDef CFG_DDR_SGMII_PHY_rpc117_TypeDef CFG_DDR_SGMII_PHY_rpc118_TypeDef CFG_DDR_SGMII_PHY_rpc119_TypeDef CFG_DDR_SGMII_PHY_rpc120_TypeDef CFG_DDR_SGMII_PHY_rpc121_TypeDef CFG_DDR_SGMII_PHY_rpc122_TypeDef CFG_DDR_SGMII_PHY_rpc123_TypeDef CFG_DDR_SGMII_PHY_rpc124_TypeDef CFG_DDR_SGMII_PHY_rpc125_TypeDef CFG_DDR_SGMII_PHY_rpc126_TypeDef CFG_DDR_SGMII_PHY_rpc127_TypeDef CFG_DDR_SGMII_PHY_rpc128_TypeDef CFG_DDR_SGMII_PHY_rpc129_TypeDef CFG_DDR_SGMII_PHY_rpc130_TypeDef CFG_DDR_SGMII_PHY_rpc131_TypeDef CFG_DDR_SGMII_PHY_rpc132_TypeDef CFG_DDR_SGMII_PHY_rpc133_TypeDef CFG_DDR_SGMII_PHY_rpc134_TypeDef CFG_DDR_SGMII_PHY_rpc135_TypeDef CFG_DDR_SGMII_PHY_rpc136_TypeDef CFG_DDR_SGMII_PHY_rpc137_TypeDef CFG_DDR_SGMII_PHY_rpc138_TypeDef CFG_DDR_SGMII_PHY_rpc139_TypeDef CFG_DDR_SGMII_PHY_rpc140_TypeDef CFG_DDR_SGMII_PHY_rpc141_TypeDef CFG_DDR_SGMII_PHY_rpc142_TypeDef CFG_DDR_SGMII_PHY_rpc143_TypeDef CFG_DDR_SGMII_PHY_rpc144_TypeDef CFG_DDR_SGMII_PHY_rpc145_TypeDef CFG_DDR_SGMII_PHY_rpc146_TypeDef CFG_DDR_SGMII_PHY_rpc147_TypeDef CFG_DDR_SGMII_PHY_rpc148_TypeDef CFG_DDR_SGMII_PHY_rpc149_TypeDef CFG_DDR_SGMII_PHY_rpc150_TypeDef CFG_DDR_SGMII_PHY_rpc151_TypeDef CFG_DDR_SGMII_PHY_rpc152_TypeDef CFG_DDR_SGMII_PHY_rpc153_TypeDef CFG_DDR_SGMII_PHY_rpc154_TypeDef CFG_DDR_SGMII_PHY_rpc155_TypeDef CFG_DDR_SGMII_PHY_rpc156_TypeDef CFG_DDR_SGMII_PHY_rpc157_TypeDef CFG_DDR_SGMII_PHY_rpc158_TypeDef CFG_DDR_SGMII_PHY_rpc159_TypeDef CFG_DDR_SGMII_PHY_rpc160_TypeDef CFG_DDR_SGMII_PHY_rpc161_TypeDef CFG_DDR_SGMII_PHY_rpc162_TypeDef CFG_DDR_SGMII_PHY_rpc163_TypeDef CFG_DDR_SGMII_PHY_rpc164_TypeDef CFG_DDR_SGMII_PHY_rpc165_TypeDef CFG_DDR_SGMII_PHY_rpc166_TypeDef CFG_DDR_SGMII_PHY_rpc167_TypeDef CFG_DDR_SGMII_PHY_rpc168_TypeDef CFG_DDR_SGMII_PHY_rpc169_TypeDef CFG_DDR_SGMII_PHY_rpc170_TypeDef CFG_DDR_SGMII_PHY_rpc171_TypeDef CFG_DDR_SGMII_PHY_rpc172_TypeDef CFG_DDR_SGMII_PHY_rpc173_TypeDef CFG_DDR_SGMII_PHY_rpc174_TypeDef CFG_DDR_SGMII_PHY_rpc175_TypeDef CFG_DDR_SGMII_PHY_rpc176_TypeDef CFG_DDR_SGMII_PHY_rpc177_TypeDef CFG_DDR_SGMII_PHY_rpc178_TypeDef CFG_DDR_SGMII_PHY_rpc179_TypeDef CFG_DDR_SGMII_PHY_rpc180_TypeDef CFG_DDR_SGMII_PHY_rpc181_TypeDef CFG_DDR_SGMII_PHY_rpc182_TypeDef CFG_DDR_SGMII_PHY_rpc183_TypeDef CFG_DDR_SGMII_PHY_rpc184_TypeDef CFG_DDR_SGMII_PHY_rpc185_TypeDef CFG_DDR_SGMII_PHY_rpc186_TypeDef CFG_DDR_SGMII_PHY_rpc187_TypeDef CFG_DDR_SGMII_PHY_rpc188_TypeDef CFG_DDR_SGMII_PHY_rpc189_TypeDef CFG_DDR_SGMII_PHY_rpc190_TypeDef CFG_DDR_SGMII_PHY_rpc191_TypeDef CFG_DDR_SGMII_PHY_rpc192_TypeDef CFG_DDR_SGMII_PHY_rpc193_TypeDef CFG_DDR_SGMII_PHY_rpc194_TypeDef CFG_DDR_SGMII_PHY_rpc195_TypeDef CFG_DDR_SGMII_PHY_rpc196_TypeDef CFG_DDR_SGMII_PHY_rpc197_TypeDef CFG_DDR_SGMII_PHY_rpc198_TypeDef CFG_DDR_SGMII_PHY_rpc199_TypeDef CFG_DDR_SGMII_PHY_rpc200_TypeDef CFG_DDR_SGMII_PHY_rpc201_TypeDef CFG_DDR_SGMII_PHY_rpc202_TypeDef CFG_DDR_SGMII_PHY_rpc203_TypeDef CFG_DDR_SGMII_PHY_rpc204_TypeDef CFG_DDR_SGMII_PHY_rpc205_TypeDef CFG_DDR_SGMII_PHY_rpc206_TypeDef CFG_DDR_SGMII_PHY_rpc207_TypeDef CFG_DDR_SGMII_PHY_rpc208_TypeDef CFG_DDR_SGMII_PHY_rpc209_TypeDef CFG_DDR_SGMII_PHY_rpc210_TypeDef CFG_DDR_SGMII_PHY_rpc211_TypeDef CFG_DDR_SGMII_PHY_rpc212_TypeDef CFG_DDR_SGMII_PHY_rpc213_TypeDef CFG_DDR_SGMII_PHY_rpc214_TypeDef CFG_DDR_SGMII_PHY_rpc215_TypeDef CFG_DDR_SGMII_PHY_rpc216_TypeDef CFG_DDR_SGMII_PHY_rpc217_TypeDef CFG_DDR_SGMII_PHY_rpc218_TypeDef CFG_DDR_SGMII_PHY_rpc219_TypeDef CFG_DDR_SGMII_PHY_rpc220_TypeDef CFG_DDR_SGMII_PHY_rpc221_TypeDef CFG_DDR_SGMII_PHY_rpc222_TypeDef CFG_DDR_SGMII_PHY_rpc223_TypeDef CFG_DDR_SGMII_PHY_rpc224_TypeDef CFG_DDR_SGMII_PHY_rpc225_TypeDef CFG_DDR_SGMII_PHY_rpc226_TypeDef CFG_DDR_SGMII_PHY_rpc227_TypeDef CFG_DDR_SGMII_PHY_rpc228_TypeDef CFG_DDR_SGMII_PHY_rpc229_TypeDef CFG_DDR_SGMII_PHY_rpc230_TypeDef CFG_DDR_SGMII_PHY_rpc231_TypeDef CFG_DDR_SGMII_PHY_rpc232_TypeDef CFG_DDR_SGMII_PHY_rpc233_TypeDef CFG_DDR_SGMII_PHY_rpc234_TypeDef CFG_DDR_SGMII_PHY_rpc235_TypeDef CFG_DDR_SGMII_PHY_rpc236_TypeDef CFG_DDR_SGMII_PHY_rpc237_TypeDef CFG_DDR_SGMII_PHY_rpc238_TypeDef CFG_DDR_SGMII_PHY_rpc239_TypeDef CFG_DDR_SGMII_PHY_rpc240_TypeDef CFG_DDR_SGMII_PHY_rpc241_TypeDef CFG_DDR_SGMII_PHY_rpc242_TypeDef CFG_DDR_SGMII_PHY_rpc243_TypeDef CFG_DDR_SGMII_PHY_rpc244_TypeDef CFG_DDR_SGMII_PHY_rpc245_TypeDef CFG_DDR_SGMII_PHY_rpc246_TypeDef CFG_DDR_SGMII_PHY_rpc247_TypeDef CFG_DDR_SGMII_PHY_rpc248_TypeDef CFG_DDR_SGMII_PHY_rpc249_TypeDef CFG_DDR_SGMII_PHY_rpc250_TypeDef CFG_DDR_SGMII_PHY_rpc_calib_TypeDef CFG_DDR_SGMII_PHY_spio251_TypeDef CFG_DDR_SGMII_PHY_spio252_TypeDef CFG_DDR_SGMII_PHY_spio253_TypeDef CFG_DDR_SGMII_PHY_tip_cfg_params_TypeDef CFG_DDR_SGMII_PHY_tip_vref_param_TypeDef CFG_DDR_SGMII_PHY_training_reset_TypeDef CFG_DDR_SGMII_PHY_training_skip_TypeDef CFG_DDR_SGMII_PHY_training_start_TypeDef CFG_DDR_SGMII_PHY_training_status_TypeDef CFG_DDR_SGMII_PHY_wl_delay_0_TypeDef DDR_CSR_APB_CFG_ACTIVE_DQ_SEL_TypeDef DDR_CSR_APB_CFG_ADDR_MIRROR_TypeDef DDR_CSR_APB_CFG_ADVANCE_ACTIVATE_READY_TypeDef DDR_CSR_APB_CFG_AL_MODE_TypeDef DDR_CSR_APB_CFG_ASYNC_ODT_TypeDef DDR_CSR_APB_CFG_AUTO_REF_EN_TypeDef DDR_CSR_APB_CFG_AUTO_SR_TypeDef DDR_CSR_APB_CFG_AUTO_ZQ_CAL_EN_TypeDef DDR_CSR_APB_CFG_AXI_AUTO_PCH_TypeDef DDR_CSR_APB_CFG_AXI_END_ADDRESS_AXI1_0_TypeDef DDR_CSR_APB_CFG_AXI_END_ADDRESS_AXI1_1_TypeDef DDR_CSR_APB_CFG_AXI_END_ADDRESS_AXI2_0_TypeDef DDR_CSR_APB_CFG_AXI_END_ADDRESS_AXI2_1_TypeDef DDR_CSR_APB_CFG_AXI_START_ADDRESS_AXI1_0_TypeDef DDR_CSR_APB_CFG_AXI_START_ADDRESS_AXI1_1_TypeDef DDR_CSR_APB_CFG_AXI_START_ADDRESS_AXI2_0_TypeDef DDR_CSR_APB_CFG_AXI_START_ADDRESS_AXI2_1_TypeDef DDR_CSR_APB_CFG_BANKADDR_MAP_0_TypeDef DDR_CSR_APB_CFG_BANKADDR_MAP_1_TypeDef DDR_CSR_APB_CFG_BG_INTERLEAVE_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS0_0_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS0_1_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS1_0_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS1_1_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS2_0_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS2_1_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS3_0_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS3_1_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS4_0_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS4_1_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS5_0_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS5_1_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS6_0_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS6_1_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS7_0_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS7_1_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS8_0_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS8_1_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS9_0_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS9_1_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS10_0_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS10_1_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS11_0_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS11_1_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS12_0_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS12_1_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS13_0_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS13_1_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS14_0_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS14_1_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS15_0_TypeDef DDR_CSR_APB_CFG_BIT_MAP_INDEX_CS15_1_TypeDef DDR_CSR_APB_CFG_BL_MODE_TypeDef DDR_CSR_APB_CFG_BL_TypeDef DDR_CSR_APB_CFG_BT_TypeDef DDR_CSR_APB_CFG_BURST_RW_REFRESH_HOLDOFF_TypeDef DDR_CSR_APB_CFG_CAL_READ_PERIOD_TypeDef DDR_CSR_APB_CFG_CA_ODT_TypeDef DDR_CSR_APB_CFG_CA_PARITY_ERR_STATUS_TypeDef DDR_CSR_APB_CFG_CA_PARITY_LATENCY_TypeDef DDR_CSR_APB_CFG_CA_PARITY_PERSIST_ERR_TypeDef DDR_CSR_APB_CFG_CCD_L_TypeDef DDR_CSR_APB_CFG_CCD_S_TypeDef DDR_CSR_APB_CFG_CHIPADDR_MAP_TypeDef DDR_CSR_APB_CFG_CIDADDR_MAP_TypeDef DDR_CSR_APB_CFG_CKSRE_TypeDef DDR_CSR_APB_CFG_CKSRX_TypeDef DDR_CSR_APB_CFG_CL_TypeDef DDR_CSR_APB_CFG_COLADDR_MAP_0_TypeDef DDR_CSR_APB_CFG_COLADDR_MAP_1_TypeDef DDR_CSR_APB_CFG_COLADDR_MAP_2_TypeDef DDR_CSR_APB_CFG_CRC_ERROR_CLEAR_TypeDef DDR_CSR_APB_CFG_CS_TO_CMDADDR_LATENCY_TypeDef DDR_CSR_APB_CFG_CTRLR_BUSY_ENABLE_TypeDef DDR_CSR_APB_CFG_CTRLR_BUSY_RESTART_HOLDOFF_TypeDef DDR_CSR_APB_CFG_CTRLR_BUSY_SEL_TypeDef DDR_CSR_APB_CFG_CTRLR_BUSY_SLOW_RESTART_WINDOW_TypeDef DDR_CSR_APB_CFG_CTRLR_BUSY_TURN_OFF_DELAY_TypeDef DDR_CSR_APB_CFG_CTRLR_BUSY_VALUE_TypeDef DDR_CSR_APB_CFG_CTRLR_INIT_DISABLE_TypeDef DDR_CSR_APB_CFG_CTRLUPD_START_DELAY_TypeDef DDR_CSR_APB_CFG_CTRLUPD_TRIG_TypeDef DDR_CSR_APB_CFG_CWL_TypeDef DDR_CSR_APB_CFG_DATA_MASK_TypeDef DDR_CSR_APB_CFG_DATA_SEL_FIRST_ERROR_TypeDef DDR_CSR_APB_CFG_DATA_SEL_TypeDef DDR_CSR_APB_CFG_DBI_CL_TypeDef DDR_CSR_APB_CFG_DFI_DATA_BYTE_DISABLE_TypeDef DDR_CSR_APB_CFG_DFI_LVL_PATTERN_TypeDef DDR_CSR_APB_CFG_DFI_LVL_PERIODIC_TypeDef DDR_CSR_APB_CFG_DFI_LVL_SEL_TypeDef DDR_CSR_APB_CFG_DFI_PHYUPD_EN_TypeDef DDR_CSR_APB_CFG_DFI_T_CTRLUPD_MAX_TypeDef DDR_CSR_APB_CFG_DFI_T_CTRL_DELAY_TypeDef DDR_CSR_APB_CFG_DFI_T_DRAM_CLK_ENABLE_TypeDef DDR_CSR_APB_CFG_DFI_T_PHY_RDLAT_TypeDef DDR_CSR_APB_CFG_DFI_T_PHY_WRLAT_TypeDef DDR_CSR_APB_CFG_DFI_T_RDDATA_EN_TypeDef DDR_CSR_APB_CFG_DLL_DISABLE_TypeDef DDR_CSR_APB_CFG_DM_EN_TypeDef DDR_CSR_APB_CFG_DQ_ODT_TypeDef DDR_CSR_APB_CFG_DQ_WIDTH_TypeDef DDR_CSR_APB_CFG_DRAM_CLK_DISABLE_IN_SELF_REFRESH_TypeDef DDR_CSR_APB_CFG_DS_TypeDef DDR_CSR_APB_CFG_EARLY_RANK_TO_RD_START_TypeDef DDR_CSR_APB_CFG_EARLY_RANK_TO_WR_START_TypeDef DDR_CSR_APB_CFG_ECC_1BIT_INT_THRESH_TypeDef DDR_CSR_APB_CFG_ECC_BYPASS_TypeDef DDR_CSR_APB_CFG_ECC_CORRECTION_EN_TypeDef DDR_CSR_APB_CFG_EMR3_TypeDef DDR_CSR_APB_CFG_ENABLE_BUS_HOLD_AXI1_TypeDef DDR_CSR_APB_CFG_ENABLE_BUS_HOLD_AXI2_TypeDef DDR_CSR_APB_CFG_EN_MASK_TypeDef DDR_CSR_APB_CFG_ERROR_GROUP_SEL_TypeDef DDR_CSR_APB_CFG_FAW_DLR_TypeDef DDR_CSR_APB_CFG_FAW_TypeDef DDR_CSR_APB_CFG_FINE_GRAN_REF_MODE_TypeDef DDR_CSR_APB_CFG_GEARDOWN_MODE_TypeDef DDR_CSR_APB_CFG_GENERATE_REFRESH_ON_SRX_TypeDef DDR_CSR_APB_CFG_IDLE_TIME_TO_POWER_DOWN_TypeDef DDR_CSR_APB_CFG_IDLE_TIME_TO_SELF_REFRESH_TypeDef DDR_CSR_APB_CFG_INIT_DURATION_TypeDef DDR_CSR_APB_CFG_INTRAPORT_REORDER_EN_TypeDef DDR_CSR_APB_CFG_INT_VREF_MON_TypeDef DDR_CSR_APB_CFG_LOOKAHEAD_ACT_TypeDef DDR_CSR_APB_CFG_LOOKAHEAD_PCH_TypeDef DDR_CSR_APB_CFG_LPDDR4_FSP_OP_TypeDef DDR_CSR_APB_CFG_LP_ASR_TypeDef DDR_CSR_APB_CFG_LRDIMM_TypeDef DDR_CSR_APB_CFG_MAINTAIN_COHERENCY_TypeDef DDR_CSR_APB_CFG_MANUAL_ADDRESS_MAP_TypeDef DDR_CSR_APB_CFG_MAX_PWR_DOWN_MODE_TypeDef DDR_CSR_APB_CFG_MB_AUTOPCH_COL_BIT_POS_HIGH_TypeDef DDR_CSR_APB_CFG_MB_AUTOPCH_COL_BIT_POS_LOW_TypeDef DDR_CSR_APB_CFG_MEMORY_TYPE_TypeDef DDR_CSR_APB_CFG_MEM_BANKBITS_TypeDef DDR_CSR_APB_CFG_MEM_COLBITS_TypeDef DDR_CSR_APB_CFG_MEM_ROWBITS_TypeDef DDR_CSR_APB_CFG_MEM_START_ADDRESS_AXI1_0_TypeDef DDR_CSR_APB_CFG_MEM_START_ADDRESS_AXI1_1_TypeDef DDR_CSR_APB_CFG_MEM_START_ADDRESS_AXI2_0_TypeDef DDR_CSR_APB_CFG_MEM_START_ADDRESS_AXI2_1_TypeDef DDR_CSR_APB_CFG_MIN_READ_IDLE_TypeDef DDR_CSR_APB_CFG_MIRROR_X16_BG0_BG1_TypeDef DDR_CSR_APB_CFG_MOD_TypeDef DDR_CSR_APB_CFG_MPR_READ_FORMAT_TypeDef DDR_CSR_APB_CFG_MRD_TypeDef DDR_CSR_APB_CFG_MRRI_TypeDef DDR_CSR_APB_CFG_MRR_TypeDef DDR_CSR_APB_CFG_MRW_TypeDef DDR_CSR_APB_CFG_NIBBLE_DEVICES_TypeDef DDR_CSR_APB_CFG_NON_DBI_CL_TypeDef DDR_CSR_APB_CFG_NUM_CAL_READS_TypeDef DDR_CSR_APB_CFG_NUM_LOGICAL_RANKS_PER_3DS_TypeDef DDR_CSR_APB_CFG_NUM_RANKS_TypeDef DDR_CSR_APB_CFG_ODTD_CA_TypeDef DDR_CSR_APB_CFG_ODTE_CK_TypeDef DDR_CSR_APB_CFG_ODTE_CS_TypeDef DDR_CSR_APB_CFG_ODT_INBUF_4_PD_TypeDef DDR_CSR_APB_CFG_ODT_POWERDOWN_TypeDef DDR_CSR_APB_CFG_ODT_RD_MAP_CS0_TypeDef DDR_CSR_APB_CFG_ODT_RD_MAP_CS1_TypeDef DDR_CSR_APB_CFG_ODT_RD_MAP_CS2_TypeDef DDR_CSR_APB_CFG_ODT_RD_MAP_CS3_TypeDef DDR_CSR_APB_CFG_ODT_RD_MAP_CS4_TypeDef DDR_CSR_APB_CFG_ODT_RD_MAP_CS5_TypeDef DDR_CSR_APB_CFG_ODT_RD_MAP_CS6_TypeDef DDR_CSR_APB_CFG_ODT_RD_MAP_CS7_TypeDef DDR_CSR_APB_CFG_ODT_RD_TURN_OFF_TypeDef DDR_CSR_APB_CFG_ODT_RD_TURN_ON_TypeDef DDR_CSR_APB_CFG_ODT_WR_MAP_CS0_TypeDef DDR_CSR_APB_CFG_ODT_WR_MAP_CS1_TypeDef DDR_CSR_APB_CFG_ODT_WR_MAP_CS2_TypeDef DDR_CSR_APB_CFG_ODT_WR_MAP_CS3_TypeDef DDR_CSR_APB_CFG_ODT_WR_MAP_CS4_TypeDef DDR_CSR_APB_CFG_ODT_WR_MAP_CS5_TypeDef DDR_CSR_APB_CFG_ODT_WR_MAP_CS6_TypeDef DDR_CSR_APB_CFG_ODT_WR_MAP_CS7_TypeDef DDR_CSR_APB_CFG_ODT_WR_TURN_OFF_TypeDef DDR_CSR_APB_CFG_ODT_WR_TURN_ON_TypeDef DDR_CSR_APB_CFG_ONLY_SRANK_CMDS_TypeDef DDR_CSR_APB_CFG_PARITY_RDIMM_DELAY_TypeDef DDR_CSR_APB_CFG_PASR_BANK_TypeDef DDR_CSR_APB_CFG_PASR_SEG_TypeDef DDR_CSR_APB_CFG_PASR_TypeDef DDR_CSR_APB_CFG_PER_DRAM_ADDR_EN_TypeDef DDR_CSR_APB_CFG_PHYUPD_ACK_DELAY_TypeDef DDR_CSR_APB_CFG_POST_TRIG_CYCS_TypeDef DDR_CSR_APB_CFG_PRE_TRIG_CYCS_TypeDef DDR_CSR_APB_CFG_PU_CAL_TypeDef DDR_CSR_APB_CFG_QOFF_TypeDef DDR_CSR_APB_CFG_QUAD_RANK_TypeDef DDR_CSR_APB_CFG_Q_AGE_LIMIT_TypeDef DDR_CSR_APB_CFG_RAS_TypeDef DDR_CSR_APB_CFG_RCD_STAB_TypeDef DDR_CSR_APB_CFG_RCD_TypeDef DDR_CSR_APB_CFG_RC_TypeDef DDR_CSR_APB_CFG_RDIMM_BSIDE_INVERT_TypeDef DDR_CSR_APB_CFG_RDIMM_LAT_TypeDef DDR_CSR_APB_CFG_RD_POSTAMBLE_TypeDef DDR_CSR_APB_CFG_RD_PREAMBLE_TypeDef DDR_CSR_APB_CFG_RD_PREAMB_TOGGLE_TypeDef DDR_CSR_APB_CFG_RD_PREAMB_TRN_MODE_TypeDef DDR_CSR_APB_CFG_READ_DBI_TypeDef DDR_CSR_APB_CFG_READ_TO_READ_ODT_TypeDef DDR_CSR_APB_CFG_READ_TO_READ_TypeDef DDR_CSR_APB_CFG_READ_TO_WRITE_ODT_TypeDef DDR_CSR_APB_CFG_READ_TO_WRITE_TypeDef DDR_CSR_APB_CFG_REFRESH_DURING_PHY_TRAINING_TypeDef DDR_CSR_APB_CFG_REF_PER_TypeDef DDR_CSR_APB_CFG_REGDIMM_TypeDef DDR_CSR_APB_CFG_REORDER_EN_TypeDef DDR_CSR_APB_CFG_REORDER_QUEUE_EN_TypeDef DDR_CSR_APB_CFG_REORDER_RW_ONLY_TypeDef DDR_CSR_APB_CFG_RFC1_TypeDef DDR_CSR_APB_CFG_RFC2_TypeDef DDR_CSR_APB_CFG_RFC4_TypeDef DDR_CSR_APB_CFG_RFC_DLR1_TypeDef DDR_CSR_APB_CFG_RFC_DLR2_TypeDef DDR_CSR_APB_CFG_RFC_DLR4_TypeDef DDR_CSR_APB_CFG_RFC_TypeDef DDR_CSR_APB_CFG_RL_TypeDef DDR_CSR_APB_CFG_RMW_EN_TypeDef DDR_CSR_APB_CFG_ROWADDR_MAP_0_TypeDef DDR_CSR_APB_CFG_ROWADDR_MAP_1_TypeDef DDR_CSR_APB_CFG_ROWADDR_MAP_2_TypeDef DDR_CSR_APB_CFG_ROWADDR_MAP_3_TypeDef DDR_CSR_APB_CFG_RO_CLOSED_PAGE_POLICY_TypeDef DDR_CSR_APB_CFG_RO_PRIORITY_EN_TypeDef DDR_CSR_APB_CFG_RP_TypeDef DDR_CSR_APB_CFG_RRD_DLR_TypeDef DDR_CSR_APB_CFG_RRD_L_TypeDef DDR_CSR_APB_CFG_RRD_S_TypeDef DDR_CSR_APB_CFG_RRD_TypeDef DDR_CSR_APB_CFG_RTP_TypeDef DDR_CSR_APB_CFG_RTT_PARK_TypeDef DDR_CSR_APB_CFG_RTT_TypeDef DDR_CSR_APB_CFG_RTT_WR_TypeDef DDR_CSR_APB_CFG_SOC_ODT_TypeDef DDR_CSR_APB_CFG_SRT_TypeDef DDR_CSR_APB_CFG_SR_ABORT_TypeDef DDR_CSR_APB_CFG_STARTUP_DELAY_TypeDef DDR_CSR_APB_CFG_STARVE_TIMEOUT_P0_TypeDef DDR_CSR_APB_CFG_STARVE_TIMEOUT_P1_TypeDef DDR_CSR_APB_CFG_STARVE_TIMEOUT_P2_TypeDef DDR_CSR_APB_CFG_STARVE_TIMEOUT_P3_TypeDef DDR_CSR_APB_CFG_STARVE_TIMEOUT_P4_TypeDef DDR_CSR_APB_CFG_STARVE_TIMEOUT_P5_TypeDef DDR_CSR_APB_CFG_STARVE_TIMEOUT_P6_TypeDef DDR_CSR_APB_CFG_STARVE_TIMEOUT_P7_TypeDef DDR_CSR_APB_CFG_TDQS_TypeDef DDR_CSR_APB_CFG_TEMP_CTRL_REF_MODE_TypeDef DDR_CSR_APB_CFG_TEMP_CTRL_REF_RANGE_TypeDef DDR_CSR_APB_CFG_TEMP_SENSOR_READOUT_TypeDef DDR_CSR_APB_CFG_THERMAL_OFFSET_TypeDef DDR_CSR_APB_CFG_TRIG_ERR_MASK_0_TypeDef DDR_CSR_APB_CFG_TRIG_ERR_MASK_1_TypeDef DDR_CSR_APB_CFG_TRIG_ERR_MASK_2_TypeDef DDR_CSR_APB_CFG_TRIG_ERR_MASK_3_TypeDef DDR_CSR_APB_CFG_TRIG_ERR_MASK_4_TypeDef DDR_CSR_APB_CFG_TRIG_MASK_TypeDef DDR_CSR_APB_CFG_TRIG_MODE_TypeDef DDR_CSR_APB_CFG_TRIG_MT_ADDR_0_TypeDef DDR_CSR_APB_CFG_TRIG_MT_ADDR_1_TypeDef DDR_CSR_APB_CFG_TWO_T_SEL_CYCLE_TypeDef DDR_CSR_APB_CFG_TWO_T_TypeDef DDR_CSR_APB_CFG_VRCG_DISABLE_TypeDef DDR_CSR_APB_CFG_VRCG_ENABLE_TypeDef DDR_CSR_APB_CFG_VREFDQ_TRN_ENABLE_TypeDef DDR_CSR_APB_CFG_VREFDQ_TRN_RANGE_TypeDef DDR_CSR_APB_CFG_VREFDQ_TRN_VALUE_TypeDef DDR_CSR_APB_CFG_WL_TypeDef DDR_CSR_APB_CFG_WRITE_CRC_TypeDef DDR_CSR_APB_CFG_WRITE_DBI_TypeDef DDR_CSR_APB_CFG_WRITE_LATENCY_SET_TypeDef DDR_CSR_APB_CFG_WRITE_TO_READ_ODT_TypeDef DDR_CSR_APB_CFG_WRITE_TO_READ_TypeDef DDR_CSR_APB_CFG_WRITE_TO_WRITE_ODT_TypeDef DDR_CSR_APB_CFG_WRITE_TO_WRITE_TypeDef DDR_CSR_APB_CFG_WR_CMD_LAT_CRC_DM_TypeDef DDR_CSR_APB_CFG_WR_CRC_DM_TypeDef DDR_CSR_APB_CFG_WR_POSTAMBLE_TypeDef DDR_CSR_APB_CFG_WR_PREAMBLE_TypeDef DDR_CSR_APB_CFG_WR_TypeDef DDR_CSR_APB_CFG_WTR_L_CRC_DM_TypeDef DDR_CSR_APB_CFG_WTR_L_TypeDef DDR_CSR_APB_CFG_WTR_S_CRC_DM_TypeDef DDR_CSR_APB_CFG_WTR_S_TypeDef DDR_CSR_APB_CFG_WTR_TypeDef DDR_CSR_APB_CFG_XPR_TypeDef DDR_CSR_APB_CFG_XP_TypeDef DDR_CSR_APB_CFG_XSDLL_TypeDef DDR_CSR_APB_CFG_XSR_TypeDef DDR_CSR_APB_CFG_XS_TypeDef DDR_CSR_APB_CFG_ZQINIT_CAL_DURATION_TypeDef DDR_CSR_APB_CFG_ZQLATCH_DURATION_TypeDef DDR_CSR_APB_CFG_ZQ_CAL_DURATION_TypeDef DDR_CSR_APB_CFG_ZQ_CAL_L_DURATION_TypeDef DDR_CSR_APB_CFG_ZQ_CAL_PER_TypeDef DDR_CSR_APB_CFG_ZQ_CAL_R_DURATION_TypeDef DDR_CSR_APB_CFG_ZQ_CAL_S_DURATION_TypeDef DDR_CSR_APB_CFG_ZQ_CAL_TYPE_TypeDef DDR_CSR_APB_CTRLR_INIT_DONE_TypeDef DDR_CSR_APB_CTRLR_INIT_TypeDef DDR_CSR_APB_CTRLR_READY_TypeDef DDR_CSR_APB_CTRLR_SOFT_RESET_N_TypeDef DDR_CSR_APB_INIT_ACK_TypeDef DDR_CSR_APB_INIT_AUTOINIT_DISABLE_TypeDef DDR_CSR_APB_INIT_CAL_L_ADDR_0_TypeDef DDR_CSR_APB_INIT_CAL_L_ADDR_1_TypeDef DDR_CSR_APB_INIT_CAL_L_B_SIZE_TypeDef DDR_CSR_APB_INIT_CAL_L_READ_COMPLETE_TypeDef DDR_CSR_APB_INIT_CAL_L_R_ACK_TypeDef DDR_CSR_APB_INIT_CAL_L_R_REQ_TypeDef DDR_CSR_APB_INIT_CAL_SELECT_TypeDef DDR_CSR_APB_INIT_CA_PARITY_ERROR_GEN_ACK_TypeDef DDR_CSR_APB_INIT_CA_PARITY_ERROR_GEN_CMD_TypeDef DDR_CSR_APB_INIT_CA_PARITY_ERROR_GEN_REQ_TypeDef DDR_CSR_APB_INIT_CS_TypeDef DDR_CSR_APB_INIT_DFI_DRAM_CLK_DISABLE_TypeDef DDR_CSR_APB_INIT_DFI_LP_CTRL_REQ_TypeDef DDR_CSR_APB_INIT_DFI_LP_DATA_REQ_TypeDef DDR_CSR_APB_INIT_DFI_LP_WAKEUP_TypeDef DDR_CSR_APB_INIT_DISABLE_CKE_TypeDef DDR_CSR_APB_INIT_FORCE_RESET_TypeDef DDR_CSR_APB_INIT_FORCE_WRITE_CS_TypeDef DDR_CSR_APB_INIT_FORCE_WRITE_DATA_0_TypeDef DDR_CSR_APB_INIT_FORCE_WRITE_TypeDef DDR_CSR_APB_INIT_GEARDOWN_EN_TypeDef DDR_CSR_APB_INIT_MEMORY_RESET_MASK_TypeDef DDR_CSR_APB_INIT_MRR_MODE_TypeDef DDR_CSR_APB_INIT_MR_ADDR_TypeDef DDR_CSR_APB_INIT_MR_WR_DATA_TypeDef DDR_CSR_APB_INIT_MR_WR_MASK_TypeDef DDR_CSR_APB_INIT_MR_W_REQ_TypeDef DDR_CSR_APB_INIT_NOP_TypeDef DDR_CSR_APB_INIT_ODT_FORCE_EN_TypeDef DDR_CSR_APB_INIT_ODT_FORCE_RANK_TypeDef DDR_CSR_APB_INIT_PDA_MR_W_REQ_TypeDef DDR_CSR_APB_INIT_PDA_NIBBLE_SELECT_TypeDef DDR_CSR_APB_INIT_POWER_DOWN_STATUS_TypeDef DDR_CSR_APB_INIT_POWER_DOWN_TypeDef DDR_CSR_APB_INIT_PRECHARGE_ALL_TypeDef DDR_CSR_APB_INIT_RDIMM_COMPLETE_TypeDef DDR_CSR_APB_INIT_RDIMM_READY_TypeDef DDR_CSR_APB_INIT_RD_DQCAL_TypeDef DDR_CSR_APB_INIT_READ_CAPTURE_ADDR_TypeDef DDR_CSR_APB_INIT_READ_CAPTURE_DATA_0_TypeDef DDR_CSR_APB_INIT_READ_CAPTURE_DATA_1_TypeDef DDR_CSR_APB_INIT_READ_CAPTURE_DATA_2_TypeDef DDR_CSR_APB_INIT_READ_CAPTURE_DATA_3_TypeDef DDR_CSR_APB_INIT_READ_CAPTURE_DATA_4_TypeDef DDR_CSR_APB_INIT_REFRESH_COUNT_TypeDef DDR_CSR_APB_INIT_REFRESH_TypeDef DDR_CSR_APB_INIT_RWFIFO_TypeDef DDR_CSR_APB_INIT_SELF_REFRESH_STATUS_TypeDef DDR_CSR_APB_INIT_SELF_REFRESH_TypeDef DDR_CSR_APB_INIT_START_DQSOSC_TypeDef DDR_CSR_APB_INIT_STOP_DQSOSC_TypeDef DDR_CSR_APB_INIT_WRITE_DATA_1B_ECC_ERROR_GEN_TypeDef DDR_CSR_APB_INIT_WRITE_DATA_2B_ECC_ERROR_GEN_TypeDef DDR_CSR_APB_INIT_ZQ_CAL_REQ_TypeDef DDR_CSR_APB_INIT_ZQ_CAL_START_TypeDef DDR_CSR_APB_MTC_ACK_TypeDef DDR_CSR_APB_MTC_ACQ_ADDR_TypeDef DDR_CSR_APB_MTC_ACQ_CYCS_STORED_TypeDef DDR_CSR_APB_MTC_ACQ_ERROR_CNT_OVFL_TypeDef DDR_CSR_APB_MTC_ACQ_ERROR_CNT_TypeDef DDR_CSR_APB_MTC_ACQ_MEM_LAST_ADDR_TypeDef DDR_CSR_APB_MTC_ACQ_MEM_TRIG_ADDR_TypeDef DDR_CSR_APB_MTC_ACQ_RD_DATA_0_TypeDef DDR_CSR_APB_MTC_ACQ_RD_DATA_1_TypeDef DDR_CSR_APB_MTC_ACQ_RD_DATA_2_TypeDef DDR_CSR_APB_MTC_ACQ_TRIG_DETECT_TypeDef DDR_CSR_APB_MTC_ACQ_WR_DATA_0_TypeDef DDR_CSR_APB_MTC_ACQ_WR_DATA_1_TypeDef DDR_CSR_APB_MTC_ACQ_WR_DATA_2_TypeDef DDR_CSR_APB_MT_ADDR_BITS_TypeDef DDR_CSR_APB_MT_ADDR_PATTERN_TypeDef DDR_CSR_APB_MT_ALG_AUTO_PCH_TypeDef DDR_CSR_APB_MT_DATA_INVERT_TypeDef DDR_CSR_APB_MT_DATA_PATTERN_TypeDef DDR_CSR_APB_MT_DONE_ACK_TypeDef DDR_CSR_APB_MT_EN_SINGLE_TypeDef DDR_CSR_APB_MT_EN_TypeDef DDR_CSR_APB_MT_ERROR_MASK_0_TypeDef DDR_CSR_APB_MT_ERROR_MASK_1_TypeDef DDR_CSR_APB_MT_ERROR_MASK_2_TypeDef DDR_CSR_APB_MT_ERROR_MASK_3_TypeDef DDR_CSR_APB_MT_ERROR_MASK_4_TypeDef DDR_CSR_APB_MT_ERROR_STS_TypeDef DDR_CSR_APB_MT_RD_ONLY_TypeDef DDR_CSR_APB_MT_START_ADDR_0_TypeDef DDR_CSR_APB_MT_START_ADDR_1_TypeDef DDR_CSR_APB_MT_STOP_ON_ERROR_TypeDef DDR_CSR_APB_MT_USER_DATA_PATTERN_TypeDef DDR_CSR_APB_MT_WR_ONLY_TypeDef DDR_CSR_APB_PHY_CLR_DFI_LVL_PERIODIC_TypeDef DDR_CSR_APB_PHY_DFI_INIT_START_TypeDef DDR_CSR_APB_PHY_ENCODED_QUAD_CS_TypeDef DDR_CSR_APB_PHY_EYE_PAT_TypeDef DDR_CSR_APB_PHY_EYE_TRAIN_DELAY_TypeDef DDR_CSR_APB_PHY_GATE_TRAIN_DELAY_TypeDef DDR_CSR_APB_PHY_HALF_CLK_DLY_ENABLE_TypeDef DDR_CSR_APB_PHY_INDPNDT_TRAINING_TypeDef DDR_CSR_APB_PHY_LPDDR_DQ_CAL_PAT_TypeDef DDR_CSR_APB_PHY_PC_RANK_TypeDef DDR_CSR_APB_PHY_RANKS_TO_TRAIN_TypeDef DDR_CSR_APB_PHY_READ_REQUEST_DONE_TypeDef DDR_CSR_APB_PHY_READ_REQUEST_TypeDef DDR_CSR_APB_PHY_RESET_CONTROL_TypeDef DDR_CSR_APB_PHY_START_RECAL_TypeDef DDR_CSR_APB_PHY_TRAIN_STEP_ENABLE_TypeDef DDR_CSR_APB_PHY_WRITE_LEVEL_DELAY_TypeDef DDR_CSR_APB_PHY_WRITE_REQUEST_DONE_TypeDef DDR_CSR_APB_PHY_WRITE_REQUEST_TypeDef DDR_CSR_APB_STAT_CA_PARITY_ERROR_TypeDef DDR_CSR_APB_STAT_DFI_ERROR_INFO_TypeDef DDR_CSR_APB_STAT_DFI_ERROR_TypeDef DDR_CSR_APB_STAT_DFI_INIT_COMPLETE_TypeDef DDR_CSR_APB_STAT_DFI_LP_ACK_TypeDef DDR_CSR_APB_STAT_DFI_TRAINING_COMPLETE_TypeDef DDR_CSR_APB_STAT_DFI_TRAINING_ERROR_TypeDef DDR_CSR_APB_STAT_INT_ECC_1BIT_THRESH_TypeDef IOSCBCFG_CONTROL__1_TypeDef IOSCBCFG_STATUS_TypeDef IOSCBCFG_TIMER_TypeDef MPU_CFG__bindgen_ty_1 MSS_UART_TypeDef__bindgen_ty_1 MSS_UART_TypeDef__bindgen_ty_2 MSS_UART_TypeDef__bindgen_ty_3 USB_fifo_t USB_indexed_csr_t _CAN_filterobject__bindgen_ty_1 _CAN_filterobject__bindgen_ty_2 _CAN_filterobject__bindgen_ty_3 _CAN_txmsgobject__bindgen_ty_1 _CAN_txmsgobject__bindgen_ty_3 _mss_can_msgobject__bindgen_ty_2 _mss_can_msgobject__bindgen_ty_3 _mss_can_rxmsgobject__bindgen_ty_1 _mss_can_rxmsgobject__bindgen_ty_3 _mss_can_rxmsgobject__bindgen_ty_4 _mss_can_rxmsgobject__bindgen_ty_5 can_config_reg command_reg error_status g5_mss_top_scb_regs_ATHENA_CR_TypeDef g5_mss_top_scb_regs_AXI_CONTROL_TypeDef g5_mss_top_scb_regs_AXI_RADDR_TypeDef g5_mss_top_scb_regs_AXI_RDATA_TypeDef g5_mss_top_scb_regs_AXI_RSETUP_TypeDef g5_mss_top_scb_regs_AXI_STATUS_TypeDef g5_mss_top_scb_regs_AXI_WADDR_TypeDef g5_mss_top_scb_regs_AXI_WDATA_TypeDef g5_mss_top_scb_regs_AXI_WSETUP_TypeDef g5_mss_top_scb_regs_BIST_COMMAND_TypeDef g5_mss_top_scb_regs_BIST_CONFIG_TypeDef g5_mss_top_scb_regs_BIST_DATA_TypeDef g5_mss_top_scb_regs_BOOT_ADDR0_TypeDef g5_mss_top_scb_regs_BOOT_ADDR1_TypeDef g5_mss_top_scb_regs_BOOT_ADDR2_TypeDef g5_mss_top_scb_regs_BOOT_ADDR3_TypeDef g5_mss_top_scb_regs_BOOT_ADDR4_TypeDef g5_mss_top_scb_regs_BOOT_ROM0_TypeDef g5_mss_top_scb_regs_BOOT_ROM1_TypeDef g5_mss_top_scb_regs_BOOT_ROM2_TypeDef g5_mss_top_scb_regs_BOOT_ROM3_TypeDef g5_mss_top_scb_regs_BOOT_ROM4_TypeDef g5_mss_top_scb_regs_BOOT_ROM5_TypeDef g5_mss_top_scb_regs_BOOT_ROM6_TypeDef g5_mss_top_scb_regs_BOOT_ROM7_TypeDef g5_mss_top_scb_regs_DEVICE_CONFIG_CR_TypeDef g5_mss_top_scb_regs_DEVICE_ID_TypeDef g5_mss_top_scb_regs_DEVRST_INT_TypeDef g5_mss_top_scb_regs_DLL0_CTRL0_TypeDef g5_mss_top_scb_regs_DLL0_CTRL1_TypeDef g5_mss_top_scb_regs_DLL0_STAT0_TypeDef g5_mss_top_scb_regs_DLL0_STAT1_TypeDef g5_mss_top_scb_regs_DLL0_STAT2_TypeDef g5_mss_top_scb_regs_DLL0_TEST_TypeDef g5_mss_top_scb_regs_DLL1_CTRL0_TypeDef g5_mss_top_scb_regs_DLL1_CTRL1_TypeDef g5_mss_top_scb_regs_DLL1_STAT0_TypeDef g5_mss_top_scb_regs_DLL1_STAT1_TypeDef g5_mss_top_scb_regs_DLL1_STAT2_TypeDef g5_mss_top_scb_regs_DLL1_TEST_TypeDef g5_mss_top_scb_regs_DLL2_CTRL0_TypeDef g5_mss_top_scb_regs_DLL2_CTRL1_TypeDef g5_mss_top_scb_regs_DLL2_STAT0_TypeDef g5_mss_top_scb_regs_DLL2_STAT1_TypeDef g5_mss_top_scb_regs_DLL2_STAT2_TypeDef g5_mss_top_scb_regs_DLL2_TEST_TypeDef g5_mss_top_scb_regs_DLL3_CTRL0_TypeDef g5_mss_top_scb_regs_DLL3_CTRL1_TypeDef g5_mss_top_scb_regs_DLL3_STAT0_TypeDef g5_mss_top_scb_regs_DLL3_STAT1_TypeDef g5_mss_top_scb_regs_DLL3_STAT2_TypeDef g5_mss_top_scb_regs_DLL3_TEST_TypeDef g5_mss_top_scb_regs_ENVM_CR_TypeDef g5_mss_top_scb_regs_ENVM_POWER_CR_TypeDef g5_mss_top_scb_regs_FLASH_FREEZE_TypeDef g5_mss_top_scb_regs_G5CIO_TypeDef g5_mss_top_scb_regs_MESSAGE_INT_TypeDef g5_mss_top_scb_regs_MESSAGE_TypeDef g5_mss_top_scb_regs_MSSIO_BANK2_CFG_CR_TypeDef g5_mss_top_scb_regs_MSSIO_BANK4_CFG_CR_TypeDef g5_mss_top_scb_regs_MSSIO_CONTROL_CR_TypeDef g5_mss_top_scb_regs_MSSIO_VB2_CFG_TypeDef g5_mss_top_scb_regs_MSSIO_VB4_CFG_TypeDef g5_mss_top_scb_regs_MSS_INTERRUPT_TypeDef g5_mss_top_scb_regs_MSS_IO_LOCKDOWN_CR_TypeDef g5_mss_top_scb_regs_MSS_RESET_CR_TypeDef g5_mss_top_scb_regs_MSS_STATUS_TypeDef g5_mss_top_scb_regs_RAM_MARGIN_CR_TypeDef g5_mss_top_scb_regs_RAM_SHUTDOWN_CR_TypeDef g5_mss_top_scb_regs_REDUNDANCY_TypeDef g5_mss_top_scb_regs_SCB_INTERRUPT_TypeDef g5_mss_top_scb_regs_SOFT_RESET_TypeDef g5_mss_top_scb_regs_TRACE_CR_TypeDef int_enable int_status seg_t__bindgen_ty_1