Struct MathAccelerator 

#[repr(C, packed(1))]
pub struct MathAccelerator {
    pub divout_fraction: RO<u32>,
    pub divout_whole: RO<u32>,
    pub multin_a: WO<u32>,
    pub multin_b: WO<u32>,
    pub multout: RO<u64>,
}

Registers for Math Acceleration

See the MEGA64 book, Section G-19. The hardware registers use little endian storage.

Fields

divout_fraction: RO<u32>

32-bit fractional part DIVOUT(0-3) of MULTINA divided by MULTINB

divout_whole: RO<u32>

32-bit whole part DIVOUT(4-7) of MULTINA divided by MULTINB

multin_a: WO<u32>

32-bit input A

multin_b: WO<u32>

32-bit input B

multout: RO<u64>

64-bit product MULTOUT of MULTINA and MULTINB

Implementations

impl MathAccelerator

pub fn multiply(&self, a: u32, b: u32) -> u64

32 bit multiplication using hardware multiplier

Cycles: 1

pub fn multiply_divide(&self, a: u32, b: u32) -> (u64, u32, u32)

32 bit multiplication and division using hardware multiplier

Returns a tuple with:

1. 64-bit a x b product
2. 32-bit whole part of a / b;
3. 32-bit fractional part of a / b

Cycles: less than 20