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A lexical analyzer and parser for VHDL source files as per IEEE 1076-2008.


This module implements an abstract syntax tree for VHDL. It is emitted by the parser.

A VHDL lexer. This module implements lexical analysis of VHDL source files. It converts a stream of input bytes into a stream of language tokens such as identifiers, literals, and symbols.

A VHDL parser.