Module moore_vhdl_syntax::ast
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This module implements an abstract syntax tree for VHDL. It is emitted by the parser.
Re-exports
Structs
An alias declaration.
An architecture body.
A configuration declaration.
A component declaration.
A compound name consisting of a primary name (identifier, character literal, or string literal), and zero or more suffices (select, attribute, call). The names in IEEE 1076-2008 section 8.1 map to this as follows:
A conditional wave.
A context declaration.
A design unit. Multiple design units make up a design file. Each unit consists of an optional context clause followed by a primary or secondary unit.
An entity declaration.
An expression.
An identifier. Has a node ID such that it may be referenced later on.
An interface object declaration.
A positive, small ID assigned to each node in the AST. Used as a lightweight way to refer to individual nodes, e.g. during symbol table construction and name resolution.
A parenthesized expression element. A parenthesized expression contains
elements of which each may either be a simple <expr>, or an association of
the form <choices> => <expr>.
A package body.
A package declaration.
A package instantiation declaration.
A selected wave. The second element of the tuple represents the choices for which this wave would be selected.
The body of an if, loop, or case statement.
A type declaration. If the data field is omitted, this is an incomplete
declaration.
Enums
A context item, multiple of which make up a context clause.
A declarative item.
The data associated with a specific expression.
An interface declaration.
Additional mutually exclusive details that may be provided with an object declaration.
Constants
During parsing and syntax tree construction, we assign each node this ID. Only later, during the renumbering pass do we assign actual IDs to each node.
Type Definitions
A vector of parenthesized expression elements, including the span of the expression that this would cover.