Struct USB0_EP_OUT 

pub struct USB0_EP_OUT { /* private fields */ }

usb0_ep_out

Implementations

impl USB0_EP_OUT

pub const PTR: *const RegisterBlock = {0xf0000b00 as *const generated::usb0_ep_out::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> Self

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn control(&self) -> &CONTROL

0x00 - Control register address: Controls the current device’s USB address. Should be written after a SET_ADDRESS request is received. Automatically resets back to zero on a USB reset.

pub fn endpoint(&self) -> &ENDPOINT

0x01 - Endpoint register number: Selects the endpoint number to prime. This interface allows priming multiple endpoints at once. That is, multiple endpoints can be ready to receive data at a time. See the prime and enable bits for usage.

pub fn enable(&self) -> &ENABLE

0x02 - Enable register enabled: Controls whether any data can be received on any primed OUT endpoint. This bit is automatically cleared on receive in order to give the controller time to read data from the FIFO. It must be re-enabled once the FIFO has been emptied.

pub fn prime(&self) -> &PRIME

0x03 - Prime register primed: Controls “priming” an out endpoint. To receive data on any endpoint, the CPU must first select the endpoint with the epno register; and then write a ‘1’ into the prime and enable register. This prepares our FIFO to receive data; and the next OUT transaction will be captured into the FIFO. When a transaction is complete, the enable bit is reset; the prime is not. This effectively means that enable controls receiving on any of the primed endpoints; while prime can be used to build a collection of endpoints willing to participate in receipt. Note that this does not apply to the control endpoint. Once the control endpoint has received a packet it will be un-primed and need to be re-primed before it can receive again. This is to ensure that we can establish an order on the receipt of the setup packet and any associated data. Only one transaction / data packet is captured per enable write; repeated enabling is necessary to capture multiple packets.

pub fn stall(&self) -> &STALL

0x04 - Stall register stalled: Controls STALL’ing the active endpoint. Setting or clearing this bit will set or clear STALL on the provided endpoint. Endpoint STALLs persist even after epno is changed; so multiple endpoints can be stalled at once by writing their respective endpoint numbers into epno register and then setting their stall bits.

pub fn pid(&self) -> &PID

0x05 - Pid register toggle: Sets the current PID toggle bit for the given endpoint.

pub fn status(&self) -> &STATUS

0x06 - Status register epno: Contains the endpoint number associated with the data in the FIFO – that is, the endpoint number on which the relevant data was received. have: 1 iff data is available in the FIFO. pid: Contains the current PID toggle bit for the given endpoint.

pub fn reset(&self) -> &RESET

0x08 - Reset register fifo: Local reset for the OUT handler; clears the out FIFO.

pub fn data(&self) -> &DATA

0x09 - Data register Read-only register. A FIFO that returns the bytes from the most recently captured OUT transaction. Reading a byte from this register advances the FIFO. byte: Contains the most recently received byte.

pub fn ev_enable(&self) -> &EV_ENABLE

0x20 - A CSR register. Parameters ––––– fields : :class:dict or :class:list or :class:Field Collection of register fields. If None (default), a dict is populated from Python :term:variable annotations <python:variable annotations>. fields is used to create a :class:FieldActionMap, :class:FieldActionArray, or :class:FieldAction, depending on its type (dict, list, or Field). Interface attributes –––––––––– element : :class:Element Interface between this register and a CSR bus primitive. Attributes ––––– field : :class:FieldActionMap or :class:FieldActionArray or :class:FieldAction Collection of field instances. f : :class:FieldActionMap or :class:FieldActionArray or :class:FieldAction Shorthand for :attr:Register.field. Raises —— :exc:TypeError If fields is neither None, a :class:dict, a :class:list, or a :class:Field. :exc:ValueError If fields is not None and at least one variable annotation is a :class:Field. :exc:ValueError If element.access is not readable and at least one field is readable. :exc:ValueError If element.access is not writable and at least one field is writable.

pub fn ev_pending(&self) -> &EV_PENDING

0x21 - A CSR register. Parameters ––––– fields : :class:dict or :class:list or :class:Field Collection of register fields. If None (default), a dict is populated from Python :term:variable annotations <python:variable annotations>. fields is used to create a :class:FieldActionMap, :class:FieldActionArray, or :class:FieldAction, depending on its type (dict, list, or Field). Interface attributes –––––––––– element : :class:Element Interface between this register and a CSR bus primitive. Attributes ––––– field : :class:FieldActionMap or :class:FieldActionArray or :class:FieldAction Collection of field instances. f : :class:FieldActionMap or :class:FieldActionArray or :class:FieldAction Shorthand for :attr:Register.field. Raises —— :exc:TypeError If fields is neither None, a :class:dict, a :class:list, or a :class:Field. :exc:ValueError If fields is not None and at least one variable annotation is a :class:Field. :exc:ValueError If element.access is not readable and at least one field is readable. :exc:ValueError If element.access is not writable and at least one field is writable.

Trait Implementations

impl Debug for USB0_EP_OUT

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Deref for USB0_EP_OUT

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl Send for USB0_EP_OUT