RegisterBlock

mm32f5::rcc

Struct RegisterBlock 

Source 
pub struct RegisterBlock {
Show 20 fields
    pub cr: CR,
    pub cfgr: CFGR,
    pub cir: CIR,
    pub ahb1rstr: AHB1RSTR,
    pub apb2rstr: APB2RSTR,
    pub apb1rstr: APB1RSTR,
    pub ahb1enr: AHB1ENR,
    pub apb2enr: APB2ENR,
    pub apb1enr: APB1ENR,
    pub bdcr: BDCR,
    pub csr: CSR,
    pub syscfg: SYSCFG,
    pub cfgr2: CFGR2,
    pub pll1cfgr: PLL1CFGR,
    pub pll2cfgr: PLL2CFGR,
    pub adc1cfgr: ADC1CFGR,
    pub adc2cfgr: ADC2CFGR,
    pub daccfgr: DACCFGR,
    pub fsmccfgr: FSMCCFGR,
    pub tpiucfgr: TPIUCFGR,
    /* private fields */

}
Expand description

Register block

Fields§

§cr: CR

0x00 - clock control register

§cfgr: CFGR

0x04 - Clock Configuration Register

§cir: CIR

0x08 - clock interrupt register

§ahb1rstr: AHB1RSTR

0x14 - AHB1 Peripheral Reset Register

§apb2rstr: APB2RSTR

0x18 - APB2 Peripheral Reset Register

§apb1rstr: APB1RSTR

0x1c - APB1 Peripheral Reset Register

§ahb1enr: AHB1ENR

0x28 - AHB1 peripheral clock enable register

§apb2enr: APB2ENR

0x2c - APB2 Peripheral Clock Enable Register

§apb1enr: APB1ENR

0x30 - APB1 Peripheral Clock Enable Register

§bdcr: BDCR

0x34 - Backup Domain Control Register

§csr: CSR

0x38 - Control Status Register

§syscfg: SYSCFG

0x3c - System Configuration Register

§cfgr2: CFGR2

0x40 - Clock Configuration Register 2

§pll1cfgr: PLL1CFGR

0x48 - PLL1 Configuration Register

§pll2cfgr: PLL2CFGR

0x4c - PLL2 Configuration Register

§adc1cfgr: ADC1CFGR

0x60 - ADC1 Configuration Register

§adc2cfgr: ADC2CFGR

0x64 - ADC2 Configuration Register

§daccfgr: DACCFGR

0x70 - DAC Configuration Register

§fsmccfgr: FSMCCFGR

0x78 - FSMC Configuration Register

§tpiucfgr: TPIUCFGR

0x7c - TPIU configuration register

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