RegisterBlock

mm32f5::dac

Struct RegisterBlock 

Source 
#[repr(C)]
pub struct RegisterBlock {
Show 13 fields
    pub cr: CR,
    pub swtrigr: SWTRIGR,
    pub dhr12r1: DHR12R1,
    pub dhr12l1: DHR12L1,
    pub dhr8r1: DHR8R1,
    pub dhr12r2: DHR12R2,
    pub dhr12l2: DHR12L2,
    pub dhr8r2: DHR8R2,
    pub dhr12rd: DHR12RD,
    pub dhr12ld: DHR12LD,
    pub dhr8rd: DHR8RD,
    pub dor1: DOR1,
    pub dor2: DOR2,

}
Expand description

Register block

Fields§

§cr: CR

0x00 - DAC Control Register

§swtrigr: SWTRIGR

0x04 - DAC Software Trigger Register

§dhr12r1: DHR12R1

0x08 - 12-Bit Right-Justified Data Holding Register for DAC Channel 1

§dhr12l1: DHR12L1

0x0c - 12-Bit Left-Justified Data Holding Register for DAC Channel 1

§dhr8r1: DHR8R1

0x10 - 8-Bit Right-Justified Data Holding Register for DAC Channel 1

§dhr12r2: DHR12R2

0x14 - 12-Bit Right-Justified Data Holding Register for DAC Channel 2

§dhr12l2: DHR12L2

0x18 - 12-Bit Left-Justified Data Holding Register for DAC Channel 2

§dhr8r2: DHR8R2

0x1c - 8-Bit Right-Justified Data Holding Register for DAC Channel 2

§dhr12rd: DHR12RD

0x20 - 12-Bit Right-Justified Data Holding Registers for Dual DACs

§dhr12ld: DHR12LD

0x24 - 12-Bit Left-Justified Data Holding Registers for Dual DACs

§dhr8rd: DHR8RD

0x28 - 8-Bit Right-Justified Data Holding Registers for Dual DACs

§dor1: DOR1

0x2c - DAC Channel 1 Data Output Register

§dor2: DOR2

0x30 - DAC Channel 2 Data Output Register

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