Enum PLLSW 

pub enum PLLSW {
    _0,
    _1,
}

Values that can be written to the field PLLS

Variants

_0

FLL is selected.

_1

PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2 - 4 MHz prior to setting the PLLS bit).