Enum ClockGating 

pub enum ClockGating {
    ClockEnable,
    IntegratedClockGate,
}

Clock gating approach.

FPGA and ASIC handle clock gating differently at the cell level.

Variants

ClockEnable

Use a clock enable signal (FPGA style).

The clock runs continuously; a CE pin on the flip-flop controls whether it captures new data.

IntegratedClockGate

Use an integrated clock gating cell (ASIC style).

A dedicated ICG cell gates the clock tree, reducing dynamic power consumption.

Trait Implementations

impl Clone for ClockGating

fn clone(&self) -> ClockGating

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for ClockGating

impl Debug for ClockGating

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for ClockGating

impl Hash for ClockGating

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for ClockGating

fn eq(&self, other: &ClockGating) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl StructuralPartialEq for ClockGating