Enum RtcSubsecEna 

pub enum RtcSubsecEna {
    Disable = 0,
    Enable = 1,
}

The 32 KHz sub-second counter enable

Value on reset: 0

Variants

Disable = 0

0: The sub-second counter (if implemented) is disabled. This bit is cleared by a system-level POR or BOD reset as well as a by the RTC_ENA bit (bit 7 in this register). On modules not equipped with a sub-second counter, this bit will always read-back as a ‘0’

Enable = 1

1: The 32 KHz sub-second counter is enabled (if implemented). Counting will commence on the start of the first one-second interval after this bit is set. Note: This bit can only be set after the RTC_ENA bit (bit 7) has been set by a previous write operation. Note: The RTC sub-second counter must be re-enabled whenever the chip exits deep_powerdown mode.

Trait Implementations

impl Clone for RtcSubsecEna

fn clone(&self) -> RtcSubsecEna

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for RtcSubsecEna

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<RtcSubsecEna> for bool

fn from(variant: RtcSubsecEna) -> Self

Converts to this type from the input type.

impl PartialEq for RtcSubsecEna

fn eq(&self, other: &RtcSubsecEna) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for RtcSubsecEna

impl Eq for RtcSubsecEna

impl StructuralPartialEq for RtcSubsecEna