Struct Spi3

pub struct Spi3 { /* private fields */ }

LPC_Next0 Serial Peripheral Interfaces (SPI)

Implementations

impl Spi3

pub const PTR: *const RegisterBlock = {0x40109000 as *const spi0::RegisterBlock}

Pointer to the register block

pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

pub unsafe fn steal() -> Self

Steal an instance of this peripheral

Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>

pub fn cfg(&self) -> &Cfg

0x400 - SPI Configuration register

pub fn dly(&self) -> &Dly

0x404 - SPI Delay register

pub fn stat(&self) -> &Stat

0x408 - SPI Status. Some status flags can be cleared by writing a 1 to that bit position.

pub fn intenset(&self) -> &Intenset

0x40c - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.

pub fn intenclr(&self) -> &Intenclr

0x410 - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.

pub fn div(&self) -> &Div

0x424 - SPI clock Divider

pub fn intstat(&self) -> &Intstat

0x428 - SPI Interrupt Status

pub fn fifocfg(&self) -> &Fifocfg

0xe00 - FIFO configuration and enable register.

pub fn fifostat(&self) -> &Fifostat

0xe04 - FIFO status register.

pub fn fifotrig(&self) -> &Fifotrig

0xe08 - FIFO trigger settings for interrupt and DMA request.

pub fn fifointenset(&self) -> &Fifointenset

0xe10 - FIFO interrupt enable set (enable) and read register.

pub fn fifointenclr(&self) -> &Fifointenclr

0xe14 - FIFO interrupt enable clear (disable) and read register.

pub fn fifointstat(&self) -> &Fifointstat

0xe18 - FIFO interrupt status register.

pub fn fifowr(&self) -> &Fifowr

0xe20 - FIFO write data.

pub fn fiford(&self) -> &Fiford

0xe30 - FIFO read data.

pub fn fifordnopop(&self) -> &Fifordnopop

0xe40 - FIFO data read with no FIFO pop.

pub fn fifosize(&self) -> &Fifosize

0xe48 - FIFO size register

pub fn id(&self) -> &Id

0xffc - Peripheral identification register.

Trait Implementations

impl Debug for Spi3

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Deref for Spi3

type Target = RegisterBlock

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl Send for Spi3