Struct DflashDraft 

pub struct DflashDraft {
    pub cfg: DflashCfg,
    pub layers: Vec<DflashLayer>,
    pub fc: GpuTensor,
    pub hidden_norm: CudaSlice<f32>,
    pub norm: CudaSlice<f32>,
    pub markov: Option<MarkovHead>,
}

Fields

cfg: DflashCfg

layers: Vec<DflashLayer>

fc: GpuTensor

hidden_norm: CudaSlice<f32>

norm: CudaSlice<f32>

markov: Option<MarkovHead>

DSpark semi-AR markov head (present in the repo-root checkpoint variant): draft logits at position k get + W2(W1[prev_realized_token]) — left-to-right within the block (the patch’s _markov_semiar_sample_block semantics, greedy). w1 = raw bf16 [V, rank] (row-gathered by device token id); w2 = q8_0 [rank->V].

Implementations

impl DflashDraft

pub fn load(e: &Engine, dir: &Path) -> Result<Self, Box<dyn Error>>

Load the backbone-only checkpoint dir (config.json + model.safetensors, bf16). Config scalars ride a minimal extractor (no json dep in-tree — HfConfig precedent).

pub fn ctx_features( &self, e: &Engine, taps: &CudaSlice<f32>, t: usize, ) -> Result<CudaSlice<f32>, Box<dyn Error>>

FIRST-LIGHT forward (oracle contract): full non-causal attention over [ctx_features ; block], NO draft KV cache, NO sliding window (the oracle bypasses the reference mask machinery the same way — window/caching land in the round arm).

target_hidden: [ctx, n_taps*hidden] (f32, device) — raw tapped states. noise_emb: [block, hidden] — target embed rows for [accepted, MASK x b-1]. pos: absolute positions for ctx rows THEN block rows (ctx+block i32). Returns final normed hidden [block, hidden] (feed target lm_head for draft logits). ctx features for t tapped rows: hidden_norm(fc(taps)) — the drafter’s context representation, cacheable across rounds (append-only in committed-token order).

pub fn forward( &self, e: &Engine, target_hidden: &CudaSlice<f32>, noise_emb: &CudaSlice<f32>, pos: &[i32], ctx: usize, ) -> Result<CudaSlice<f32>, Box<dyn Error>>

pub fn forward_block( &self, e: &Engine, ctx_f: &CudaSlice<f32>, noise_emb: &CudaSlice<f32>, pos: &[i32], ctx: usize, ) -> Result<CudaSlice<f32>, Box<dyn Error>>

Block forward over PRECOMPUTED ctx features (the round arm’s entry: features are cached across rounds; only the block work repeats).

impl DflashDraft

pub fn ingest_ctx( &self, e: &Engine, kv: &mut DflashKv, feats: &CudaSlice<f32>, pos_new: &[i32], t: usize, ) -> Result<(), Box<dyn Error>>

Ingest t NEW ctx-feature rows (committed order, absolute positions pos_new) into the draft KV: per layer k/v projections + k head-norm + rope, appended at kv.len.

pub fn forward_round( &self, e: &Engine, kv: &mut DflashKv, noise_emb: &CudaSlice<f32>, pos_block: &[i32], ) -> Result<CudaSlice<f32>, Box<dyn Error>>

Block forward over the CACHED ctx KV: only the 16 block rows are projected per layer; block K/V land transiently at kv[len..len+b]. Bit-class-identical to forward_block (same kernels, same per-row programs; ONLY the ctx K/V recompute is cached).