Struct DevExps 

pub struct DevExps {
    pub gate: CudaSlice<u8>,
    pub up: CudaSlice<u8>,
    pub down: CudaSlice<u8>,
    pub ptr_row: CudaSlice<u64>,
    pub dev: usize,
    pub rp: bool,
    pub fp8_blk: Option<DevExpertFp8BlockScales>,
}

Device-resident expert slabs for one layer (gate/up/down) + the prebuilt [3, n_expert] pointer row the _dev kernels consume.

Fields

gate: CudaSlice<u8>

up: CudaSlice<u8>

down: CudaSlice<u8>

ptr_row: CudaSlice<u64>

[3*n_expert] u64 device row: gate ptrs, up ptrs, down ptrs (proj-major like layer_dev_row).

dev: usize

The CUDA device ordinal these slabs live on (the OWNING stage’s device under the PP sharded loader — cx-503b sizes and layer_engine places per device). Consumers that dispatch from a DIFFERENT device must NOT dereference the slabs: an m=1 qmatvec over peer-read expert bytes is the measured 34-150x slow class (research/pp-prefill-20260807 anatomy), strictly worse than SLRU staging. The sequential arm’s slab-locality gate (lane/pp-leverb) keys on this field; the per-stage prime walker makes every layer’s slab local by construction.

rp: bool

The three slabs are slot-major per row (QT_NVFP4_V2; MEMRA_MOE_EXPERT_RP, memra#147): readers must be told so (crate::rp_qt) or refuse (crate::moe_rp_refuse).

fp8_blk: Option<DevExpertFp8BlockScales>

Native block-E4M3 expert scale slabs, projection-major. When present, the raw checkpoint code slabs above are the sole resident weight copy and each expert selects its contiguous scale-grid view.