Struct LatentPlaneSnapshot 

pub struct LatentPlaneSnapshot {
    pub rows: CudaSlice<f32>,
    pub width: usize,
    pub len: usize,
    pub index_width: usize,
    pub index_pool: usize,
    pub index_tail: Option<CudaSlice<f32>>,
    pub index_pool_keys: Option<CudaSlice<f32>>,
    pub index_pools_ready: usize,
}

One MLA/DSA layer’s captured latent-plane state: everything mla_attn_cached + mla_kpool_indices need to continue as if the destination session had primed the prefix itself (lane/glm5-prefix-latent, 2026-08-30; design in research/glm5-prefix-latent-20260830/DESIGN.md).

The three asymmetries against an ordinary PrefixPlane, and how each is carried:

• rows is deliberately UNQUANTIZED f32 (the maxdiff oracle depends on the f32 plane), so the copy is f32-for-f32 — no quantization program is introduced at the snapshot seam.
• index_rows is a TAIL RING whose rows below index_pools_ready * pool are OVERWRITTEN by design, so “the index plane” is not copyable and not rebuildable: the snapshot carries the DERIVED keys (final by the append-only invariant, bit-identical to a rebuild) plus the len % pool still-live tail rows (index_tail, at most pool - 1 rows).
• index_pool_keys / index_pools_ready carry the append-only finality invariant, so the capture asserts index_pools_ready == len / pool (every call boundary leaves the drain there) and the restore re-establishes both, keeping the engine’s residency tripwire and index_ring_take arithmetic blind to the fact that a restore happened.

Fields

rows: CudaSlice<f32>

Rows [0..len) of the latent plane, len * width f32.

width: usize

len: usize

index_width: usize

0 = the layer has no indexer state plane (and every index_* field below is empty).

index_pool: usize

The indexer’s pool size at capture (LatentKvLayer::index_pool); 0 iff no indexer.

index_tail: Option<CudaSlice<f32>>

The live tail-ring rows [index_pools_ready * pool, len), (len % pool) * index_width f32; None when the boundary is pool-aligned.

index_pool_keys: Option<CudaSlice<f32>>

The FINAL pool keys [0..index_pools_ready * d), d = index_width / 2; None when no pool has completed.

index_pools_ready: usize

Implementations

impl LatentPlaneSnapshot

pub fn bytes(&self) -> usize

Device bytes this snapshot holds, for the prefix cache’s byte ledger. The defective pre-lane entry cost ZERO bytes per token; this is the honest bill.