Struct mcxn947_pac::Peripherals

source · 
pub struct Peripherals {
Show 154 fields
    pub SYSCON0: SYSCON0,
    pub PINT0: PINT0,
    pub INPUTMUX0: INPUTMUX0,
    pub CTIMER0: CTIMER0,
    pub CTIMER1: CTIMER1,
    pub CTIMER2: CTIMER2,
    pub CTIMER3: CTIMER3,
    pub CTIMER4: CTIMER4,
    pub FREQME0: FREQME0,
    pub UTICK0: UTICK0,
    pub MRT0: MRT0,
    pub WWDT0: WWDT0,
    pub WWDT1: WWDT1,
    pub CACHE64_CTRL0: CACHE64_CTRL0,
    pub CACHE64_POLSEL0: CACHE64_POLSEL0,
    pub I3C0: I3C0,
    pub I3C1: I3C1,
    pub GDET0: GDET0,
    pub GDET1: GDET1,
    pub ITRC0: ITRC0,
    pub PKC0: PKC0,
    pub PUF: PUF,
    pub PUF_CTRL: PUF_CTRL,
    pub SM3_0: SM3_0,
    pub BSP32_0: BSP32_0,
    pub SMARTDMA0: SMARTDMA0,
    pub PLU0: PLU0,
    pub PORT0: PORT0,
    pub PORT5: PORT5,
    pub FMU0: FMU0,
    pub SCG0: SCG0,
    pub SPC0: SPC0,
    pub WUU0: WUU0,
    pub CMC0: CMC0,
    pub OSTIMER0: OSTIMER0,
    pub LPTMR0: LPTMR0,
    pub LPTMR1: LPTMR1,
    pub RTC0: RTC0,
    pub RTC_SUBSYSTEM0: RTC_SUBSYSTEM0,
    pub TSI0: TSI0,
    pub CMP0: CMP0,
    pub CMP1: CMP1,
    pub CMP2: CMP2,
    pub ELS: ELS,
    pub TDET0: TDET0,
    pub VBAT0: VBAT0,
    pub TRNG0: TRNG0,
    pub EIM0: EIM0,
    pub ERM0: ERM0,
    pub INTM0: INTM0,
    pub DMA0: DMA0,
    pub DMA1: DMA1,
    pub EDMA_0_TCD: EDMA_0_TCD,
    pub SCT0: SCT0,
    pub LPSPI0: LPSPI0,
    pub LPSPI1: LPSPI1,
    pub LPSPI2: LPSPI2,
    pub LPSPI3: LPSPI3,
    pub LPSPI4: LPSPI4,
    pub LPSPI5: LPSPI5,
    pub LPSPI6: LPSPI6,
    pub LPSPI7: LPSPI7,
    pub LPSPI8: LPSPI8,
    pub LPSPI9: LPSPI9,
    pub LPUART0: LPUART0,
    pub LPUART1: LPUART1,
    pub LPUART2: LPUART2,
    pub LPUART3: LPUART3,
    pub LPUART4: LPUART4,
    pub LPUART5: LPUART5,
    pub LPUART6: LPUART6,
    pub LPUART7: LPUART7,
    pub LPUART8: LPUART8,
    pub LPUART9: LPUART9,
    pub LP_FLEXCOMM0: LP_FLEXCOMM0,
    pub LP_FLEXCOMM1: LP_FLEXCOMM1,
    pub LP_FLEXCOMM2: LP_FLEXCOMM2,
    pub LP_FLEXCOMM3: LP_FLEXCOMM3,
    pub LP_FLEXCOMM4: LP_FLEXCOMM4,
    pub LP_FLEXCOMM5: LP_FLEXCOMM5,
    pub LP_FLEXCOMM6: LP_FLEXCOMM6,
    pub LP_FLEXCOMM7: LP_FLEXCOMM7,
    pub LP_FLEXCOMM8: LP_FLEXCOMM8,
    pub LP_FLEXCOMM9: LP_FLEXCOMM9,
    pub LPI2C0: LPI2C0,
    pub LPI2C1: LPI2C1,
    pub LPI2C2: LPI2C2,
    pub LPI2C3: LPI2C3,
    pub LPI2C4: LPI2C4,
    pub LPI2C5: LPI2C5,
    pub LPI2C6: LPI2C6,
    pub LPI2C7: LPI2C7,
    pub LPI2C8: LPI2C8,
    pub LPI2C9: LPI2C9,
    pub GPIO0: GPIO0,
    pub GPIO5: GPIO5,
    pub GPIO1: GPIO1,
    pub GPIO2: GPIO2,
    pub GPIO3: GPIO3,
    pub GPIO4: GPIO4,
    pub EDMA_1_TCD: EDMA_1_TCD,
    pub SEMA42_0: SEMA42_0,
    pub MAILBOX: MAILBOX,
    pub CDOG0: CDOG0,
    pub CDOG1: CDOG1,
    pub DM0: DM0,
    pub POWERQUAD: POWERQUAD,
    pub EWM0: EWM0,
    pub CMX_PERFMON0: CMX_PERFMON0,
    pub CMX_PERFMON1: CMX_PERFMON1,
    pub TRDC: TRDC,
    pub FLEXSPI0: FLEXSPI0,
    pub OTPC0: OTPC0,
    pub CRC0: CRC0,
    pub NPX0: NPX0,
    pub PWM0: PWM0,
    pub PWM1: PWM1,
    pub ENC0: ENC0,
    pub ENC1: ENC1,
    pub EVTG0: EVTG0,
    pub CAN0: CAN0,
    pub CAN1: CAN1,
    pub USBDCD0: USBDCD0,
    pub USBFS0: USBFS0,
    pub ENET0: ENET0,
    pub EMVSIM0: EMVSIM0,
    pub EMVSIM1: EMVSIM1,
    pub FLEXIO0: FLEXIO0,
    pub SAI0: SAI0,
    pub SAI1: SAI1,
    pub SINC0: SINC0,
    pub USDHC0: USDHC0,
    pub USBPHY: USBPHY,
    pub USBHS1_PHY_DCD: USBHS1_PHY_DCD,
    pub USBHS1__USBC: USBHS1__USBC,
    pub USBHS1__USBNC: USBHS1__USBNC,
    pub PDM: PDM,
    pub ADC0: ADC0,
    pub ADC1: ADC1,
    pub DAC0: DAC0,
    pub DAC1: DAC1,
    pub OPAMP0: OPAMP0,
    pub OPAMP1: OPAMP1,
    pub OPAMP2: OPAMP2,
    pub VREF0: VREF0,
    pub DAC2: DAC2,
    pub PORT1: PORT1,
    pub PORT2: PORT2,
    pub PORT3: PORT3,
    pub PORT4: PORT4,
    pub AHBSC: AHBSC,
    pub SCN_SCB: SCN_SCB,
    pub SYS_TICK0: SYS_TICK0,
    pub SAU: SAU,

}
Expand description

All the peripherals.

Fields§

§SYSCON0: SYSCON0

SYSCON0

§PINT0: PINT0

PINT0

§INPUTMUX0: INPUTMUX0

INPUTMUX0

§CTIMER0: CTIMER0

CTIMER0

§CTIMER1: CTIMER1

CTIMER1

§CTIMER2: CTIMER2

CTIMER2

§CTIMER3: CTIMER3

CTIMER3

§CTIMER4: CTIMER4

CTIMER4

§FREQME0: FREQME0

FREQME0

§UTICK0: UTICK0

UTICK0

§MRT0: MRT0

MRT0

§WWDT0: WWDT0

WWDT0

§WWDT1: WWDT1

WWDT1

§CACHE64_CTRL0: CACHE64_CTRL0

CACHE64_CTRL0

§CACHE64_POLSEL0: CACHE64_POLSEL0

CACHE64_POLSEL0

§I3C0: I3C0

I3C0

§I3C1: I3C1

I3C1

§GDET0: GDET0

GDET0

§GDET1: GDET1

GDET1

§ITRC0: ITRC0

ITRC0

§PKC0: PKC0

PKC0

§PUF: PUF

PUF

§PUF_CTRL: PUF_CTRL

PUF_CTRL

§SM3_0: SM3_0

SM3_0

§BSP32_0: BSP32_0

BSP32_0

§SMARTDMA0: SMARTDMA0

SMARTDMA0

§PLU0: PLU0

PLU0

§PORT0: PORT0

PORT0

§PORT5: PORT5

PORT5

§FMU0: FMU0

FMU0

§SCG0: SCG0

SCG0

§SPC0: SPC0

SPC0

§WUU0: WUU0

WUU0

§CMC0: CMC0

CMC0

§OSTIMER0: OSTIMER0

OSTIMER0

§LPTMR0: LPTMR0

LPTMR0

§LPTMR1: LPTMR1

LPTMR1

§RTC0: RTC0

RTC0

§RTC_SUBSYSTEM0: RTC_SUBSYSTEM0

RTC_SUBSYSTEM0

§TSI0: TSI0

TSI0

§CMP0: CMP0

CMP0

§CMP1: CMP1

CMP1

§CMP2: CMP2

CMP2

§ELS: ELS

ELS

§TDET0: TDET0

TDET0

§VBAT0: VBAT0

VBAT0

§TRNG0: TRNG0

TRNG0

§EIM0: EIM0

EIM0

§ERM0: ERM0

ERM0

§INTM0: INTM0

INTM0

§DMA0: DMA0

DMA0

§DMA1: DMA1

DMA1

§EDMA_0_TCD: EDMA_0_TCD

EDMA_0_TCD

§SCT0: SCT0

SCT0

§LPSPI0: LPSPI0

LPSPI0

§LPSPI1: LPSPI1

LPSPI1

§LPSPI2: LPSPI2

LPSPI2

§LPSPI3: LPSPI3

LPSPI3

§LPSPI4: LPSPI4

LPSPI4

§LPSPI5: LPSPI5

LPSPI5

§LPSPI6: LPSPI6

LPSPI6

§LPSPI7: LPSPI7

LPSPI7

§LPSPI8: LPSPI8

LPSPI8

§LPSPI9: LPSPI9

LPSPI9

§LPUART0: LPUART0

LPUART0

§LPUART1: LPUART1

LPUART1

§LPUART2: LPUART2

LPUART2

§LPUART3: LPUART3

LPUART3

§LPUART4: LPUART4

LPUART4

§LPUART5: LPUART5

LPUART5

§LPUART6: LPUART6

LPUART6

§LPUART7: LPUART7

LPUART7

§LPUART8: LPUART8

LPUART8

§LPUART9: LPUART9

LPUART9

§LP_FLEXCOMM0: LP_FLEXCOMM0

LP_FLEXCOMM0

§LP_FLEXCOMM1: LP_FLEXCOMM1

LP_FLEXCOMM1

§LP_FLEXCOMM2: LP_FLEXCOMM2

LP_FLEXCOMM2

§LP_FLEXCOMM3: LP_FLEXCOMM3

LP_FLEXCOMM3

§LP_FLEXCOMM4: LP_FLEXCOMM4

LP_FLEXCOMM4

§LP_FLEXCOMM5: LP_FLEXCOMM5

LP_FLEXCOMM5

§LP_FLEXCOMM6: LP_FLEXCOMM6

LP_FLEXCOMM6

§LP_FLEXCOMM7: LP_FLEXCOMM7

LP_FLEXCOMM7

§LP_FLEXCOMM8: LP_FLEXCOMM8

LP_FLEXCOMM8

§LP_FLEXCOMM9: LP_FLEXCOMM9

LP_FLEXCOMM9

§LPI2C0: LPI2C0

LPI2C0

§LPI2C1: LPI2C1

LPI2C1

§LPI2C2: LPI2C2

LPI2C2

§LPI2C3: LPI2C3

LPI2C3

§LPI2C4: LPI2C4

LPI2C4

§LPI2C5: LPI2C5

LPI2C5

§LPI2C6: LPI2C6

LPI2C6

§LPI2C7: LPI2C7

LPI2C7

§LPI2C8: LPI2C8

LPI2C8

§LPI2C9: LPI2C9

LPI2C9

§GPIO0: GPIO0

GPIO0

§GPIO5: GPIO5

GPIO5

§GPIO1: GPIO1

GPIO1

§GPIO2: GPIO2

GPIO2

§GPIO3: GPIO3

GPIO3

§GPIO4: GPIO4

GPIO4

§EDMA_1_TCD: EDMA_1_TCD

EDMA_1_TCD

§SEMA42_0: SEMA42_0

SEMA42_0

§MAILBOX: MAILBOX

MAILBOX

§CDOG0: CDOG0

CDOG0

§CDOG1: CDOG1

CDOG1

§DM0: DM0

DM0

§POWERQUAD: POWERQUAD

POWERQUAD

§EWM0: EWM0

EWM0

§CMX_PERFMON0: CMX_PERFMON0

CMX_PERFMON0

§CMX_PERFMON1: CMX_PERFMON1

CMX_PERFMON1

§TRDC: TRDC

TRDC

§FLEXSPI0: FLEXSPI0

FLEXSPI0

§OTPC0: OTPC0

OTPC0

§CRC0: CRC0

CRC0

§NPX0: NPX0

NPX0

§PWM0: PWM0

PWM0

§PWM1: PWM1

PWM1

§ENC0: ENC0

ENC0

§ENC1: ENC1

ENC1

§EVTG0: EVTG0

EVTG0

§CAN0: CAN0

CAN0

§CAN1: CAN1

CAN1

§USBDCD0: USBDCD0

USBDCD0

§USBFS0: USBFS0

USBFS0

§ENET0: ENET0

ENET0

§EMVSIM0: EMVSIM0

EMVSIM0

§EMVSIM1: EMVSIM1

EMVSIM1

§FLEXIO0: FLEXIO0

FLEXIO0

§SAI0: SAI0

SAI0

§SAI1: SAI1

SAI1

§SINC0: SINC0

SINC0

§USDHC0: USDHC0

USDHC0

§USBPHY: USBPHY

USBPHY

§USBHS1_PHY_DCD: USBHS1_PHY_DCD

USBHS1_PHY_DCD

§USBHS1__USBC: USBHS1__USBC

USBHS1__USBC

§USBHS1__USBNC: USBHS1__USBNC

USBHS1__USBNC

§PDM: PDM

PDM

§ADC0: ADC0

ADC0

§ADC1: ADC1

ADC1

§DAC0: DAC0

DAC0

§DAC1: DAC1

DAC1

§OPAMP0: OPAMP0

OPAMP0

§OPAMP1: OPAMP1

OPAMP1

§OPAMP2: OPAMP2

OPAMP2

§VREF0: VREF0

VREF0

§DAC2: DAC2

DAC2

§PORT1: PORT1

PORT1

§PORT2: PORT2

PORT2

§PORT3: PORT3

PORT3

§PORT4: PORT4

PORT4

§AHBSC: AHBSC

AHBSC

§SCN_SCB: SCN_SCB

SCnSCB

§SYS_TICK0: SYS_TICK0

SysTick0

§SAU: SAU

SAU

Implementations§

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impl Peripherals

source

pub fn take() -> Option<Self>

Returns all the peripherals once.

source

pub unsafe fn steal() -> Self

Unchecked version of Peripherals::take.

§Safety

Each of the returned peripherals must be used at most once.

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fn borrow_mut(&mut self) -> &mut T

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