Struct mcxn947_pac::ENET0

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pub struct ENET0 { /* private fields */ }

Expand description

ENET

Implementations§

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impl ENET0

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pub const PTR: const RegisterBlock = {0x40100000 as const enet0::RegisterBlock}

Pointer to the register block

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pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

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pub unsafe fn steal() -> Self

Steal an instance of this peripheral

§Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>§

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pub fn mac_configuration(&self) -> &MAC_CONFIGURATION

0x00 - MAC Configuration

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pub fn mac_ext_configuration(&self) -> &MAC_EXT_CONFIGURATION

0x04 - MAC Extended Configuration Register

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pub fn mac_packet_filter(&self) -> &MAC_PACKET_FILTER

0x08 - MAC Packet Filter

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pub fn mac_watchdog_timeout(&self) -> &MAC_WATCHDOG_TIMEOUT

0x0c - Watchdog Timeout

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pub fn mac_vlan_tag_ctrl(&self) -> &MAC_VLAN_TAG_CTRL

0x50 - MAC VLAN Tag Control

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pub fn mac_vlan_incl(&self) -> &MAC_VLAN_INCL

0x60 - VLAN Tag Inclusion or Replacement

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pub fn mac_inner_vlan_incl(&self) -> &MAC_INNER_VLAN_INCL

0x64 - MAC Inner VLAN Tag Inclusion or Replacement

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pub fn mac_q0_tx_flow_ctrl(&self) -> &MAC_Q0_TX_FLOW_CTRL

0x70 - MAC Q0 Tx Flow Control

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pub fn mac_rx_flow_ctrl(&self) -> &MAC_RX_FLOW_CTRL

0x90 - MAC Rx Flow Control

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pub fn mac_rxq_ctrl4(&self) -> &MAC_RXQ_CTRL4

0x94 - Receive Queue Control 4

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pub fn mac_rxq_ctrl0(&self) -> &MAC_RXQ_CTRL0

0xa0 - Receive Queue Control 0

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pub fn mac_rxq_ctrl1(&self) -> &MAC_RXQ_CTRL1

0xa4 - Receive Queue Control 1

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pub fn mac_rxq_ctrl2(&self) -> &MAC_RXQ_CTRL2

0xa8 - Receive Queue Control 2

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pub fn mac_interrupt_status(&self) -> &MAC_INTERRUPT_STATUS

0xb0 - Interrupt Status

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pub fn mac_interrupt_enable(&self) -> &MAC_INTERRUPT_ENABLE

0xb4 - Interrupt Enable

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pub fn mac_rx_tx_status(&self) -> &MAC_RX_TX_STATUS

0xb8 - Receive Transmit Status

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pub fn mac_pmt_control_status(&self) -> &MAC_PMT_CONTROL_STATUS

0xc0 - PMT Control and Status

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pub fn mac_rwk_packet_filter(&self) -> &MAC_RWK_PACKET_FILTER

0xc4 - Remote Wakeup Filter

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pub fn mac_lpi_control_status(&self) -> &MAC_LPI_CONTROL_STATUS

0xd0 - LPI Control and Status

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pub fn mac_lpi_timers_control(&self) -> &MAC_LPI_TIMERS_CONTROL

0xd4 - LPI Timers Control

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pub fn mac_lpi_entry_timer(&self) -> &MAC_LPI_ENTRY_TIMER

0xd8 - Tx LPI Entry Timer Control

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pub fn mac_oneus_tic_counter(&self) -> &MAC_ONEUS_TIC_COUNTER

0xdc - One-microsecond Reference Timer

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pub fn mac_version(&self) -> &MAC_VERSION

0x110 - MAC Version

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pub fn mac_debug(&self) -> &MAC_DEBUG

0x114 - MAC Debug

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pub fn mac_hw_feature0(&self) -> &MAC_HW_FEATURE0

0x11c - Hardware Features 0

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pub fn mac_hw_feature1(&self) -> &MAC_HW_FEATURE1

0x120 - Hardware Features 1

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pub fn mac_hw_feature2(&self) -> &MAC_HW_FEATURE2

0x124 - Hardware Features 2

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pub fn mac_hw_feature3(&self) -> &MAC_HW_FEATURE3

0x128 - Hardware Features 3

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pub fn mac_mdio_address(&self) -> &MAC_MDIO_ADDRESS

0x200 - MDIO Address

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pub fn mac_mdio_data(&self) -> &MAC_MDIO_DATA

0x204 - MAC MDIO Data

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pub fn mac_csr_sw_ctrl(&self) -> &MAC_CSR_SW_CTRL

0x230 - CSR Software Control

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pub fn mac_address0_high(&self) -> &MAC_ADDRESS0_HIGH

0x300 - MAC Address0 High

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pub fn mac_address0_low(&self) -> &MAC_ADDRESS0_LOW

0x304 - MAC Address0 Low

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pub fn indir_access_ctrl(&self) -> &INDIR_ACCESS_CTRL

0xa70 - Indirect Access Control

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pub fn indir_access_data(&self) -> &INDIR_ACCESS_DATA

0xa74 - Indirect Access Data

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pub fn mac_timestamp_control(&self) -> &MAC_TIMESTAMP_CONTROL

0xb00 - Timestamp Control

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pub fn mac_sub_second_increment(&self) -> &MAC_SUB_SECOND_INCREMENT

0xb04 - Subsecond Increment

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pub fn mac_system_time_seconds(&self) -> &MAC_SYSTEM_TIME_SECONDS

0xb08 - System Time Seconds

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pub fn mac_system_time_nanoseconds(&self) -> &MAC_SYSTEM_TIME_NANOSECONDS

0xb0c - System Time Nanoseconds

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pub fn mac_system_time_seconds_update(&self) -> &MAC_SYSTEM_TIME_SECONDS_UPDATE

0xb10 - System Time Seconds Update

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pub fn mac_system_time_nanoseconds_update( &self ) -> &MAC_SYSTEM_TIME_NANOSECONDS_UPDATE

0xb14 - System Time Nanoseconds Update

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pub fn mac_timestamp_addend(&self) -> &MAC_TIMESTAMP_ADDEND

0xb18 - Timestamp Addend

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pub fn mac_timestamp_status(&self) -> &MAC_TIMESTAMP_STATUS

0xb20 - Timestamp Status

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pub fn mac_tx_timestamp_status_nanoseconds( &self ) -> &MAC_TX_TIMESTAMP_STATUS_NANOSECONDS

0xb30 - Transmit Timestamp Status Nanoseconds

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pub fn mac_tx_timestamp_status_seconds( &self ) -> &MAC_TX_TIMESTAMP_STATUS_SECONDS

0xb34 - Transmit Timestamp Status Seconds

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pub fn mac_timestamp_ingress_corr_nanosecond( &self ) -> &MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND

0xb58 - Timestamp Ingress Correction Nanosecond

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pub fn mac_timestamp_egress_corr_nanosecond( &self ) -> &MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND

0xb5c - Timestamp Egress Correction Nanosecond

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pub fn mac_timestamp_ingress_latency(&self) -> &MAC_TIMESTAMP_INGRESS_LATENCY

0xb68 - Timestamp Ingress Latency

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pub fn mac_timestamp_egress_latency(&self) -> &MAC_TIMESTAMP_EGRESS_LATENCY

0xb6c - Timestamp Egress Latency

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pub fn mac_pps_control(&self) -> &MAC_PPS_CONTROL

0xb70 - PPS Control

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pub fn pps0_target_time_seconds(&self) -> &PPS0_TARGET_TIME_SECONDS

0xb80 - PPS0 Target Time Seconds

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pub fn pps0_target_time_nanoseconds(&self) -> &PPS0_TARGET_TIME_NANOSECONDS

0xb84 - PPS0 Target Time Nanoseconds

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pub fn mtl_operation_mode(&self) -> &MTL_OPERATION_MODE

0xc00 - MTL Operation Mode

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pub fn mtl_interrupt_status(&self) -> &MTL_INTERRUPT_STATUS

0xc20 - MTL Interrupt Status

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pub fn mtl_rxq_dma_map0(&self) -> &MTL_RXQ_DMA_MAP0

0xc30 - Receive Queue and DMA Channel Mapping 0

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pub fn queue(&self, n: usize) -> &QUEUE

0xd00..0xd80 - Cluster QUEUE%s, containing MTL_TXQ?_OPERATION_MODE, MTL_TXQ?_UNDERFLOW, MTL_TXQ?_DEBUG, MTL_TXQ?_ETS_STATUS, MTL_TXQ?_QUANTUM_WEIGHT, MTL_Q?_INTERRUPT_CONTROL_STATUS, MTL_RXQ?_OPERATION_MODE, MTL_RXQ?_MISSED_PACKET_OVERFLOW_CNT, MTL_RXQ?_DEBUG, MTL_RXQ?_CONTROL

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pub fn queue_iter(&self) -> impl Iterator<Item = &QUEUE>

Iterator for array of: 0xd00..0xd80 - Cluster QUEUE%s, containing MTL_TXQ?_OPERATION_MODE, MTL_TXQ?_UNDERFLOW, MTL_TXQ?_DEBUG, MTL_TXQ?_ETS_STATUS, MTL_TXQ?_QUANTUM_WEIGHT, MTL_Q?_INTERRUPT_CONTROL_STATUS, MTL_RXQ?_OPERATION_MODE, MTL_RXQ?_MISSED_PACKET_OVERFLOW_CNT, MTL_RXQ?_DEBUG, MTL_RXQ?_CONTROL

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pub fn mtl_txq1_ets_control(&self) -> &MTL_TXQ1_ETS_CONTROL

0xd50 - Queue 1 ETS Control

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pub fn mtl_txq1_sendslopecredit(&self) -> &MTL_TXQ1_SENDSLOPECREDIT

0xd5c - Queue 1 sendSlopeCredit

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pub fn mtl_txq1_hicredit(&self) -> &MTL_TXQ1_HICREDIT

0xd60 - Queue 1 hiCredit

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pub fn mtl_txq1_locredit(&self) -> &MTL_TXQ1_LOCREDIT

0xd64 - Queue 1 loCredit

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pub fn dma_mode(&self) -> &DMA_MODE

0x1000 - DMA Bus Mode

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pub fn dma_sysbus_mode(&self) -> &DMA_SYSBUS_MODE

0x1004 - DMA System Bus Mode

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pub fn dma_interrupt_status(&self) -> &DMA_INTERRUPT_STATUS

0x1008 - DMA Interrupt Status

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pub fn dma_debug_status0(&self) -> &DMA_DEBUG_STATUS0

0x100c - DMA Debug Status 0

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pub fn dma_ch(&self, n: usize) -> &DMA_CH

0x1100..0x11e0 - Cluster DMA_CH%s, containing DMA_CH?_CONTROL, DMA_CH?_TX_CONTROL, DMA_CH?_RX_CONTROL, DMA_CH?_TXDESC_LIST_ADDRESS, DMA_CH?_RXDESC_LIST_ADDRESS, DMA_CH?_TXDESC_TAIL_POINTER, DMA_CH?_RXDESC_TAIL_POINTER, DMA_CH?_TXDESC_RING_LENGTH, DMA_CH?_RX_CONTROL2, DMA_CH?_INTERRUPT_ENABLE, DMA_CH?_RX_INTERRUPT_WATCHDOG_TIMER, DMA_CH?_SLOT_FUNCTION_CONTROL_STATUS, DMA_CH?_CURRENT_APP_TXDESC, DMA_CH?_CURRENT_APP_RXDESC, DMA_CH?_CURRENT_APP_TXBUFFER, DMA_CH?_CURRENT_APP_RXBUFFER, DMA_CH?_STATUS, DMA_CH?_MISS_FRAME_CNT, DMA_CH?_RX_ERI_CNT

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pub fn dma_ch_iter(&self) -> impl Iterator<Item = &DMA_CH>

Iterator for array of: 0x1100..0x11e0 - Cluster DMA_CH%s, containing DMA_CH?_CONTROL, DMA_CH?_TX_CONTROL, DMA_CH?_RX_CONTROL, DMA_CH?_TXDESC_LIST_ADDRESS, DMA_CH?_RXDESC_LIST_ADDRESS, DMA_CH?_TXDESC_TAIL_POINTER, DMA_CH?_RXDESC_TAIL_POINTER, DMA_CH?_TXDESC_RING_LENGTH, DMA_CH?_RX_CONTROL2, DMA_CH?_INTERRUPT_ENABLE, DMA_CH?_RX_INTERRUPT_WATCHDOG_TIMER, DMA_CH?_SLOT_FUNCTION_CONTROL_STATUS, DMA_CH?_CURRENT_APP_TXDESC, DMA_CH?_CURRENT_APP_RXDESC, DMA_CH?_CURRENT_APP_TXBUFFER, DMA_CH?_CURRENT_APP_RXBUFFER, DMA_CH?_STATUS, DMA_CH?_MISS_FRAME_CNT, DMA_CH?_RX_ERI_CNT