Struct mcan::bus::Can

pub struct Can<'a, Id, D, C: Capacities> {
    pub interrupt_configuration: InterruptConfiguration<Id>,
    pub interrupts: OwnedInterruptSet<Id, Disabled>,
    pub rx_fifo_0: RxFifo<'a, Fifo0, Id, C::RxFifo0Message>,
    pub rx_fifo_1: RxFifo<'a, Fifo1, Id, C::RxFifo1Message>,
    pub rx_dedicated_buffers: RxDedicatedBuffer<'a, Id, C::RxBufferMessage>,
    pub tx: Tx<'a, Id, C>,
    pub tx_event_fifo: TxEventFifo<'a, Id>,
    pub aux: Aux<'a, Id, D>,
}

A CAN bus that is not in configuration mode (CCE=0)

Some errors (including Bus_Off) can asynchronously stop bus operation (INIT=1), which will require user intervention to reactivate the bus to resume sending and receiving messages.

Fields

interrupt_configuration: InterruptConfiguration<Id>

Controls enabling and line selection of interrupts.

interrupts: OwnedInterruptSet<Id, Disabled>

Initial set of interrupts in a disabled state.

rx_fifo_0: RxFifo<'a, Fifo0, Id, C::RxFifo0Message>

Receive FIFO 0

rx_fifo_1: RxFifo<'a, Fifo1, Id, C::RxFifo1Message>

Receive FIFO 1

rx_dedicated_buffers: RxDedicatedBuffer<'a, Id, C::RxBufferMessage>

Dedicated receive buffers

tx: Tx<'a, Id, C>

Message transmission

tx_event_fifo: TxEventFifo<'a, Id>

Events for successfully transmitted messages

aux: Aux<'a, Id, D>

Auxiliary bits and bobs

Implementations

impl<'a, Id: CanId, D: Dependencies<Id>, C: Capacities> Can<'a, Id, D, C>

pub unsafe fn registers(&self) -> &Can<Id>

Raw access to the registers.

Safety

The abstraction assumes that it has exclusive ownership of the registers. Direct access can break such assumptions.

pub fn configure(self) -> CanConfigurable<'a, Id, D, C>

Return to configuration mode. This resets some status registers, which effectively clears received messages, messages pending transmission and tranmit events.

pub fn release(self) -> D

Disables the peripheral and makes the Dependencies available again.