Type Alias R 

pub type R = R<CtrlSpec>;

Register CTRL reader

Aliased Type

pub struct R { /* private fields */ }

Implementations

impl R

pub fn rx_thd_val(&self) -> RxThdValR

Bits 0:3 - This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored)

pub fn par_en(&self) -> ParEnR

Bit 4 - Parity Enable

pub fn par_eo(&self) -> ParEoR

Bit 5 - when PAREN=1 selects odd or even parity odd is 1 even is 0

pub fn par_md(&self) -> ParMdR

Bit 6 - Selects parity based on 1s or 0s count (when PAREN=1)

pub fn cts_dis(&self) -> CtsDisR

Bit 7 - CTS Sampling Disable

pub fn tx_flush(&self) -> TxFlushR

Bit 8 - Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed.

pub fn rx_flush(&self) -> RxFlushR

Bit 9 - Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed.

pub fn char_size(&self) -> CharSizeR

Bits 10:11 - Selects UART character size

pub fn stopbits(&self) -> StopbitsR

Bit 12 - Selects the number of stop bits that will be generated

pub fn hfc_en(&self) -> HfcEnR

Bit 13 - Enables/disables hardware flow control

pub fn rtsdc(&self) -> RtsdcR

Bit 14 - Hardware Flow Control RTS Mode

pub fn bclken(&self) -> BclkenR

Bit 15 - Baud clock enable

pub fn bclksrc(&self) -> BclksrcR

Bits 16:17 - To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock.

pub fn dpfe_en(&self) -> DpfeEnR

Bit 18 - Data/Parity bit frame error detection enable

pub fn bclkrdy(&self) -> BclkrdyR

Bit 19 - Baud clock Ready read only bit

pub fn ucagm(&self) -> UcagmR

Bit 20 - UART Clock Auto Gating mode

pub fn fdm(&self) -> FdmR

Bit 21 - Fractional Division Mode

pub fn desm(&self) -> DesmR

Bit 22 - RX Dual Edge Sampling Mode