Type Alias R 

pub type R = R<CtrlSpec>;

Register CTRL reader

Aliased Type

pub struct R { /* private fields */ }

Implementations

impl R

pub fn en(&self) -> EnR

Bit 0 - Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.

pub fn tod_alarm_ie(&self) -> TodAlarmIeR

Bit 1 - Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.

pub fn ssec_alarm_ie(&self) -> SsecAlarmIeR

Bit 2 - Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.

pub fn busy(&self) -> BusyR

Bit 3 - RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.

pub fn rdy(&self) -> RdyR

Bit 4 - RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.

pub fn rdy_ie(&self) -> RdyIeR

Bit 5 - RTC Ready Interrupt Enable.

pub fn tod_alarm(&self) -> TodAlarmR

Bit 6 - Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.

pub fn ssec_alarm(&self) -> SsecAlarmR

Bit 7 - Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.

pub fn sqw_en(&self) -> SqwEnR

Bit 8 - Square Wave Output Enable.

pub fn sqw_sel(&self) -> SqwSelR

Bits 9:10 - Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.

pub fn rd_en(&self) -> RdEnR

Bit 14 - Asynchronous Counter Read Enable.

pub fn wr_en(&self) -> WrEnR

Bit 15 - Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.