Struct RegisterBlock 

pub struct RegisterBlock {
    pub addr: Reg<ADDR_SPEC>,
    pub clkdiv: Reg<CLKDIV_SPEC>,
    pub cn: Reg<CN_SPEC>,
    pub intr: Reg<INTR_SPEC>,
    pub data: [Reg<DATA_SPEC>; 4],
    pub acntl: Reg<ACNTL_SPEC>,
    /* private fields */
}

Register block

Fields

addr: Reg<ADDR_SPEC>

0x00 - Flash Write Address.

clkdiv: Reg<CLKDIV_SPEC>

0x04 - Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.

cn: Reg<CN_SPEC>

0x08 - Flash Control Register.

intr: Reg<INTR_SPEC>

0x24 - Flash Interrupt Register.

data: [Reg<DATA_SPEC>; 4]

0x30..0x40 - Flash Write Data.

acntl: Reg<ACNTL_SPEC>

0x40 - Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero.