Struct max32630_svd::clkman::RegisterBlock[−][src]

#[repr(C)]

pub struct RegisterBlock {
    pub clk_config: CLK_CONFIG,
    pub clk_ctrl: CLK_CTRL,
    pub intfl: INTFL,
    pub inten: INTEN,
    pub trim_calc: TRIM_CALC,
    pub i2c_timer_ctrl: I2C_TIMER_CTRL,
    pub cm4_start_clk_en0: CM4_START_CLK_EN0,
    pub cm4_start_clk_en1: CM4_START_CLK_EN1,
    pub cm4_start_clk_en2: CM4_START_CLK_EN2,
    pub sys_clk_ctrl_0_cm4: SYS_CLK_CTRL_0_CM4,
    pub sys_clk_ctrl_1_sync: SYS_CLK_CTRL_1_SYNC,
    pub sys_clk_ctrl_2_spix: SYS_CLK_CTRL_2_SPIX,
    pub sys_clk_ctrl_3_prng: SYS_CLK_CTRL_3_PRNG,
    pub sys_clk_ctrl_4_wdt0: SYS_CLK_CTRL_4_WDT0,
    pub sys_clk_ctrl_5_wdt1: SYS_CLK_CTRL_5_WDT1,
    pub sys_clk_ctrl_6_gpio: SYS_CLK_CTRL_6_GPIO,
    pub sys_clk_ctrl_7_pt: SYS_CLK_CTRL_7_PT,
    pub sys_clk_ctrl_8_uart: SYS_CLK_CTRL_8_UART,
    pub sys_clk_ctrl_9_i2cm: SYS_CLK_CTRL_9_I2CM,
    pub sys_clk_ctrl_10_i2cs: SYS_CLK_CTRL_10_I2CS,
    pub sys_clk_ctrl_11_spi0: SYS_CLK_CTRL_11_SPI0,
    pub sys_clk_ctrl_12_spi1: SYS_CLK_CTRL_12_SPI1,
    pub sys_clk_ctrl_13_spi2: SYS_CLK_CTRL_13_SPI2,
    pub sys_clk_ctrl_14_spib: SYS_CLK_CTRL_14_SPIB,
    pub sys_clk_ctrl_15_owm: SYS_CLK_CTRL_15_OWM,
    pub sys_clk_ctrl_16_spis: SYS_CLK_CTRL_16_SPIS,
    pub crypt_clk_ctrl_0_aes: CRYPT_CLK_CTRL_0_AES,
    pub crypt_clk_ctrl_1_maa: CRYPT_CLK_CTRL_1_MAA,
    pub crypt_clk_ctrl_2_prng: CRYPT_CLK_CTRL_2_PRNG,
    pub clk_gate_ctrl0: CLK_GATE_CTRL0,
    pub clk_gate_ctrl1: CLK_GATE_CTRL1,
    pub clk_gate_ctrl2: CLK_GATE_CTRL2,
    // some fields omitted
}

Register block

Fields

0x00 - System Clock Configuration

0x04 - System Clock Controls

0x08 - Interrupt Flags

0x0c - Interrupt Enable/Disable Controls

0x10 - Trim Calculation Controls

0x14 - I2C Timer Control

0x18 - CM4 Start Clock on Interrupt Enable 0

0x1c - CM4 Start Clock on Interrupt Enable 1

0x20 - CM4 Start Clock on Interrupt Enable 2

0x40 - Control Settings for CLK0 - Cortex M4 Clock

0x44 - Control Settings for CLK1 - Synchronizer Clock

0x48 - Control Settings for CLK2 - SPI XIP Clock

0x4c - Control Settings for CLK3 - PRNG Clock

0x50 - Control Settings for CLK4 - Watchdog Timer 0

0x54 - Control Settings for CLK5 - Watchdog Timer 1

0x58 - Control Settings for CLK6 - Clock for GPIO Ports

0x5c - Control Settings for CLK7 - Source Clock for All Pulse Trains

0x60 - Control Settings for CLK8 - Source Clock for All UARTs

0x64 - Control Settings for CLK9 - Source Clock for All I2C Masters

0x68 - Control Settings for CLK10 - Source Clock for I2C Slave

0x6c - Control Settings for CLK11 - SPI Master 0

0x70 - Control Settings for CLK12 - SPI Master 1

0x74 - Control Settings for CLK13 - SPI Master 2

0x78 - Control Settings for CLK14 - SPI Bridge Clock

0x7c - Control Settings for CLK15 - 1-Wire Master Clock

0x80 - Control Settings for CLK16 - SPI Slave Clock

0x100 - Control Settings for Crypto Clock 0 - AES

0x104 - Control Settings for Crypto Clock 1 - MAA

0x108 - Control Settings for Crypto Clock 2 - PRNG

0x140 - Dynamic Clock Gating Control Register 0

0x144 - Dynamic Clock Gating Control Register 1

0x148 - Dynamic Clock Gating Control Register 2

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