Module max32630_svd::clkman

System Clock Manager

Modules

clk_config	System Clock Configuration
clk_ctrl	System Clock Controls
clk_gate_ctrl0	Dynamic Clock Gating Control Register 0
clk_gate_ctrl1	Dynamic Clock Gating Control Register 1
clk_gate_ctrl2	Dynamic Clock Gating Control Register 2
cm4_start_clk_en0	CM4 Start Clock on Interrupt Enable 0
cm4_start_clk_en1	CM4 Start Clock on Interrupt Enable 1
cm4_start_clk_en2	CM4 Start Clock on Interrupt Enable 2
crypt_clk_ctrl_0_aes	Control Settings for Crypto Clock 0 - AES
crypt_clk_ctrl_1_maa	Control Settings for Crypto Clock 1 - MAA
crypt_clk_ctrl_2_prng	Control Settings for Crypto Clock 2 - PRNG
i2c_timer_ctrl	I2C Timer Control
inten	Interrupt Enable/Disable Controls
intfl	Interrupt Flags
sys_clk_ctrl_0_cm4	Control Settings for CLK0 - Cortex M4 Clock
sys_clk_ctrl_10_i2cs	Control Settings for CLK10 - Source Clock for I2C Slave
sys_clk_ctrl_11_spi0	Control Settings for CLK11 - SPI Master 0
sys_clk_ctrl_12_spi1	Control Settings for CLK12 - SPI Master 1
sys_clk_ctrl_13_spi2	Control Settings for CLK13 - SPI Master 2
sys_clk_ctrl_14_spib	Control Settings for CLK14 - SPI Bridge Clock
sys_clk_ctrl_15_owm	Control Settings for CLK15 - 1-Wire Master Clock
sys_clk_ctrl_16_spis	Control Settings for CLK16 - SPI Slave Clock
sys_clk_ctrl_1_sync	Control Settings for CLK1 - Synchronizer Clock
sys_clk_ctrl_2_spix	Control Settings for CLK2 - SPI XIP Clock
sys_clk_ctrl_3_prng	Control Settings for CLK3 - PRNG Clock
sys_clk_ctrl_4_wdt0	Control Settings for CLK4 - Watchdog Timer 0
sys_clk_ctrl_5_wdt1	Control Settings for CLK5 - Watchdog Timer 1
sys_clk_ctrl_6_gpio	Control Settings for CLK6 - Clock for GPIO Ports
sys_clk_ctrl_7_pt	Control Settings for CLK7 - Source Clock for All Pulse Trains
sys_clk_ctrl_8_uart	Control Settings for CLK8 - Source Clock for All UARTs
sys_clk_ctrl_9_i2cm	Control Settings for CLK9 - Source Clock for All I2C Masters
trim_calc	Trim Calculation Controls

Structs

CLK_CONFIG	System Clock Configuration
CLK_CTRL	System Clock Controls
CLK_GATE_CTRL0	Dynamic Clock Gating Control Register 0
CLK_GATE_CTRL1	Dynamic Clock Gating Control Register 1
CLK_GATE_CTRL2	Dynamic Clock Gating Control Register 2
CM4_START_CLK_EN0	CM4 Start Clock on Interrupt Enable 0
CM4_START_CLK_EN1	CM4 Start Clock on Interrupt Enable 1
CM4_START_CLK_EN2	CM4 Start Clock on Interrupt Enable 2
CRYPT_CLK_CTRL_0_AES	Control Settings for Crypto Clock 0 - AES
CRYPT_CLK_CTRL_1_MAA	Control Settings for Crypto Clock 1 - MAA
CRYPT_CLK_CTRL_2_PRNG	Control Settings for Crypto Clock 2 - PRNG
I2C_TIMER_CTRL	I2C Timer Control
INTEN	Interrupt Enable/Disable Controls
INTFL	Interrupt Flags
RegisterBlock	Register block
SYS_CLK_CTRL_0_CM4	Control Settings for CLK0 - Cortex M4 Clock
SYS_CLK_CTRL_10_I2CS	Control Settings for CLK10 - Source Clock for I2C Slave
SYS_CLK_CTRL_11_SPI0	Control Settings for CLK11 - SPI Master 0
SYS_CLK_CTRL_12_SPI1	Control Settings for CLK12 - SPI Master 1
SYS_CLK_CTRL_13_SPI2	Control Settings for CLK13 - SPI Master 2
SYS_CLK_CTRL_14_SPIB	Control Settings for CLK14 - SPI Bridge Clock
SYS_CLK_CTRL_15_OWM	Control Settings for CLK15 - 1-Wire Master Clock
SYS_CLK_CTRL_16_SPIS	Control Settings for CLK16 - SPI Slave Clock
SYS_CLK_CTRL_1_SYNC	Control Settings for CLK1 - Synchronizer Clock
SYS_CLK_CTRL_2_SPIX	Control Settings for CLK2 - SPI XIP Clock
SYS_CLK_CTRL_3_PRNG	Control Settings for CLK3 - PRNG Clock
SYS_CLK_CTRL_4_WDT0	Control Settings for CLK4 - Watchdog Timer 0
SYS_CLK_CTRL_5_WDT1	Control Settings for CLK5 - Watchdog Timer 1
SYS_CLK_CTRL_6_GPIO	Control Settings for CLK6 - Clock for GPIO Ports
SYS_CLK_CTRL_7_PT	Control Settings for CLK7 - Source Clock for All Pulse Trains
SYS_CLK_CTRL_8_UART	Control Settings for CLK8 - Source Clock for All UARTs
SYS_CLK_CTRL_9_I2CM	Control Settings for CLK9 - Source Clock for All I2C Masters
TRIM_CALC	Trim Calculation Controls