Struct RenderPlan 

pub struct RenderPlan {
    pub buffer_size: usize,
    pub buffers: Vec<UnsafeCell<Vec<f32>>>,
    pub nodes: Vec<Op>,
    pub indegree: Vec<u32>,
    pub dependents: Vec<Vec<NodeId>>,
    pub sources: Vec<NodeId>,
    pub hw_in_map: Vec<(usize, BufferId)>,
    pub hw_out_map: Vec<(BufferId, usize)>,
    pub port_map: HashMap<usize, BufferId>,
    pub midi_edges: Vec<(NodeId, NodeId)>,
    pub forced: Vec<NodeId>,
}

A compiled, immutable render plan. Owns the whole buffer arena.

Fields

buffer_size: usize

Samples per port buffer (the driver block size at compile time).

buffers: Vec<UnsafeCell<Vec<f32>>>

The arena: one buffer per AudioIO port, owned by the plan. Replaces shared mutable buffer wrappers on the real-time path.

Interior mutability is required because workers execute disjoint nodes of the same plan concurrently. Soundness rests on the single-producer-chain invariant enforced by RenderPlan::verify: two nodes that may run concurrently never touch the same buffer, and every buffer access goes through the node currently executing on this thread. This is the one audited unsafe cell of the design.

nodes: Vec<Op>

Nodes in topological order (producers before consumers).

indegree: Vec<u32>

indegree[i] = number of nodes that must finish before nodes[i].

dependents: Vec<Vec<NodeId>>

dependents[i] = nodes that may run once nodes[i] has finished.

sources: Vec<NodeId>

Nodes with indegree == 0 — the cycle seeds.

hw_in_map: Vec<(usize, BufferId)>

(hw channel, buffer) — the driver fills these before dispatch.

hw_out_map: Vec<(BufferId, usize)>

(buffer, hw channel) — the driver drains these after the cycle.

port_map: HashMap<usize, BufferId>

Arc pointer identity of each AudioIO port → its arena buffer. Transition aid so control code can resolve ports without re-walking.

midi_edges: Vec<(NodeId, NodeId)>

(writer task, reader task) pairs derived from MIDI connections (Phase 3, see LOCKLESS.md). Event payloads stay in the MIDIIO port buffers; these edges only guarantee that a port’s producer task completes before any task that merges it. Checked by verify().

forced: Vec<NodeId>

Nodes whose dependencies may never be satisfied (feedback loops). The executor force-completes them after the task timeout, mirroring today’s !progressed fallback in the dynamic scheduler.

Implementations

impl RenderPlan

pub unsafe fn buffer_ptr(&self, id: BufferId) -> *mut Vec<f32>

Mutable access to an arena buffer, as a raw pointer.

Returns a pointer rather than a &mut because the aliasing discipline is dynamic (enforced by the plan’s dependency graph, not the borrow checker) — this is the same shape as UnsafeCell::get.

Safety

The caller must be executing (or have already completed) the unique node chain that writes buffer id in this cycle, per the plan’s single-producer-chain invariant: no other concurrently running node may read or write the same buffer. The returned pointer is valid for the lifetime of the plan.

pub unsafe fn buffer(&self, id: BufferId) -> &[f32]

Read access to an arena buffer.

Safety

Same discipline as RenderPlan::buffer_ptr: the buffer’s producer chain must have completed, and no concurrent writer may exist.

pub fn buffer_count(&self) -> usize

Number of arena buffers.

pub fn compile( state: &StateSnapshot, hw_inputs: &[Arc<AudioIO>], hw_outputs: &[Arc<AudioIO>], buffer_size: usize, ) -> Self

Compile the current topology (tracks, folders, plugins, port wiring, HW bridges) into an immutable plan. Runs on the control thread; may allocate freely.

Track visit order is sorted by name so plans are deterministic — the legacy scheduler iterated State.tracks in HashMap order.

pub fn verify(&self) -> Result<(), String>

Verify the plan invariants (see the module docs). Called by compile (violations are logged) and by tests. Returns the first violation.

Trait Implementations

impl Debug for RenderPlan

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Sync for RenderPlan