Struct LinearMemoryBus 

pub struct LinearMemoryBus { /* private fields */ }

Fast linear-memory bus for RAM-backed emulators and WebAssembly builds.

This keeps all normal memory accesses inside Rust/wasm linear memory instead of crossing into a host callback for each byte/word/long. Addresses wrap within the backing buffer, with a fast mask path for power-of-two sizes.

Implementations

impl LinearMemoryBus

pub fn new(size: usize) -> Self

Create a zero-filled bus with size bytes.

pub fn from_vec(memory: Vec<u8>) -> Self

Create a bus using an existing memory buffer.

pub fn len(&self) -> usize

Return the number of bytes in the backing buffer.

pub fn is_empty(&self) -> bool

Return whether the backing buffer is empty.

A constructed LinearMemoryBus is never empty because LinearMemoryBus::from_vec rejects an empty buffer.

pub fn as_slice(&self) -> &[u8]

Borrow the complete backing buffer.

pub fn as_mut_slice(&mut self) -> &mut [u8]

Mutably borrow the complete backing buffer.

Taking a mutable slice advances the instruction-memory version conservatively because the caller may change executable bytes.

pub fn load(&mut self, address: u32, data: &[u8])

Copy bytes into memory at address, wrapping at the end of the backing buffer.

pub fn write_word_at(&mut self, address: u32, value: u16)

Write one big-endian word, wrapping within the backing buffer.

pub fn write_long_at(&mut self, address: u32, value: u32)

Write one big-endian longword, wrapping within the backing buffer.

Trait Implementations

impl AddressBus for LinearMemoryBus

fn fast_mem(&mut self) -> Option<FastMem>

The whole backing buffer is side-effect-free RAM, so expose it as a fastmem window starting at guest address 0. Accesses beyond len (which the bus methods wrap) simply fall back to the bus.

fn read_byte(&mut self, address: u32) -> u8

Read one byte from address.

fn read_word(&mut self, address: u32) -> u16

Read one big-endian 16-bit word from address.

fn read_long(&mut self, address: u32) -> u32

Read one big-endian 32-bit longword from address.

fn write_byte(&mut self, address: u32, value: u8)

Write one byte to address.

fn write_word(&mut self, address: u32, value: u16)

Write one big-endian 16-bit word to address.

fn write_long(&mut self, address: u32, value: u32)

Write one big-endian 32-bit longword to address.

fn read_immediate_word(&mut self, address: u32) -> u16

Read an instruction-stream word.

fn read_immediate_long(&mut self, address: u32) -> u32

Read an instruction-stream longword.

fn sync(&mut self, _cpu_clocks: u32)

Precise-timing callback (Part E.2): called immediately before each bus access with the number of CPU clocks of internal (non-bus) processing the core performed since its previous access. The access itself then takes the standard 4 CPU clocks of a 68000 bus cycle.

fn try_read_byte(&mut self, address: u32) -> Result<u8, BusFault>

Fallible read variants used to surface bus/MMU faults to the CPU core.

fn try_read_word(&mut self, address: u32) -> Result<u16, BusFault>

Fallible word read used for bus/MMU fault delivery.

fn try_read_long(&mut self, address: u32) -> Result<u32, BusFault>

Fallible longword read used for bus/MMU fault delivery.

fn try_write_byte(&mut self, address: u32, value: u8) -> Result<(), BusFault>

Fallible byte write used for bus/MMU fault delivery.

fn try_write_word(&mut self, address: u32, value: u16) -> Result<(), BusFault>

Fallible word write used for bus/MMU fault delivery.

fn try_write_long(&mut self, address: u32, value: u32) -> Result<(), BusFault>

Fallible longword write used for bus/MMU fault delivery.

fn read_three_bytes(&mut self, address: u32) -> u32

Read a big-endian three-byte operand from address, returned in the low 24 bits.

fn write_three_bytes(&mut self, address: u32, value: u32)

Write the low 24 bits of value as a big-endian three-byte operand.

fn try_read_three_bytes(&mut self, address: u32) -> Result<u32, BusFault>

Fallible three-byte read used for bus/MMU fault delivery. This is the variant the core calls, so a host that bills bus cycles must override it (as well as AddressBus::read_three_bytes) for the billing to take effect.

fn try_write_three_bytes( &mut self, address: u32, value: u32, ) -> Result<(), BusFault>

Fallible three-byte write used for bus/MMU fault delivery.

fn try_read_immediate_word(&mut self, address: u32) -> Result<u16, BusFault>

Instruction-stream reads with bus-fault reporting, used by the non-prefetch (68010+) opcode/immediate path so hosts can tell fetches from data reads (e.g. to model a 32-bit fetch path).

fn try_read_immediate_long(&mut self, address: u32) -> Result<u32, BusFault>

Fallible instruction-stream longword read.

fn last_fetch_was_cached(&self) -> bool

Whether the most recent instruction-stream read was served from the CPU’s instruction cache. The 68060 timing model gates superscalar pairing and branch folding on a cached fetch stream; plain test buses default to true (pair freely).

fn begin_instruction_fetches(&mut self)

Start tracking cache residency for one complete instruction. The MC68020 timing tables define their cache case for an instruction that is in the cache, including extension and immediate words rather than only the opcode word. Hosts with an instruction-cache model use this hook to reset their per-instruction hit accumulator.

fn instruction_fetches_were_cached(&self) -> bool

Whether every instruction-stream access since begin_instruction_fetches hit the instruction cache. Functional test buses without a cache model default to the most recent fetch result.

fn take_boundary_request(&mut self) -> bool

Take a pending request to return from cycle-scheduled execution at the next completed instruction or interrupt-entry boundary.

fn interrupt_acknowledge(&mut self, _level: u8) -> u32

Perform an interrupt-acknowledge cycle for level.

fn ipl_hold_sample(&mut self)

IPL poll-point marker. The 68000/68010 sample their IPL pins at ONE microcode-determined point per instruction, and the take-interrupt decision at the next instruction boundary consumes that sample. A timing-accurate host latches the IPL level at the start of every bus access and, by default, lets the instruction’s LAST access provide the boundary sample. For instructions whose poll point is NOT the last access (e.g. read-modify-write instructions poll during the final prefetch that precedes the writeback), the core calls this right after the polling access: the host must keep that access’s sample and ignore later accesses until the boundary decision consumes it. Functional-only buses can ignore it.

fn ipl_release_sample(&mut self)

Release an ipl_hold_sample poll-point hold before the instruction boundary consumes it. Called on exception dispatch: the vector jump’s handler-entry prefetch is a fresh poll point on real silicon (Moira jumpToVector polls during the final refill read), so a hold placed earlier in the faulted instruction must not survive into the handler.

fn reset_devices(&mut self)

Notify attached devices that the CPU asserted the external RESET line.

impl Clone for LinearMemoryBus

fn clone(&self) -> LinearMemoryBus

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for LinearMemoryBus

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl InstructionCacheBus for LinearMemoryBus

fn instruction_cache_version(&mut self, _address: u32) -> Option<u64>

Stable version for instruction memory at address, when known.

fn invalidate_instruction_cache(&mut self, _address: u32, _len: u32)

Notify the bus that bytes in a code-visible range were written by the CPU.