Struct Lr2021 

pub struct Lr2021<O, SPI, M: BusyPin> { /* private fields */ }

LR2021 Device

Implementations

impl<O, SPI, M> Lr2021<O, SPI, M>

where O: OutputPin, SPI: SpiBus<u8>, M: BusyPin,

pub async fn get_status(&mut self) -> Result<(Status, Intr), Lr2021Error>

Read status and interrupt from the chip

pub async fn get_errors(&mut self) -> Result<ErrorsRsp, Lr2021Error>

Read status and interrupt from the chip

pub async fn get_version(&mut self) -> Result<VersionRsp, Lr2021Error>

Read status and interrupt from the chip

pub async fn get_and_clear_irq(&mut self) -> Result<Intr, Lr2021Error>

Read interrupt from the chip and clear them all

pub async fn clear_irqs(&mut self, intr: Intr) -> Result<(), Lr2021Error>

Set the RF channel (in Hz)

pub async fn calibrate( &mut self, pa_offset: bool, meas_unit: bool, aaf: bool, pll: bool, hf_rc: bool, lf_rc: bool, ) -> Result<(), Lr2021Error>

Run calibration of different blocks Work in any chip mode and on exit the chip goes into Standby RC Eventual calibration error can be read with get_errors

pub async fn calib_fe(&mut self, freqs_4m: &[u16]) -> Result<(), Lr2021Error>

Run calibration on up to 3 frequencies on 16b (MSB encode RX Path) If none, use current frequency

pub async fn set_chip_mode( &mut self, chip_mode: ChipMode, ) -> Result<(), Lr2021Error>

Set Tx power and ramp time

pub async fn set_regulator_mode( &mut self, simo_en: bool, ) -> Result<(), Lr2021Error>

Configure regulator (LDO or SIMO) Shall only be called while in Standby RC

pub async fn add_register_to_retention( &mut self, slot: u8, addr: u32, ) -> Result<(), Lr2021Error>

Add a register to the retention list (i.e. the value is restored on wake-up)

pub async fn setup_retention( &mut self, cfg: RetentionCfg, ) -> Result<(), Lr2021Error>

Add registers to the retention list using a configuration parameter Registers are: SIMO, LoRa SX127x SF6/Syncword, LoRa SX127x hopping and BLE/WISUN tracking

pub async fn set_eol_config( &mut self, thr: EolTrim, en: bool, ) -> Result<(), Lr2021Error>

Configure End-of-Life

pub async fn patch_simo( &mut self, ret_en: Option<u8>, ) -> Result<(), Lr2021Error>

Update SIMO configuration for optimal performances Must be called after a the modulation parameters are set when SIMO is enabled (set_regulator_mode(true)) The retention enable allows to define a register slot to save setting in retention

pub async fn set_dio_function( &mut self, dio: DioNum, func: DioFunc, pull_drive: PullDrive, ) -> Result<(), Lr2021Error>

Configure a DIO function (IRQ, RF Switch, Clock, …) Note: LF clock can only be output on DIO 7 to 11

pub async fn set_dio_rf_switch( &mut self, dio_num: DioNum, tx_hf: bool, rx_hf: bool, tx_lf: bool, rx_lf: bool, standby: bool, ) -> Result<(), Lr2021Error>

Configure a pin as An RF Switch Each args flags when the IO should be high

pub async fn set_dio_irq( &mut self, dio: DioNum, intr_en: Intr, ) -> Result<(), Lr2021Error>

Configure a pin as IRQ and enable interrupts for this pin

pub async fn set_dio_clk_scaling( &mut self, div_scaling: ClkScaling, ) -> Result<(), Lr2021Error>

Configure the clock scaling when output on a DIO

pub async fn set_lf_clk(&mut self, sel: LfClock) -> Result<(), Lr2021Error>

Configure the LF clock

pub async fn set_tcxo( &mut self, volt: TcxoVoltage, start_time: u32, ) -> Result<(), Lr2021Error>

Configure the chip to use a TCXO

pub async fn set_xosc_trim( &mut self, xta: u8, xtb: u8, delay_us: Option<u8>, ) -> Result<(), Lr2021Error>

Configure XOsc foot capacitor XT A/B configure the foot capacitor for each pin with value ranging from 0 to 47 1 LSB is 0.47pF and min value starts at 11.3pF and 10.1pF for XTA and XTB respectively The optional delay allows to wait longer for the crystal to stabilize when it starts

pub async fn get_temperature( &mut self, src: TempSrc, res: AdcRes, ) -> Result<i16, Lr2021Error>

Return temperature in °C with 5 fractional bits When the selected source is an NTC, its parameter must be configure with set_ntc_params_cmd The resolution directly controls how long the measure take: from 8us (8b) to 256us (13b)

pub async fn set_ntc_param( &mut self, r_ratio: u16, beta: u16, delay: u8, ) -> Result<(), Lr2021Error>

Configure NTC parameters r_ratio is the resistance bias ratio of the NTC at 25°C given with 9 fractional bits The beta coefficient is given in unit of 2 Kelvin The delay corresponds to a first order time delay coefficient used in the temperature compensation feature: this depends on the PCB and how far the NTC is from the crystal

pub async fn set_temp_comp( &mut self, mode: CompMode, ntc: bool, ) -> Result<(), Lr2021Error>

Configure Temperature compensation Command will fail if a TCXO is configured External NTC is important when the board does not have sufficient thermal break and/or when transmission is particularly long (more than 2s)

pub async fn get_vbat(&mut self, res: AdcRes) -> Result<u16, Lr2021Error>

Return the battery voltage in mV A resolution of 13b corresponds to roughly 0.82mV The resolution directly controls how long the measure take: from 8us (8b) to 256us (13b)

pub async fn get_random_number(&mut self) -> Result<u32, Lr2021Error>

Return a random number using entropy from PLL and ADC

pub async fn rd_reg(&mut self, addr: u32) -> Result<u32, Lr2021Error>

Read a register value

pub async fn rd_mem(&mut self, addr: u32, nb32: u8) -> Result<(), Lr2021Error>

Read nb32 qword (max 40) from memory and save them inside local buffer

pub async fn wr_reg(&mut self, addr: u32, value: u32) -> Result<(), Lr2021Error>

Write a register value

pub async fn wr_reg_mask( &mut self, addr: u32, mask: u32, value: u32, ) -> Result<(), Lr2021Error>

Write a register value with a mask (only bit where mask is high are changed)

pub async fn wr_field( &mut self, addr: u32, value: u32, pos: u8, width: u8, ) -> Result<(), Lr2021Error>

Write a field value

impl<O, SPI, M> Lr2021<O, SPI, M>

where O: OutputPin, SPI: SpiBus<u8>, M: BusyPin,

pub async fn set_fifo_irq_en( &mut self, tx_en: FifoIrqEn, rx_en: FifoIrqEn, ) -> Result<(), Lr2021Error>

Configure interrupts enable for TX/RX Fifo

pub async fn set_fifo_irq_cfg( &mut self, tx: FifoIrqCfg, rx: FifoIrqCfg, ) -> Result<(), Lr2021Error>

Configure interrupts for TX/RX Fifo (enable with low and high threshold)

pub async fn get_fifo_irq( &mut self, ) -> Result<(FifoIrqEn, FifoIrqEn), Lr2021Error>

Return the irqs flag for TX and RX FIFO

pub async fn wr_tx_fifo_from( &mut self, buffer: &[u8], ) -> Result<(), Lr2021Error>

Write data to the TX FIFO Check number of bytes available with get_tx_fifo_lvl()

pub async fn wr_tx_fifo(&mut self, len: usize) -> Result<(), Lr2021Error>

Write data to the TX FIFO Check number of bytes available with get_tx_fifo_lvl()

pub async fn clear_tx_fifo(&mut self) -> Result<(), Lr2021Error>

Clear TX Fifo

pub async fn get_tx_fifo_lvl(&mut self) -> Result<u16, Lr2021Error>

Return number of byte in TX FIFO

pub async fn rd_rx_fifo_to( &mut self, buffer: &mut [u8], ) -> Result<(), Lr2021Error>

Read data from the RX FIFO

pub async fn rd_rx_fifo(&mut self, len: usize) -> Result<(), Lr2021Error>

Read data from the RX FIFO to the local buffer

pub async fn get_rx_fifo_lvl(&mut self) -> Result<u16, Lr2021Error>

Return number of byte in RX FIFO

pub async fn clear_rx_fifo(&mut self) -> Result<(), Lr2021Error>

Clear RX FIFO

impl<O, SPI, M> Lr2021<O, SPI, M>

where O: OutputPin, SPI: SpiBus<u8>, M: BusyPin,

pub async fn set_rf(&mut self, freq: u32) -> Result<(), Lr2021Error>

Set the RF channel (in Hz)

pub async fn set_rf_ranging(&mut self, freq: u32) -> Result<(), Lr2021Error>

Set the RF channel (in Hz) for ranging operation Call only after set_packet_type(Ranging)

pub async fn set_rx_path( &mut self, rx_path: RxPath, rx_boost: RxBoost, ) -> Result<(), Lr2021Error>

Set the RX Path (LF/HF)

pub async fn set_packet_type( &mut self, packet_type: PacketType, ) -> Result<(), Lr2021Error>

Set the packet type

pub async fn set_tx_params( &mut self, tx_power: i8, ramp_time: RampTime, ) -> Result<(), Lr2021Error>

Set Tx power and ramp time TX Power in given in half-dB unit. Range is -19..44 for LF Path and -39..24 for HF path Ramp-time is important to reduce Out-of-band emission. A safe rule of thumb is to set it to around 4/Bandwidth.

pub async fn set_pa_lf( &mut self, pa_lf_mode: PaLfMode, pa_lf_duty_cycle: u8, pa_lf_slices: u8, ) -> Result<(), Lr2021Error>

Configure LF Power Amplifier

pub async fn set_pa_lf_ocp_threshold( &mut self, thr: PaLfOcpThr, ) -> Result<(), Lr2021Error>

Change PA LF Over-Current Protection Threshold The power amplifier consumption may increase depending on antenna matching. Some 900MHz band antenna have shown a power consumption increase close to the OCP limitation. Calling this function allows to increase the OCP limitation in these situations WARNING: USE THIS FUNCTION CAREFULLY AS AN INCORRECT USAGE MAY RESULT IN DESTRUCTION OF THE CHIP.

pub async fn set_pa_hf(&mut self) -> Result<(), Lr2021Error>

Configure HF Power Amplifier

pub async fn set_fallback( &mut self, fallback_mode: FallbackMode, ) -> Result<(), Lr2021Error>

Set the Fallback mode after TX/RX

pub async fn set_tx(&mut self, tx_timeout: u32) -> Result<(), Lr2021Error>

Set chip in TX mode. Set timeout to 0 or to a value longer than the packet duration. Timeout is given in LF clock step (1/32.768kHz ~ 30.5us)

pub async fn set_tx_test(&mut self, mode: TestMode) -> Result<(), Lr2021Error>

Start TX in test mode (infinite preamble, continuous wave or PRBS9)

pub async fn set_rx( &mut self, rx_timeout: u32, wait_ready: bool, ) -> Result<(), Lr2021Error>

Set chip in RX mode. A timeout equal to 0 means a single reception, the value 0xFFFFFF is for continuous RX (i.e. always restart reception) and any other value, the chip will go back to its fallback mode if a reception does not occur before the timeout is elapsed Timeout is given in LF clock step (1/32.768kHz ~ 30.5us)

pub async fn set_rx_continous(&mut self) -> Result<(), Lr2021Error>

Set RX in continuous mode

pub async fn set_rx_duty_cycle( &mut self, listen_time: u32, cycle_time: u32, use_lora_cad: bool, dram_ret: u8, ) -> Result<(), Lr2021Error>

Start periodic RX Radio listens for rx_max_time: go to sleep once packet is received or no packet was detect Repeat operation every cycle_time (which must be bigger than rx_max_time) The use_lora_cad is only valid if packet type was set to LoRa and performs a CAD instead of a standard reception. In this case the exit mode of the CAD is performed, i.e. it can start a TX if configured as Listen-Before-Talk

pub async fn set_auto_rxtx( &mut self, clear: bool, mode: AutoTxrxMode, timeout: u32, delay: u32, ) -> Result<(), Lr2021Error>

Configure automatic Transmission/reception after RxDone/TxDone This mode triggers only once and must re-enabled. When clear is set, the auto_txrx is cleared even on RX timeout.

pub async fn set_cad_params( &mut self, cad_timeout: u32, threshold: u8, exit_mode: ExitMode, trx_timeout: u32, ) -> Result<(), Lr2021Error>

Configure parameters for Channel Activity Detection

• CAD Timeout is the maximum time spent measuring RSSI in 31.25ns step
• Threshold in -dBm to determine if a signal is present
• Exit Mode: controls what happens after CAD (nothing, TX if nothing, RX if something)
• TRX Timeout is the timeout used in case the exit_mode triggers a TX or RX

pub async fn set_cad(&mut self) -> Result<(), Lr2021Error>

Set chip in Channel activity Detection mode CAD is configured with set_cad_params

pub async fn set_cca( &mut self, duration: u32, gain: Option<u8>, ) -> Result<(), Lr2021Error>

Set chip in CCA (Clear Channel Assesment) for duration (31.25ns) Note: Chip must be standby or FS before issuing the command

pub async fn get_cca_result(&mut self) -> Result<CcaResultRsp, Lr2021Error>

Get CCA measurement results

pub async fn set_and_get_cca( &mut self, duration: u32, gain: Option<u8>, ) -> Result<CcaResultRsp, Lr2021Error>

Run a Clear Channel Assesment for duration (31.25ns) and retrieve the result Note: Chip must be standby or FS before issuing the command

pub async fn set_rx_gain(&mut self, gain: u8) -> Result<(), Lr2021Error>

Configure the radio gain manually:

• Gain 0 enable the automatic gain selection (default setting)
• Max gain is 13

pub async fn clear_rx_stats(&mut self) -> Result<(), Lr2021Error>

Clear RX stats

pub async fn get_rx_pkt_len(&mut self) -> Result<u16, Lr2021Error>

Return length of last packet received

pub async fn force_crc_out(&mut self) -> Result<(), Lr2021Error>

Output CRC to the FIFO even when already checked by hardware

pub async fn get_rssi_inst(&mut self) -> Result<u16, Lr2021Error>

Measure RSSI instantaneous

pub async fn get_rssi_avg(&mut self, nb_meas: u16) -> Result<u16, Lr2021Error>

Measure an average RSSI (in -0.5dBm) Average is the result of n instantaneous RSSI measurement

pub async fn set_default_timeout( &mut self, tx: u32, rx: u32, ) -> Result<(), Lr2021Error>

Set default timeout for TX/RX operation Used when started on DIO trigger

pub async fn set_stop_timeout( &mut self, on_preamble: bool, ) -> Result<(), Lr2021Error>

Set whether the RX timeout stops when preamble is detected or when the synchronization is confirmed

pub async fn set_timestamp_source( &mut self, index: TimestampIndex, source: TimestampSource, ) -> Result<(), Lr2021Error>

Set source for a timestamp (up to 3 configurable)

pub async fn get_timestamp( &mut self, index: TimestampIndex, ) -> Result<u32, Lr2021Error>

Get Timestamp (as number of HF tick elapsed until NSS)

impl<O, SPI, M> Lr2021<O, SPI, M>

where O: OutputPin, SPI: SpiBus<u8>, M: BusyPin,

pub async fn set_lora_modulation( &mut self, params: &LoraModulationParams, ) -> Result<(), Lr2021Error>

Set LoRa Modulation parameters

pub async fn set_ranging_modulation( &mut self, params: &LoraModulationParams, is_initiator: bool, ) -> Result<(), Lr2021Error>

Set LoRa Modulation parameters for ranging operation

pub async fn set_lora_packet( &mut self, params: &LoraPacketParams, ) -> Result<(), Lr2021Error>

Set LoRa Packet parameters

pub async fn set_lora_syncword( &mut self, syncword: u8, ) -> Result<(), Lr2021Error>

Set LoRa Syncword using legacy (SX127x) 1B notation: 0x34 for public network, 0x12 for private

pub async fn set_lora_syncword_ext( &mut self, s1: i8, s2: i8, ) -> Result<(), Lr2021Error>

Set LoRa Syncword, using 2B notation (2 values on 5b signed each) Public network is (6,8) and private network is (2,4)

pub async fn set_lora_synch_timeout( &mut self, timeout: u8, format: TimeoutFormat, ) -> Result<(), Lr2021Error>

Set synchronisation timeout Timeout is given in number of symbol: either the direct value or with mantissa/exponent (like SX126x)

pub async fn set_lora_address( &mut self, len: AddrLen, pos: u8, addr: u64, ) -> Result<(), Lr2021Error>

Set address for address filtering Length is the address length in number of byte 0 (no address filtering, default) up to 8 Pos is the first byte in the payload the address appears

pub async fn get_lora_packet_status( &mut self, ) -> Result<LoraPacketStatusRsp, Lr2021Error>

Return Information about last packet received

pub async fn get_lora_rx_stats(&mut self) -> Result<LoraRxStatsRsp, Lr2021Error>

Return RX statistics: packet received, CRC errors, …

pub async fn set_lora_cad_params( &mut self, params: &LoraCadParams, ) -> Result<(), Lr2021Error>

Set LoRa Channel Activity Detection parameters

pub async fn set_lora_cad(&mut self) -> Result<(), Lr2021Error>

Start a LoRa Channel Activity Detection (CAD)

pub async fn comp_sx127x_sf6_sw( &mut self, en: bool, ret_en: Option<u8>, ) -> Result<(), Lr2021Error>

Enable compatibility with SX127x for SF6 communication and syncword format When enabled, use set_lora_syncword_ext to configure syncword with only even value in the range 0..30 Must be called after each SetLoraModulation The retention enable allows to define a register slot to save this compatibility mode in retention

pub async fn comp_sx127x_hopping( &mut self, en: bool, ret_en: Option<u8>, ) -> Result<(), Lr2021Error>

Enable compatibility with SX127x for frequency hopping communication The retention enable allows to define a register slot to save this compatibility mode in retention

pub async fn set_lora_sidedet_cfg( &mut self, cfg: &[SidedetCfg], ) -> Result<(), Lr2021Error>

Configure Side-Detector allowing multiple SF to be detected Must be called after set_lora_modulation If cfg is an empty slice, this disabled all side-detector

pub async fn set_lora_sidedet_syncword( &mut self, sw: &[u8], ) -> Result<(), Lr2021Error>

Configure Side-Detector Syncword using basic syncword format

pub async fn set_lora_freq_range( &mut self, range: FreqRange, ) -> Result<(), Lr2021Error>

Configure the frequency error range supported by detection Medium range (+/-BW/3) has only a very minor sensitivity impact while the max range can degrade sensitivity by 2dB

pub async fn set_lora_preamble_modulation( &mut self, en: bool, dram_ret: u8, wakeup_time: u16, min_sleep_time: u32, ) -> Result<(), Lr2021Error>

Long preamble can be modulated in phase in order to provide information about how many symbols are left This allows a receiver to go back to sleep if beginning of the frame starts in a long time

pub async fn set_lora_blanking( &mut self, cfg: BlankingCfg, ) -> Result<(), Lr2021Error>

Configure blanking (algorithm to reduce impact of interferers) Works best when long interleaving is enabled (i.e. any CR > 4)

pub async fn set_lora_hopping( &mut self, period: u16, freq_hops: &[u32], ) -> Result<(), Lr2021Error>

Configure intra-packet frequency hopping Provide an empty slice of hops to disable hopping Max number of hops if 40

pub async fn patch_ranging_rf(&mut self) -> Result<(), Lr2021Error>

Patch the RF setting for ranging operation This ensure the RF channel setting is coherent with PLL configuration MUST be called after a set_rf or patch_dcdc

pub async fn set_ranging_dev_addr( &mut self, addr: u32, length: Option<CheckLength>, ) -> Result<(), Lr2021Error>

Set the device address for ranging operation The device will answer to ranging request only if the request address matches the device address The length allows to define how many bytes from the address are checked (starting from LSB)

pub async fn set_ranging_req_addr( &mut self, addr: u32, ) -> Result<(), Lr2021Error>

Set the request address for ranging operation

pub async fn set_ranging_txrx_delay( &mut self, delay: u32, ) -> Result<(), Lr2021Error>

Set the ranging calibration value

pub fn get_ranging_base_delay(&self, modulation: &LoraModulationParams) -> u32

Get the base delay for ranging depdending on bandwidth and SF Delay was calibrated only for bandwidth 125kHz and higher. For lower bandwidth (not recommended to use in ranging) a crude estimation is provided Note: the board itself will introduce some offset which should not be dependent on SF but might vary with bandwidth.

pub async fn set_ranging_params( &mut self, extended: bool, spy_mode: bool, nb_symbols: u8, ) -> Result<(), Lr2021Error>

Set the ranging parameters: Extended/Spy and number of symbols Extended mode initiate a second exchange with an inverted direction to improve accuracy and provide some relative speed indication Spy mode allows to estimate distance between two device while they are performing a ranging exchange. Number of symbols should typically be between 8 to 16 symbols, with 12 being close to optimal performances

pub async fn get_ranging_result( &mut self, ) -> Result<RangingResultRsp, Lr2021Error>

Return the result of last ranging exchange (round-trip time of flight and RSSI) The distance is provided

pub async fn get_ranging_ext_result( &mut self, ) -> Result<RangingExtResultRsp, Lr2021Error>

Return the result of last extended ranging exchange (round-trip time of flight and RSSI for both exchange) The round-trip time of flight can be converted in meter with the formula: rng150/(2^12Bandwidth)

pub async fn get_ranging_gain( &mut self, ) -> Result<RangingGainStepRsp, Lr2021Error>

Return the gain step used during ranging (the second gain step is only valid for extended ranging) This is mainly for debug, since gain can influence very slightly the results

pub async fn get_ranging_stats( &mut self, ) -> Result<RangingStatsRsp, Lr2021Error>

Return statistics about ranging exchanges

pub async fn get_ranging_rssi_offset(&mut self) -> Result<i16, Lr2021Error>

Return a correction offset on ranging RSSI Read the value after any change to the gain table

pub async fn set_lora_timing_sync( &mut self, mode: TimingSyncMode, dio_num: DioNum, ) -> Result<(), Lr2021Error>

Set Lora in Timing Synchronisation mode The initiator sends a special frame when the dio is asserted The responder is in reception mode and will assert the DIO a known delay after reception of the TimingSync packet

pub async fn set_lora_timing_sync_pulse( &mut self, delay: u32, width: TimingSyncPulseWidth, ) -> Result<(), Lr2021Error>

Configure the LoRa TimingSync Pulse for the initiator (delay and width)

impl<O, SPI, M> Lr2021<O, SPI, M>

where O: OutputPin, SPI: SpiBus<u8>, M: BusyPin,

pub async fn set_ble_modulation( &mut self, mode: BleMode, ) -> Result<(), Lr2021Error>

Set BLE Mode (1M, 2M, 500k, 125k)

pub async fn set_ble_params( &mut self, crc_in_fifo: bool, channel_type: ChannelType, whit_init: u8, crc_init: u32, syncword: u32, ) -> Result<(), Lr2021Error>

Set BLE parameters: Channel type (advertising, Header16/24b), Whitening & CRC init, SyncWord/AccessCode Call before set_ble_modulation to ensure BLE coded settings are not overwritten

pub async fn set_ble_tx(&mut self, len: u8) -> Result<(), Lr2021Error>

Set the PDU length and send the packet PDU must be ready in FIFO

pub async fn set_ble_tx_pdu_len(&mut self, len: u8) -> Result<(), Lr2021Error>

Set the PDU length Useful compare to set_ble_tx when using a pin trigger to control the exact transmit time

pub async fn get_ble_packet_status( &mut self, ) -> Result<BlePacketStatusRsp, Lr2021Error>

Return length of last packet received

pub async fn get_ble_rx_stats(&mut self) -> Result<BleRxStatsRsp, Lr2021Error>

Return basic RX stats

pub async fn patch_ble_coded( &mut self, ret_en: Option<u8>, ) -> Result<(), Lr2021Error>

Patch some settings when BLE Coded is used This fixes some issue related to BLE certification Automatically called by set_ble_modulation (without a retention slot) Note that two retention slot are used (slot and slot+1)

impl<O, SPI, M> Lr2021<O, SPI, M>

where O: OutputPin, SPI: SpiBus<u8>, M: BusyPin,

pub async fn set_flrc_modulation( &mut self, bitrate: FlrcBitrate, cr: FlrcCr, pulse_shape: PulseShape, ) -> Result<(), Lr2021Error>

Set Modulation parameters: raw bitrate, coding rate and pulse shaping

pub async fn set_flrc_packet( &mut self, params: &FlrcPacketParams, ) -> Result<(), Lr2021Error>

Set FLRC packet parameters: preamble, syncword, header implicit/explicit, CRC and packet length (max 511)

pub async fn set_flrc_syncword( &mut self, sw_num: u8, syncword: u32, is_16b: bool, ) -> Result<(), Lr2021Error>

Configure one of the three possible syncword

pub async fn get_flrc_packet_status( &mut self, ) -> Result<FlrcPacketStatusRsp, Lr2021Error>

Return length of last packet received

pub async fn get_flrc_rx_stats(&mut self) -> Result<FlrcRxStatsRsp, Lr2021Error>

Return basic RX stats

impl<O, SPI, M> Lr2021<O, SPI, M>

where O: OutputPin, SPI: SpiBus<u8>, M: BusyPin,

pub async fn set_ook_modulation( &mut self, bitrate: u32, rx_bw: RxBw, pulse_shape: PulseShape, ) -> Result<(), Lr2021Error>

Set Modulation parameters: raw bitrate, bandwidth and pulse shaping

pub async fn set_ook_packet( &mut self, pre_len_tx: u16, addr_comp: AddrComp, pkt_format: PktFormat, pld_len: u16, crc: Crc, encoding: Encoding, ) -> Result<(), Lr2021Error>

Set OOK packet parameter: preamble length (TX), Address filtering, header implicit/explicit, payload length, CRC and encoding

pub async fn set_ook_detector( &mut self, preamble_pattern: u16, pattern_length: u8, pattern_num_repeats: u8, sw_is_raw: bool, sfd_kind: SfdKind, sfd_length: u8, ) -> Result<(), Lr2021Error>

Set OOK detector: Preamble (pattern/length/repetition), Sync encoding, Start of Frame delimiter

pub async fn set_ook_syncword( &mut self, syncword: u32, bit_order: BitOrder, nb_bits: u8, ) -> Result<(), Lr2021Error>

Configure syncword (value, length and bit order)

pub async fn set_ook_crc( &mut self, polynom: u32, init: u32, ) -> Result<(), Lr2021Error>

Configure OOK polynom and init value

pub async fn set_ook_thr(&mut self, threshold: i8) -> Result<(), Lr2021Error>

Configure OOK Detection absolute threshold Typically add a few dB above the ambiant noise level

pub async fn set_ook_adsb(&mut self) -> Result<(), Lr2021Error>

Configure OOK receiver for ADS-B:

• Modulation: 2Mb/s with 3MHz bandwidth
• Packet: Fixed payload 11B + 3B CRC with inverted manchester encoding
• Detector: Pattern 15b 0x285 and no SFD

pub async fn set_ook_rts(&mut self) -> Result<(), Lr2021Error>

Configure OOK receiver for Somfy RTS:

• Modulation: 1562b/s with 7.4kHz Bandwidth
• Packet: Fixed payload 7B with Manchester encoding and no syncword
• Detector:
  • Pattern is 00001111 repeated twice
  • Start of frame Delimiter is roughly 8 symbol high follow by a 0
  • Corresponds to: 000-0111_1000-0111_1000-01_1111_1110 : pattern 1E (LSB first) repeated twice with SFD

pub async fn get_ook_packet_status( &mut self, ) -> Result<OokPacketStatusRsp, Lr2021Error>

Return stats about last packet received: length, RSSI, LQI

pub async fn get_ook_rx_stats(&mut self) -> Result<OokRxStatsRsp, Lr2021Error>

Return basic RX stats

impl<O, SPI, M> Lr2021<O, SPI, M>

where O: OutputPin, SPI: SpiBus<u8>, M: BusyPin,

pub async fn set_fsk_modulation( &mut self, bitrate: u32, pulse_shape: PulseShape, rx_bw: RxBw, fdev: u32, ) -> Result<(), Lr2021Error>

Set Modulation parameters: raw bitrate, pulse shaping, Bandwidth and fdev

pub async fn set_fsk_packet( &mut self, pbl_len_tx: u16, pbl_len_detect: PblLenDetect, pbl_long: bool, pld_len_unit: PldLenUnit, addr_comp: AddrComp, fsk_pkt_format: FskPktFormat, pld_len: u16, crc: Crc, dc_free: bool, ) -> Result<(), Lr2021Error>

Set packet parameters (preamble, length format, CRC, addressing, whitening)

pub async fn set_fsk_syncword( &mut self, syncword: u64, bit_order: BitOrder, nb_bits: u8, ) -> Result<(), Lr2021Error>

Configure syncword

pub async fn set_fsk_long_prmb_support( &mut self, en: bool, ) -> Result<(), Lr2021Error>

Enable long preamble support in FSK (more than 2048 symbols)

pub async fn get_fsk_packet_status( &mut self, ) -> Result<FskPacketStatusRsp, Lr2021Error>

Return length of last packet received

pub async fn get_fsk_rx_stats(&mut self) -> Result<FskRxStatsRsp, Lr2021Error>

Return basic RX stats

impl<O, SPI, M> Lr2021<O, SPI, M>

where O: OutputPin, SPI: SpiBus<u8>, M: BusyPin,

pub async fn set_zigbee_packet( &mut self, params: &ZigbeePacketParams, ) -> Result<(), Lr2021Error>

Set Zigbee packet parameters: preamble, Bandwidth, Payload length, Address filtering, FCS handling (software/Hardware)

pub async fn set_zigbee_packet_len( &mut self, pld_len: u8, ) -> Result<(), Lr2021Error>

Sets the zigbee packet length without calling set_zigbee_packet which takes longer The function set_zigbee_packet must have been called once before !

pub async fn set_zigbee_address( &mut self, long_dest_addr: u64, short_dest_addr: u16, pan_id: u16, trans_id: u8, ) -> Result<(), Lr2021Error>

Configure the different Zigbee addresses for filtering in RX. Frames that don’t match the addresses raise an address error IRQ and reception is aborted. When a packet is received, the destination address and PAN ID are both checked. Multi-cast is not supported or filtered and must be handled by the host

pub async fn get_zigbee_packet_status( &mut self, ) -> Result<ZigbeePacketStatusRsp, Lr2021Error>

Return length of last packet received

pub async fn get_zigbee_rx_stats( &mut self, ) -> Result<ZigbeeRxStatsRsp, Lr2021Error>

Return basic RX stats

impl<O, SPI, M> Lr2021<O, SPI, M>

where O: OutputPin, SPI: SpiBus<u8>, M: BusyPin,

pub async fn set_zwave_packet( &mut self, params: &ZwavePacketParams, ) -> Result<(), Lr2021Error>

Set ZWave packet parameters: preamble, syncword, header implicit/explicit, CRC and packet length (max 511)

pub async fn set_zwave_home_id(&mut self, id: u32) -> Result<(), Lr2021Error>

Sets the zwave Home ID, used as address filter in RX

pub async fn set_zwave_beam_filt( &mut self, beam_tag: u8, addr_len: AddrLen, node_id: u16, id_hash: u8, ) -> Result<(), Lr2021Error>

Sets the zwave Beam frame filtering

pub async fn set_zwave_scan_config( &mut self, cfg: &ZwaveScanCfg, ) -> Result<(), Lr2021Error>

Configure scan: number of active channel, their mode and frequency

pub async fn start_zwave_scan(&mut self) -> Result<(), Lr2021Error>

Start the ZWave Scan: it will alternate between up to 4 channels to find an incoming packet

pub async fn get_zwave_packet_status( &mut self, ) -> Result<ZwavePacketStatusRsp, Lr2021Error>

Return length of last packet received

pub async fn get_zwave_rx_stats( &mut self, ) -> Result<ZwaveRxStatsRsp, Lr2021Error>

Return basic RX stats

impl<O, SPI, M> Lr2021<O, SPI, M>

where O: OutputPin, SPI: SpiBus<u8>, M: BusyPin,

pub async fn lrfhss_build_packet( &mut self, sync_header_cnt: u8, cr: LrfhssCr, grid: Grid, hopping: Hopping, bw: LrfhssBw, sequence: u16, offset: i8, pld: &[u8], ) -> Result<(), Lr2021Error>

Prepare the LR-FHSS packet

pub async fn set_lrfhss_syncword( &mut self, syncword: u32, ) -> Result<(), Lr2021Error>

Configure Syncword of LRFHSS packet Default value is 0x2C0F7995

pub async fn set_lrfhss_hopping( &mut self, hop_en: bool, freq_hz: bool, pkt_length: u16, nb_used_freqs: u8, nb_hopping_blocks: u8, hops: &[LrfhssHop], ) -> Result<(), Lr2021Error>

Set the LRFHSS hopping table The data parameter should be up to 40 pairs (freq (4B), Nb_symbols (2B))

impl<O, SPI, M> Lr2021<O, SPI, M>

where O: OutputPin, SPI: SpiBus<u8>, M: BusyPin,

pub async fn set_wmbus_packet( &mut self, params: WmbusPacketParams, ) -> Result<(), Lr2021Error>

Set Wmbus packet parameters: preamble, Bandwidth, Payload length, Address filtering

pub async fn set_wmbus_address(&mut self, addr: u64) -> Result<(), Lr2021Error>

Configure the node address for address filtering

pub async fn get_wmbus_packet_status( &mut self, ) -> Result<WmbusPacketStatusRsp, Lr2021Error>

Return info about last packet received: length, CRC error per block, RSSI, LQI

pub async fn get_wmbus_rx_stats( &mut self, ) -> Result<WmbusRxStatsRsp, Lr2021Error>

Return basic RX stats

impl<O, SPI, M> Lr2021<O, SPI, M>

where O: OutputPin, SPI: SpiBus<u8>, M: BusyPin,

pub async fn set_wisun_modulation( &mut self, mode: WisunMode, rx_bw: RxBw, ) -> Result<(), Lr2021Error>

Set Wisun packet parameters: preamble, Bandwidth, Payload length, Address filtering

pub async fn set_wisun_packet( &mut self, params: WisunPacketParams, ) -> Result<(), Lr2021Error>

Set Wisun packet parameters: preamble, Bandwidth, Payload length, Address filtering

pub async fn get_wisun_packet_status( &mut self, ) -> Result<WisunPacketStatusRsp, Lr2021Error>

Return info about last packet received: length, CRC error per block, RSSI, LQI

pub async fn get_wisun_rx_stats( &mut self, ) -> Result<WisunRxStatsRsp, Lr2021Error>

Return basic RX stats (Numer of packet received, Number of error CRC or length)

impl<O, SPI, M> Lr2021<O, SPI, M>

where O: OutputPin, SPI: SpiBus<u8>, M: BusyPin,

pub async fn set_bpsk_modulation( &mut self, bitrate: u32, pulse_shape: PulseShape, diff_mode_en: DiffModeEn, diff_mode_init: bool, diff_mode_parity: bool, ) -> Result<(), Lr2021Error>

Set Modulation parameters: raw bitrate, pulse shaping, Bandwidth and fdev

pub async fn set_bpsk_packet( &mut self, pld_len: u8, bpsk_mode: BpskMode, sigfox_msg: SigfoxMsg, sigfox_rank: SigfoxRank, ) -> Result<(), Lr2021Error>

Set FLRC packet parameters: preamble, syncword, header implicit/explicit, CRC and packet length (max 511)

impl<I, O, SPI> Lr2021<O, SPI, BusyBlocking<I>>

where I: InputPin, O: OutputPin, SPI: SpiBus<u8>,

pub fn new_blocking(nreset: O, busy: I, spi: SPI, nss: O) -> Self

Create a LR2021 Device with blocking access on the busy pin

impl<I, O, SPI> Lr2021<O, SPI, BusyAsync<I>>

where I: InputPin + Wait, O: OutputPin, SPI: SpiBus<u8>,

pub fn new(nreset: O, busy: I, spi: SPI, nss: O) -> Self

Create a LR2021 Device with async busy pin

impl<O, SPI, M> Lr2021<O, SPI, M>

where O: OutputPin, SPI: SpiBus<u8>, M: BusyPin,

pub async fn reset(&mut self) -> Result<(), Lr2021Error>

Reset the chip

pub fn is_busy(&mut self) -> bool

Check if the busy pin is high (debug)

pub fn status(&self) -> Status

Last status (command status, chip mode, interrupt, …)

pub fn buffer(&self) -> &[u8]

Read access to internal buffer

pub fn buffer_mut(&mut self) -> &mut [u8]

Read/Write access to internal buffer

pub fn last_intr(&self) -> Intr

Last captured interrupt status Note: might be incomplete if last command was less than 6 bytes

pub async fn wait_ready(&mut self, timeout: Duration) -> Result<(), Lr2021Error>

Wait for LR2021 to be ready for a command, i.e. busy pin low

pub async fn cmd_wr_begin(&mut self, req: &[u8]) -> Result<(), Lr2021Error>

Write the beginning of a command, allowing to fill with variable length fields

pub async fn cmd_wr(&mut self, req: &[u8]) -> Result<(), Lr2021Error>

Write a command

pub async fn cmd_rd( &mut self, req: &[u8], rsp: &mut [u8], ) -> Result<(), Lr2021Error>

Write a command and read response Rsp must be n bytes where n is the number of expected byte

pub async fn cmd_data_wr( &mut self, opcode: &[u8], data: &[u8], ) -> Result<(), Lr2021Error>

Write a command with vairable length payload Any feedback data will be available in side the local buffer

pub async fn cmd_data_rw( &mut self, opcode: &[u8], data: &mut [u8], ) -> Result<(), Lr2021Error>

Write a command with variable length payload, and save result provided buffer

pub async fn cmd_buf_wr(&mut self, len: usize) -> Result<(), Lr2021Error>

Send content of the local buffer as a command

pub async fn cmd_buf_rd( &mut self, len: usize, rsp: &mut [u8], ) -> Result<(), Lr2021Error>

Send content of the local buffer as a command and read a response

pub async fn wake_up(&mut self) -> Result<(), Lr2021Error>

Wake-up the chip from a sleep mode (Set NSS low until busy goes low)