Struct lpc845_pac::sct0::dma1request::W [−][src]
pub struct W(_);
Expand description
Register DMA1REQUEST
writer
Implementations
Bits 0:5 - If bit n is one, event n triggers DMA request 1 (event 0 = bit 0, event 1 = bit 1, etc.). The number of bits = number of events in this SCT.
Bit 30 - A 1 in this bit triggers DMA request 1 when it loads the Match L/Unified registers from the Reload L/Unified registers.
Bit 31 - This read-only bit indicates the state of DMA Request 1. Note that if the related DMA channel is enabled and properly set up, it is unlikely that software will see this flag, it will be cleared rapidly by the DMA service. The flag remaining set could point to an issue with DMA setup.
Methods from Deref<Target = W<DMA1REQUEST_SPEC>>
Trait Implementations
Performs the conversion.