Enum lpc845_pac::ctimer0::tcr::CRST_A [−][src]
pub enum CRST_A {
DISABLED,
ENABLED,
}
Expand description
Counter reset.
Value on reset: 0
Variants
0: Disabled. Do nothing.
1: Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of the APB bus clock. The counters remain reset until TCR[1] is returned to zero.