Struct lpc845_pac::usart0::intenset::W [−][src]
pub struct W(_);
Expand description
Register INTENSET
writer
Implementations
Bit 0 - When 1, enables an interrupt when there is a received character available to be read from the RXDAT register.
Bit 2 - When 1, enables an interrupt when the TXDAT register is available to take another character to transmit.
Bit 3 - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1).
Bit 5 - When 1, enables an interrupt when there is a change in the state of the CTS input.
Bit 6 - When 1, enables an interrupt when the transmitter is fully disabled as indicated by the TXDISINT flag in STAT. See description of the TXDISINT bit for details.
Bit 8 - When 1, enables an interrupt when an overrun error occurred.
Bit 11 - When 1, enables an interrupt when a change of state has occurred in the detection of a received break condition (break condition asserted or deasserted).
Bit 12 - When 1, enables an interrupt when a received start bit has been detected.
Bit 13 - When 1, enables an interrupt when a framing error has been detected.
Bit 14 - When 1, enables an interrupt when a parity error has been detected.
Bit 15 - When 1, enables an interrupt when noise is detected.
Bit 16 - When 1, enables an interrupt when an autobaud error occurs.
Methods from Deref<Target = W<INTENSET_SPEC>>
Trait Implementations
Performs the conversion.