[−][src]Struct lpc845_pac::spi0::RegisterBlock
Register block
Fields
cfg: CFG
0x00 - SPI Configuration register
dly: DLY
0x04 - SPI Delay register
stat: STAT
0x08 - SPI Status. Some status flags can be cleared by writing a 1 to that bit position
intenset: INTENSET
0x0c - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
intenclr: INTENCLR
0x10 - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared.
rxdat: RXDAT
0x14 - SPI Receive Data
txdatctl: TXDATCTL
0x18 - SPI Transmit Data with Control
txdat: TXDAT
0x1c - SPI Transmit Data.
txctl: TXCTL
0x20 - SPI Transmit Control
div: DIV
0x24 - SPI clock Divider
intstat: INTSTAT
0x28 - SPI Interrupt Status
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