Struct lpc82x::sct::config::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

fn reset_value() -> W

Reset value of the register

unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

fn unify(&mut self) -> _UNIFYW

Bit 0 - SCT operation

fn clkmode(&mut self) -> _CLKMODEW

Bits 1:2 - SCT clock mode

fn cksel(&mut self) -> _CKSELW

Bits 3:6 - SCT clock select

fn norelaod_l(&mut self) -> _NORELAOD_LW

Bit 7 - A 1 in this bit prevents the lower match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.

fn noreload_h(&mut self) -> _NORELOAD_HW

Bit 8 - A 1 in this bit prevents the higher match registers from being reloaded from their respective reload registers. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.

fn insync(&mut self) -> _INSYNCW

Bits 9:16 - Synchronization for input N (bit 9 = input 0, bit 10 = input 1,..., bit 12 = input 3); all other bits are reserved. A 1 in one of these bits subjects the corresponding input to synchronization to the SCT clock, before it is used to create an event. If an input is synchronous to the SCT clock, keep its bit 0 for faster response. When the CKMODE field is 1x, the bit in this field, corresponding to the input selected by the CKSEL field, is not used.

fn autolimit_l(&mut self) -> _AUTOLIMIT_LW

Bit 17 - A one in this bit causes a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit applies to both the higher and lower registers when the UNIFY bit is set.

fn autolimit_h(&mut self) -> _AUTOLIMIT_HW

Bit 18 - A one in this bit will cause a match on match register 0 to be treated as a de-facto LIMIT condition without the need to define an associated event. As with any LIMIT event, this automatic limit causes the counter to be cleared to zero in uni-directional mode or to change the direction of count in bi-directional mode. Software can write to set or clear this bit at any time. This bit is not used when the UNIFY bit is set.