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RegisterBlock

lpc82x_pac::syscon

Struct RegisterBlock 

Source 
pub struct RegisterBlock {
Show 40 fields
    pub sysmemremap: Reg<SYSMEMREMAP_SPEC>,
    pub presetctrl: Reg<PRESETCTRL_SPEC>,
    pub syspllctrl: Reg<SYSPLLCTRL_SPEC>,
    pub syspllstat: Reg<SYSPLLSTAT_SPEC>,
    pub sysoscctrl: Reg<SYSOSCCTRL_SPEC>,
    pub wdtoscctrl: Reg<WDTOSCCTRL_SPEC>,
    pub ircctrl: Reg<IRCCTRL_SPEC>,
    pub sysrststat: Reg<SYSRSTSTAT_SPEC>,
    pub syspllclksel: Reg<SYSPLLCLKSEL_SPEC>,
    pub syspllclkuen: Reg<SYSPLLCLKUEN_SPEC>,
    pub mainclksel: Reg<MAINCLKSEL_SPEC>,
    pub mainclkuen: Reg<MAINCLKUEN_SPEC>,
    pub sysahbclkdiv: Reg<SYSAHBCLKDIV_SPEC>,
    pub sysahbclkctrl: Reg<SYSAHBCLKCTRL_SPEC>,
    pub uartclkdiv: Reg<UARTCLKDIV_SPEC>,
    pub clkoutsel: Reg<CLKOUTSEL_SPEC>,
    pub clkoutuen: Reg<CLKOUTUEN_SPEC>,
    pub clkoutdiv: Reg<CLKOUTDIV_SPEC>,
    pub uartfrgdiv: Reg<UARTFRGDIV_SPEC>,
    pub uartfrgmult: Reg<UARTFRGMULT_SPEC>,
    pub exttracecmd: Reg<EXTTRACECMD_SPEC>,
    pub pioporcap0: Reg<PIOPORCAP0_SPEC>,
    pub ioconclkdiv6: Reg<IOCONCLKDIV6_SPEC>,
    pub ioconclkdiv5: Reg<IOCONCLKDIV5_SPEC>,
    pub ioconclkdiv4: Reg<IOCONCLKDIV4_SPEC>,
    pub ioconclkdiv3: Reg<IOCONCLKDIV3_SPEC>,
    pub ioconclkdiv2: Reg<IOCONCLKDIV2_SPEC>,
    pub ioconclkdiv1: Reg<IOCONCLKDIV1_SPEC>,
    pub ioconclkdiv0: Reg<IOCONCLKDIV0_SPEC>,
    pub bodctrl: Reg<BODCTRL_SPEC>,
    pub systckcal: Reg<SYSTCKCAL_SPEC>,
    pub irqlatency: Reg<IRQLATENCY_SPEC>,
    pub nmisrc: Reg<NMISRC_SPEC>,
    pub pintsel: [Reg<PINTSEL_SPEC>; 8],
    pub starterp0: Reg<STARTERP0_SPEC>,
    pub starterp1: Reg<STARTERP1_SPEC>,
    pub pdsleepcfg: Reg<PDSLEEPCFG_SPEC>,
    pub pdawakecfg: Reg<PDAWAKECFG_SPEC>,
    pub pdruncfg: Reg<PDRUNCFG_SPEC>,
    pub device_id: Reg<DEVICE_ID_SPEC>,
    /* private fields */

}
Expand description

Register block

Fields§

§sysmemremap: Reg<SYSMEMREMAP_SPEC>

0x00 - System Remap register

§presetctrl: Reg<PRESETCTRL_SPEC>

0x04 - Peripheral reset control register

§syspllctrl: Reg<SYSPLLCTRL_SPEC>

0x08 - PLL control

§syspllstat: Reg<SYSPLLSTAT_SPEC>

0x0c - PLL status

§sysoscctrl: Reg<SYSOSCCTRL_SPEC>

0x20 - system oscillator control

§wdtoscctrl: Reg<WDTOSCCTRL_SPEC>

0x24 - Watchdog oscillator control

§ircctrl: Reg<IRCCTRL_SPEC>

0x28 - IRC control

§sysrststat: Reg<SYSRSTSTAT_SPEC>

0x30 - System reset status register

§syspllclksel: Reg<SYSPLLCLKSEL_SPEC>

0x40 - System PLL clock source select register

§syspllclkuen: Reg<SYSPLLCLKUEN_SPEC>

0x44 - System PLL clock source update enable register

§mainclksel: Reg<MAINCLKSEL_SPEC>

0x70 - Main clock source select

§mainclkuen: Reg<MAINCLKUEN_SPEC>

0x74 - Main clock source update enable

§sysahbclkdiv: Reg<SYSAHBCLKDIV_SPEC>

0x78 - System clock divider

§sysahbclkctrl: Reg<SYSAHBCLKCTRL_SPEC>

0x80 - System clock control

§uartclkdiv: Reg<UARTCLKDIV_SPEC>

0x94 - USART clock divider

§clkoutsel: Reg<CLKOUTSEL_SPEC>

0xe0 - CLKOUT clock source select

§clkoutuen: Reg<CLKOUTUEN_SPEC>

0xe4 - CLKOUT clock source update enable

§clkoutdiv: Reg<CLKOUTDIV_SPEC>

0xe8 - PLL control

§uartfrgdiv: Reg<UARTFRGDIV_SPEC>

0xf0 - USART1 to USART4 common fractional generator divider value

§uartfrgmult: Reg<UARTFRGMULT_SPEC>

0xf4 - USART common fractional generator divider value

§exttracecmd: Reg<EXTTRACECMD_SPEC>

0xfc - External trace buffer command register

§pioporcap0: Reg<PIOPORCAP0_SPEC>

0x100 - POR captured PIO status 0

§ioconclkdiv6: Reg<IOCONCLKDIV6_SPEC>

0x134 - Peripheral clock 6 to the IOCON block for programmable glitch filter

§ioconclkdiv5: Reg<IOCONCLKDIV5_SPEC>

0x138 - Peripheral clock 6 to the IOCON block for programmable glitch filter

§ioconclkdiv4: Reg<IOCONCLKDIV4_SPEC>

0x13c - Peripheral clock 4 to the IOCON block for programmable glitch filter

§ioconclkdiv3: Reg<IOCONCLKDIV3_SPEC>

0x140 - Peripheral clock 3 to the IOCON block for programmable glitch filter

§ioconclkdiv2: Reg<IOCONCLKDIV2_SPEC>

0x144 - Peripheral clock 2 to the IOCON block for programmable glitch filter

§ioconclkdiv1: Reg<IOCONCLKDIV1_SPEC>

0x148 - Peripheral clock 1 to the IOCON block for programmable glitch filter

§ioconclkdiv0: Reg<IOCONCLKDIV0_SPEC>

0x14c - Peripheral clock 0 to the IOCON block for programmable glitch filter

§bodctrl: Reg<BODCTRL_SPEC>

0x150 - BOD control register

§systckcal: Reg<SYSTCKCAL_SPEC>

0x154 - System tick timer calibration register

§irqlatency: Reg<IRQLATENCY_SPEC>

0x170 - IRQ latency register

§nmisrc: Reg<NMISRC_SPEC>

0x174 - NMI source selection register

§pintsel: [Reg<PINTSEL_SPEC>; 8]

0x178..0x198 - Pin interrupt select registers N

§starterp0: Reg<STARTERP0_SPEC>

0x204 - Start logic 0 pin wake-up enable register 0

§starterp1: Reg<STARTERP1_SPEC>

0x214 - Start logic 1 interrupt wake-up enable register

§pdsleepcfg: Reg<PDSLEEPCFG_SPEC>

0x230 - Deep-sleep configuration register

§pdawakecfg: Reg<PDAWAKECFG_SPEC>

0x234 - Wake-up configuration register

§pdruncfg: Reg<PDRUNCFG_SPEC>

0x238 - Power configuration register

§device_id: Reg<DEVICE_ID_SPEC>

0x3f8 - Part ID register

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