Module lpc82x_pac::adc0::seq_ctrl

ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n.

Structs

BURST_W	Write proxy for field BURST
CHANNELS_W	Write proxy for field CHANNELS
LOWPRIO_W	Write proxy for field LOWPRIO
MODE_W	Write proxy for field MODE
SEQ_ENA_W	Write proxy for field SEQ_ENA
SINGLESTEP_W	Write proxy for field SINGLESTEP
START_W	Write proxy for field START
SYNCBYPASS_W	Write proxy for field SYNCBYPASS
TRIGGER_W	Write proxy for field TRIGGER
TRIGPOL_W	Write proxy for field TRIGPOL

Enums

LOWPRIO_A	Set priority for sequence A.
MODE_A	Indicates whether the primary method for retrieving conversion results for this sequence will be accomplished via reading the global data register (SEQA_GDAT) at the end of each conversion, or the individual channel result registers at the end of the entire sequence. Impacts when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which overrun conditions contribute to an overrun interrupt as described below.
SEQ_ENA_A	Sequence Enable. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled. In order to avoid spuriously triggering the sequence, care should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered immediately upon being enabled.
SYNCBYPASS_A	Setting this bit allows the hardware trigger input to bypass synchronization flip-flop stages and therefore shorten the time between the trigger input signal and the start of a conversion. There are slightly different criteria for whether or not this bit can be set depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): Synchronization may be bypassed (this bit may be set) if the selected trigger source is already synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). Whether this bit is set or not, a trigger pulse must be maintained for at least one system clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be maintained for one system clock period.
TRIGPOL_A	Select the polarity of the selected input trigger for this conversion sequence. In order to avoid generating a spurious trigger, it is recommended writing to this field only when SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write.

Type Definitions

BURST_R	Reader of field BURST
CHANNELS_R	Reader of field CHANNELS
LOWPRIO_R	Reader of field LOWPRIO
MODE_R	Reader of field MODE
R	Reader of register SEQ_CTRL%s
SEQ_ENA_R	Reader of field SEQ_ENA
SINGLESTEP_R	Reader of field SINGLESTEP
START_R	Reader of field START
SYNCBYPASS_R	Reader of field SYNCBYPASS
TRIGGER_R	Reader of field TRIGGER
TRIGPOL_R	Reader of field TRIGPOL
W	Writer for register SEQ_CTRL%s