[−][src]Module lpc82x_pac::adc0
LPC82x 12-bit ADC controller (ADC)
Modules
chan_thrsel | ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel |
ctrl | ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. |
dat | ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. |
flags | ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). |
inten | ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. |
seq_ctrl | ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. |
seq_gdat | ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. |
thr0_low | ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. |
thr0_high | ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. |
thr1_low | ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. |
thr1_high | ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. |
trm | ADC Startup register. |
Structs
RegisterBlock | Register block |
Type Definitions
CHAN_THRSEL | ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel |
CTRL | ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. |
DAT | ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. |
FLAGS | ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). |
INTEN | ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. |
SEQ_CTRL | ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. |
SEQ_GDAT | ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. |
THR0_LOW | ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. |
THR0_HIGH | ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. |
THR1_LOW | ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. |
THR1_HIGH | ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. |
TRM | ADC Startup register. |