pub type CLK_DIV_W<'a, const O: u8> = FieldWriter<'a, u32, PIO0_11_SPEC, u8, CLK_DIV_A, 3, O>;
Field CLK_DIV writer - Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
CLK_DIV
IOCONCLKDIV0
IOCONCLKDIV1
IOCONCLKDIV2
IOCONCLKDIV3
IOCONCLKDIV4
IOCONCLKDIV5
IOCONCLKDIV6