pub type CLK_DIV_R = FieldReader<u8, CLK_DIV_A>;
Expand description
Field CLK_DIV
reader - Select peripheral clock divider for input filter sampling clock. Value 0x7 is reserved.
Implementations§
source§impl CLK_DIV_R
impl CLK_DIV_R
sourcepub fn is_clk_div_0(&self) -> bool
pub fn is_clk_div_0(&self) -> bool
Checks if the value of the field is CLK_DIV_0
sourcepub fn is_clk_div_1(&self) -> bool
pub fn is_clk_div_1(&self) -> bool
Checks if the value of the field is CLK_DIV_1
sourcepub fn is_clk_div_2(&self) -> bool
pub fn is_clk_div_2(&self) -> bool
Checks if the value of the field is CLK_DIV_2
sourcepub fn is_clk_div_3(&self) -> bool
pub fn is_clk_div_3(&self) -> bool
Checks if the value of the field is CLK_DIV_3
sourcepub fn is_clk_div_4(&self) -> bool
pub fn is_clk_div_4(&self) -> bool
Checks if the value of the field is CLK_DIV_4
sourcepub fn is_clk_div_5(&self) -> bool
pub fn is_clk_div_5(&self) -> bool
Checks if the value of the field is CLK_DIV_5
sourcepub fn is_clk_div_6(&self) -> bool
pub fn is_clk_div_6(&self) -> bool
Checks if the value of the field is CLK_DIV_6