[−][src]Type Definition lpc55s6x_pac::syscon::PLL0CLKDIV
type PLL0CLKDIV = Reg<u32, _PLL0CLKDIV>;
PLL0 clock divider
This register you can read
, reset
, write
, write_with_zero
, modify
. See API.
For information about avaliable fields see pll0clkdiv module
Trait Implementations
impl Readable for PLL0CLKDIV
[src]
read()
method returns pll0clkdiv::R reader structure
impl Writable for PLL0CLKDIV
[src]
write(|w| ..)
method takes pll0clkdiv::W writer structure
impl ResetValue for PLL0CLKDIV
[src]
Register PLL0CLKDIV reset()
's with value 0x4000_0000