[−][src]Type Definition lpc55s6x_pac::syscon::FCCLKSEL7
type FCCLKSEL7 = Reg<u32, _FCCLKSEL7>;
Flexcomm Interface 7 clock source select for Fractional Rate Divider
This register you can read
, reset
, write
, write_with_zero
, modify
. See API.
For information about avaliable fields see fcclksel7 module
Trait Implementations
impl Readable for FCCLKSEL7
[src]
read()
method returns fcclksel7::R reader structure
impl Writable for FCCLKSEL7
[src]
write(|w| ..)
method takes fcclksel7::W writer structure
impl ResetValue for FCCLKSEL7
[src]
Register FCCLKSEL7 reset()
's with value 0x07