Type Definition lpc55s6x_pac::pmc::resetcause::W

type W = W<u32, RESETCAUSE>;

Writer for register RESETCAUSE

Methods

impl W

pub fn por(&mut self) -> POR_W

Bit 0 - 1 : The last chip reset was caused by a Power On Reset. Write '1' to clear this bit.

pub fn padreset(&mut self) -> PADRESET_W

Bit 1 - 1 : The last chip reset was caused by a Pin Reset. Write '1' to clear this bit.

pub fn bodreset(&mut self) -> BODRESET_W

Bit 2 - 1 : The last chip reset was caused by a Brown Out Detector (BoD), either VBAT BoD or Core Logic BoD. Write '1' to clear this bit.

pub fn systemreset(&mut self) -> SYSTEMRESET_W

Bit 3 - 1 : The last chip reset was caused by a System Reset requested by the ARM CPU. Write '1' to clear this bit.

pub fn wdtreset(&mut self) -> WDTRESET_W

Bit 4 - 1 : The last chip reset was caused by the Watchdog Timer. Write '1' to clear this bit.

pub fn swrreset(&mut self) -> SWRRESET_W

Bit 5 - 1 : The last chip reset was caused by a Software. Write '1' to clear this bit.

pub fn dpdreset_wakeupio(&mut self) -> DPDRESET_WAKEUPIO_W

Bit 6 - 1 : The last chip reset was caused by a Wake-up I/O reset event during DEEP POWER DOWN mode. Write '1' to clear this bit.

pub fn dpdreset_rtc(&mut self) -> DPDRESET_RTC_W

Bit 7 - 1 : The last chip reset was caused by an RTC (either RTC Alarm or RTC wake up) reset event during DEEP POWER DOWN mode. Write '1' to clear this bit.

pub fn dpdreset_ostimer(&mut self) -> DPDRESET_OSTIMER_W

Bit 8 - 1 : The last chip reset was caused by a OS Event Timer reset eventduring DEEP POWER DOWN mode. Write '1' to clear this bit.