[−][src]Type Definition lpc55s6x_pac::usbphy::ctrl_set::R
type R = R<u32, CTRL_SET>;
Reader of register CTRL_SET
Methods
impl R
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pub fn enhostdiscondetect(&self) -> ENHOSTDISCONDETECT_R
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Bit 1 - For host mode, enables high-speed disconnect detector
pub fn hostdiscondetect_irq(&self) -> HOSTDISCONDETECT_IRQ_R
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Bit 3 - Indicates that the device has disconnected in High-Speed mode
pub fn endevplugindet(&self) -> ENDEVPLUGINDET_R
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Bit 4 - Enables non-standard resistive plugged-in detection This bit field controls connection of nominal 200kohm resistors to both the USB_DP and USB_DM pins as one method of detecting when a USB cable is attached in device mode
pub fn devplugin_irq(&self) -> DEVPLUGIN_IRQ_R
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Bit 12 - Indicates that the device is connected
pub fn enutmilevel2(&self) -> ENUTMILEVEL2_R
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Bit 14 - Enables UTMI+ Level 2 operation for the USB HS PHY
pub fn enutmilevel3(&self) -> ENUTMILEVEL3_R
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Bit 15 - Enables UTMI+ Level 3 operation for the USB HS PHY
pub fn autoresume_en(&self) -> AUTORESUME_EN_R
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Bit 18 - Enable the auto resume feature, when set, HW will use 32KHz clock to send Resume to respond to the device remote wakeup(for host mode only)
pub fn enautoclr_clkgate(&self) -> ENAUTOCLR_CLKGATE_R
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Bit 19 - Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended
pub fn enautoclr_phy_pwd(&self) -> ENAUTOCLR_PHY_PWD_R
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Bit 20 - Enables the feature to auto-clear the PWD register bits in PWD if there is wakeup event while USB is suspended
pub fn fsdll_rst_en(&self) -> FSDLL_RST_EN_R
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Bit 24 - Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.
pub fn otg_id_value(&self) -> OTG_ID_VALUE_R
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Bit 27 - Indicates the results of USB_ID pin while monitoring the cable plugged into the Micro- or Mini-AB receptacle
pub fn host_force_ls_se0(&self) -> HOST_FORCE_LS_SE0_R
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Bit 28 - Forces the next FS packet that is transmitted to have a EOP with low-speed timing
pub fn utmi_suspendm(&self) -> UTMI_SUSPENDM_R
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Bit 29 - Used by the PHY to indicate a powered-down state
pub fn clkgate(&self) -> CLKGATE_R
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Bit 30 - Gate UTMI Clocks
pub fn sftrst(&self) -> SFTRST_R
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Bit 31 - Writing a 1 to this bit will soft-reset the PWD, TX, RX, and CTRL registers