pub struct RegisterBlock {Show 21 fields
pub cfg1: CFG1,
pub cfg2: CFG2,
pub stat: STAT,
pub div: DIV,
pub secchannel0: SECCHANNEL,
pub secchannel1: SECCHANNEL,
pub secchannel2: SECCHANNEL,
pub fifocfg: FIFOCFG,
pub fifostat: FIFOSTAT,
pub fifotrig: FIFOTRIG,
pub fifointenset: FIFOINTENSET,
pub fifointenclr: FIFOINTENCLR,
pub fifointstat: FIFOINTSTAT,
pub fifowr: FIFOWR,
pub fifowr48h: FIFOWR48H,
pub fiford: FIFORD,
pub fiford48h: FIFORD48H,
pub fifordnopop: FIFORDNOPOP,
pub fiford48hnopop: FIFORD48HNOPOP,
pub fifosize: FIFOSIZE,
pub id: ID,
/* private fields */
}Expand description
Register block
Fields§
§cfg1: CFG10xc00 - Configuration register 1 for the primary channel pair.
cfg2: CFG20xc04 - Configuration register 2 for the primary channel pair.
stat: STAT0xc08 - Status register for the primary channel pair.
div: DIV0xc1c - Clock divider, used by all channel pairs.
secchannel0: SECCHANNEL0xc20..0xc2c - no description available.
secchannel1: SECCHANNEL0xc40..0xc4c - no description available.
secchannel2: SECCHANNEL0xc60..0xc6c - no description available.
fifocfg: FIFOCFG0xe00 - FIFO configuration and enable register.
fifostat: FIFOSTAT0xe04 - FIFO status register.
fifotrig: FIFOTRIG0xe08 - FIFO trigger settings for interrupt and DMA request.
fifointenset: FIFOINTENSET0xe10 - FIFO interrupt enable set (enable) and read register.
fifointenclr: FIFOINTENCLR0xe14 - FIFO interrupt enable clear (disable) and read register.
fifointstat: FIFOINTSTAT0xe18 - FIFO interrupt status register.
fifowr: FIFOWR0xe20 - FIFO write data.
fifowr48h: FIFOWR48H0xe24 - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
fiford: FIFORD0xe30 - FIFO read data.
fiford48h: FIFORD48H0xe34 - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
fifordnopop: FIFORDNOPOP0xe40 - FIFO data read with no FIFO pop.
fiford48hnopop: FIFORD48HNOPOP0xe44 - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.
fifosize: FIFOSIZE0xe48 - FIFO size register.
id: ID0xffc - I2S Module identification.