RegisterBlock

lpc55_pac::usbphy

Struct RegisterBlock 

Source 
#[repr(C)]
pub struct RegisterBlock {
Show 29 fields
    pub pwd: Reg<PWD_SPEC>,
    pub pwd_set: Reg<PWD_SET_SPEC>,
    pub pwd_clr: Reg<PWD_CLR_SPEC>,
    pub pwd_tog: Reg<PWD_TOG_SPEC>,
    pub tx: Reg<TX_SPEC>,
    pub tx_set: Reg<TX_SET_SPEC>,
    pub tx_clr: Reg<TX_CLR_SPEC>,
    pub tx_tog: Reg<TX_TOG_SPEC>,
    pub rx: Reg<RX_SPEC>,
    pub rx_set: Reg<RX_SET_SPEC>,
    pub rx_clr: Reg<RX_CLR_SPEC>,
    pub rx_tog: Reg<RX_TOG_SPEC>,
    pub ctrl: Reg<CTRL_SPEC>,
    pub ctrl_set: Reg<CTRL_SET_SPEC>,
    pub ctrl_clr: Reg<CTRL_CLR_SPEC>,
    pub ctrl_tog: Reg<CTRL_TOG_SPEC>,
    pub status: Reg<STATUS_SPEC>,
    pub pll_sic: Reg<PLL_SIC_SPEC>,
    pub pll_sic_set: Reg<PLL_SIC_SET_SPEC>,
    pub pll_sic_clr: Reg<PLL_SIC_CLR_SPEC>,
    pub pll_sic_tog: Reg<PLL_SIC_TOG_SPEC>,
    pub usb1_vbus_detect: Reg<USB1_VBUS_DETECT_SPEC>,
    pub usb1_vbus_detect_set: Reg<USB1_VBUS_DETECT_SET_SPEC>,
    pub usb1_vbus_detect_clr: Reg<USB1_VBUS_DETECT_CLR_SPEC>,
    pub usb1_vbus_detect_tog: Reg<USB1_VBUS_DETECT_TOG_SPEC>,
    pub anactrl: Reg<ANACTRL_SPEC>,
    pub anactrl_set: Reg<ANACTRL_SET_SPEC>,
    pub anactrl_clr: Reg<ANACTRL_CLR_SPEC>,
    pub anactrl_tog: Reg<ANACTRL_TOG_SPEC>,
    /* private fields */

}
Expand description

Register block

Fields§

§pwd: Reg<PWD_SPEC>

0x00 - USB PHY Power-Down Register

§pwd_set: Reg<PWD_SET_SPEC>

0x04 - USB PHY Power-Down Register

§pwd_clr: Reg<PWD_CLR_SPEC>

0x08 - USB PHY Power-Down Register

§pwd_tog: Reg<PWD_TOG_SPEC>

0x0c - USB PHY Power-Down Register

§tx: Reg<TX_SPEC>

0x10 - USB PHY Transmitter Control Register

§tx_set: Reg<TX_SET_SPEC>

0x14 - USB PHY Transmitter Control Register

§tx_clr: Reg<TX_CLR_SPEC>

0x18 - USB PHY Transmitter Control Register

§tx_tog: Reg<TX_TOG_SPEC>

0x1c - USB PHY Transmitter Control Register

§rx: Reg<RX_SPEC>

0x20 - USB PHY Receiver Control Register

§rx_set: Reg<RX_SET_SPEC>

0x24 - USB PHY Receiver Control Register

§rx_clr: Reg<RX_CLR_SPEC>

0x28 - USB PHY Receiver Control Register

§rx_tog: Reg<RX_TOG_SPEC>

0x2c - USB PHY Receiver Control Register

§ctrl: Reg<CTRL_SPEC>

0x30 - USB PHY General Control Register

§ctrl_set: Reg<CTRL_SET_SPEC>

0x34 - USB PHY General Control Register

§ctrl_clr: Reg<CTRL_CLR_SPEC>

0x38 - USB PHY General Control Register

§ctrl_tog: Reg<CTRL_TOG_SPEC>

0x3c - USB PHY General Control Register

§status: Reg<STATUS_SPEC>

0x40 - USB PHY Status Register

§pll_sic: Reg<PLL_SIC_SPEC>

0xa0 - USB PHY PLL Control/Status Register

§pll_sic_set: Reg<PLL_SIC_SET_SPEC>

0xa4 - USB PHY PLL Control/Status Register

§pll_sic_clr: Reg<PLL_SIC_CLR_SPEC>

0xa8 - USB PHY PLL Control/Status Register

§pll_sic_tog: Reg<PLL_SIC_TOG_SPEC>

0xac - USB PHY PLL Control/Status Register

§usb1_vbus_detect: Reg<USB1_VBUS_DETECT_SPEC>

0xc0 - USB PHY VBUS Detect Control Register

§usb1_vbus_detect_set: Reg<USB1_VBUS_DETECT_SET_SPEC>

0xc4 - USB PHY VBUS Detect Control Register

§usb1_vbus_detect_clr: Reg<USB1_VBUS_DETECT_CLR_SPEC>

0xc8 - USB PHY VBUS Detect Control Register

§usb1_vbus_detect_tog: Reg<USB1_VBUS_DETECT_TOG_SPEC>

0xcc - USB PHY VBUS Detect Control Register

§anactrl: Reg<ANACTRL_SPEC>

0x100 - USB PHY Analog Control Register

§anactrl_set: Reg<ANACTRL_SET_SPEC>

0x104 - USB PHY Analog Control Register

§anactrl_clr: Reg<ANACTRL_CLR_SPEC>

0x108 - USB PHY Analog Control Register

§anactrl_tog: Reg<ANACTRL_TOG_SPEC>

0x10c - USB PHY Analog Control Register

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